ir/tests/debug/memop_001.irt

--TEST--
001: Memory update (binary op with const)
--ARGS--
-S
--CODE--
{
	int32_t c = 0x80;
	l_1 = START(l_5);
	int32_t y = PARAM(l_1, "y", 1);
	int32_t v = VAR(l_1, "_spill_");
	l_2 = VSTORE(l_1, v, y);
	int32_t z, l_3 = VLOAD(l_2, v);
	int32_t ret = AND(z, c);
	l_4 = VSTORE(l_3, v, ret);
	l_5 = RETURN(l_4);
}
--EXPECT--
test:
	subq $8, %rsp
	movl %edi, (%rsp)
	andl $0x80, (%rsp)
	addq $8, %rsp
	retq
Allow memory update instructions (without loading into register) 2022-04-22 00:40:10 +02:00			`--TEST--`
Add support for instructions that modify result directly in memory 2022-05-18 20:49:08 +02:00			`001: Memory update (binary op with const)`
Allow memory update instructions (without loading into register) 2022-04-22 00:40:10 +02:00			`--ARGS--`
			`-S`
			`--CODE--`
			`{`
			`int32_t c = 0x80;`
			`l_1 = START(l_5);`
			`int32_t y = PARAM(l_1, "y", 1);`
			`int32_t v = VAR(l_1, "_spill_");`
			`l_2 = VSTORE(l_1, v, y);`
			`int32_t z, l_3 = VLOAD(l_2, v);`
			`int32_t ret = AND(z, c);`
			`l_4 = VSTORE(l_3, v, ret);`
			`l_5 = RETURN(l_4);`
			`}`
			`--EXPECT--`
			`test:`
			`subq $8, %rsp`
			`movl %edi, (%rsp)`
			`andl $0x80, (%rsp)`
			`addq $8, %rsp`
			`retq`