ir/tests/debug/sccp_001.irt

--TEST--
SCCP 001
--TARGET--
x86_64
--ARGS--
-S
--CODE--
{
	int64_t i_1 = 10;
	int64_t i_4 = 4;
	l_1 = START(l_2);
	int64_t z1 = BSWAP(i_1);
	l_2 = RETURN(l_1, z1);
}
--EXPECT--
test:
	movl $0xa, %eax
	bswapq %rax
	retq
Add more tests 2022-04-21 23:11:34 +02:00			`--TEST--`
			`SCCP 001`
Allow multi-target test suite 2022-05-25 16:38:22 +02:00			`--TARGET--`
			`x86_64`
Add more tests 2022-04-21 23:11:34 +02:00			`--ARGS--`
			`-S`
			`--CODE--`
			`{`
			`int64_t i_1 = 10;`
			`int64_t i_4 = 4;`
			`l_1 = START(l_2);`
			`int64_t z1 = BSWAP(i_1);`
			`l_2 = RETURN(l_1, z1);`
			`}`
			`--EXPECT--`
			`test:`
Uze zero extended "mov" to load 64-bit register ("mov $u32, %r32") 2023-02-17 16:11:13 +01:00			`movl $0xa, %eax`
Add more tests 2022-04-21 23:11:34 +02:00			`bswapq %rax`
			`retq`