2022-11-08 09:32:46 +01:00
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/*
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* IR - Lightweight JIT Compilation Framework
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* (Native code generator based on DynAsm)
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* Copyright (C) 2022 Zend by Perforce.
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* Authors: Dmitry Stogov <dmitry@php.net>
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*/
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2022-10-26 21:06:07 +02:00
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#include "ir.h"
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2022-10-26 21:52:19 +02:00
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#if defined(IR_TARGET_X86) || defined(IR_TARGET_X64)
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# include "ir_x86.h"
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#elif defined(IR_TARGET_AARCH64)
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# include "ir_aarch64.h"
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#else
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# error "Unknown IR target"
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#endif
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#include "ir_private.h"
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2023-02-21 00:19:03 +01:00
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#ifndef _WIN32
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# include <dlfcn.h>
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#else
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# define WIN32_LEAN_AND_MEAN
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# include <windows.h>
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# include <psapi.h>
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#endif
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2022-10-26 21:52:19 +02:00
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2022-10-26 21:06:07 +02:00
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#define DASM_M_GROW(ctx, t, p, sz, need) \
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do { \
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size_t _sz = (sz), _need = (need); \
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if (_sz < _need) { \
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if (_sz < 16) _sz = 16; \
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while (_sz < _need) _sz += _sz; \
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(p) = (t *)ir_mem_realloc((p), _sz); \
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(sz) = _sz; \
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} \
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} while(0)
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#define DASM_M_FREE(ctx, p, sz) ir_mem_free(p)
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#if IR_DEBUG
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# define DASM_CHECKS
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#endif
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2022-10-26 21:52:19 +02:00
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typedef struct _ir_copy {
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ir_type type;
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ir_reg from;
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ir_reg to;
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} ir_copy;
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2022-11-17 21:30:35 +01:00
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#if IR_REG_INT_ARGS
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static const int8_t _ir_int_reg_params[IR_REG_INT_ARGS];
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#else
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static const int8_t *_ir_int_reg_params;
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#endif
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#if IR_REG_FP_ARGS
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static const int8_t _ir_fp_reg_params[IR_REG_FP_ARGS];
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#else
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static const int8_t *_ir_fp_reg_params;
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#endif
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#ifdef IR_HAVE_FASTCALL
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static const int8_t _ir_int_fc_reg_params[IR_REG_INT_FCARGS];
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static const int8_t *_ir_fp_fc_reg_params;
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2023-03-28 12:18:12 +02:00
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static bool ir_is_fastcall(const ir_ctx *ctx, const ir_insn *insn)
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2022-11-17 21:30:35 +01:00
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{
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if (sizeof(void*) == 4) {
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if (IR_IS_CONST_REF(insn->op2)) {
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return (ctx->ir_base[insn->op2].const_flags & IR_CONST_FASTCALL_FUNC) != 0;
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} else if (ctx->ir_base[insn->op2].op == IR_BITCAST) {
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return (ctx->ir_base[insn->op2].op2 & IR_CONST_FASTCALL_FUNC) != 0;
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}
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return 0;
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}
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return 0;
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}
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#else
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# define ir_is_fastcall(ctx, insn) 0
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#endif
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2023-03-02 15:56:15 +01:00
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#ifdef _WIN64
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2023-03-28 12:18:12 +02:00
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static bool ir_is_vararg(const ir_ctx *ctx, ir_insn *insn)
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2023-03-02 15:56:15 +01:00
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{
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if (IR_IS_CONST_REF(insn->op2)) {
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return (ctx->ir_base[insn->op2].const_flags & IR_CONST_VARARG_FUNC) != 0;
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} else if (ctx->ir_base[insn->op2].op == IR_BITCAST) {
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return (ctx->ir_base[insn->op2].op2 & IR_CONST_VARARG_FUNC) != 0;
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}
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return 0;
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}
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#endif
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2023-03-28 12:18:12 +02:00
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IR_ALWAYS_INLINE uint32_t ir_rule(const ir_ctx *ctx, ir_ref ref)
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2022-10-26 21:52:19 +02:00
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{
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IR_ASSERT(!IR_IS_CONST_REF(ref));
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return ctx->rules[ref];
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}
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2023-03-29 00:21:54 +02:00
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IR_ALWAYS_INLINE bool ir_in_same_block(ir_ctx *ctx, ir_ref ref)
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{
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return ref > ctx->bb_start;
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}
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2023-03-28 12:18:12 +02:00
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static ir_reg ir_get_param_reg(const ir_ctx *ctx, ir_ref ref)
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2022-11-17 21:30:35 +01:00
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{
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ir_use_list *use_list = &ctx->use_lists[1];
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int i;
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ir_ref use, *p;
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ir_insn *insn;
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int int_param = 0;
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int fp_param = 0;
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int int_reg_params_count = IR_REG_INT_ARGS;
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int fp_reg_params_count = IR_REG_FP_ARGS;
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const int8_t *int_reg_params = _ir_int_reg_params;
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const int8_t *fp_reg_params = _ir_fp_reg_params;
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#ifdef IR_HAVE_FASTCALL
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if (sizeof(void*) == 4 && (ctx->flags & IR_FASTCALL_FUNC)) {
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int_reg_params_count = IR_REG_INT_FCARGS;
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fp_reg_params_count = IR_REG_FP_FCARGS;
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int_reg_params = _ir_int_fc_reg_params;
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fp_reg_params = _ir_fp_fc_reg_params;
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}
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#endif
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for (i = 0, p = &ctx->use_edges[use_list->refs]; i < use_list->count; i++, p++) {
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use = *p;
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insn = &ctx->ir_base[use];
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if (insn->op == IR_PARAM) {
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if (IR_IS_TYPE_INT(insn->type)) {
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if (use == ref) {
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if (int_param < int_reg_params_count) {
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return int_reg_params[int_param];
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} else {
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return IR_REG_NONE;
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}
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}
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int_param++;
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2023-03-02 15:56:15 +01:00
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#ifdef _WIN64
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/* WIN64 calling convention use common couter for int and fp registers */
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fp_param++;
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#endif
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2022-11-17 21:30:35 +01:00
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} else if (IR_IS_TYPE_FP(insn->type)) {
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if (use == ref) {
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if (fp_param < fp_reg_params_count) {
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return fp_reg_params[fp_param];
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} else {
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return IR_REG_NONE;
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}
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}
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fp_param++;
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2023-03-02 15:56:15 +01:00
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#ifdef _WIN64
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/* WIN64 calling convention use common couter for int and fp registers */
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int_param++;
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#endif
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2022-11-17 21:30:35 +01:00
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} else {
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IR_ASSERT(0);
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}
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}
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}
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return IR_REG_NONE;
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}
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2023-03-28 12:18:12 +02:00
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static int ir_get_args_regs(const ir_ctx *ctx, const ir_insn *insn, int8_t *regs)
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2022-11-17 21:30:35 +01:00
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{
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int j, n;
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ir_type type;
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int int_param = 0;
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int fp_param = 0;
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int count = 0;
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int int_reg_params_count = IR_REG_INT_ARGS;
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int fp_reg_params_count = IR_REG_FP_ARGS;
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const int8_t *int_reg_params = _ir_int_reg_params;
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const int8_t *fp_reg_params = _ir_fp_reg_params;
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#ifdef IR_HAVE_FASTCALL
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if (sizeof(void*) == 4 && ir_is_fastcall(ctx, insn)) {
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int_reg_params_count = IR_REG_INT_FCARGS;
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fp_reg_params_count = IR_REG_FP_FCARGS;
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int_reg_params = _ir_int_fc_reg_params;
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fp_reg_params = _ir_fp_fc_reg_params;
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}
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#endif
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2023-04-05 18:20:43 +02:00
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n = ir_variable_inputs_count(insn);
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2022-11-17 21:30:35 +01:00
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n = IR_MIN(n, IR_MAX_REG_ARGS + 2);
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for (j = 3; j <= n; j++) {
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type = ctx->ir_base[ir_insn_op(insn, j)].type;
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if (IR_IS_TYPE_INT(type)) {
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if (int_param < int_reg_params_count) {
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regs[j] = int_reg_params[int_param];
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count = j + 1;
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} else {
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regs[j] = IR_REG_NONE;
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}
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int_param++;
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2023-03-02 15:56:15 +01:00
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#ifdef _WIN64
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/* WIN64 calling convention use common couter for int and fp registers */
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fp_param++;
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#endif
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2022-11-17 21:30:35 +01:00
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} else if (IR_IS_TYPE_FP(type)) {
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if (fp_param < fp_reg_params_count) {
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regs[j] = fp_reg_params[fp_param];
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count = j + 1;
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} else {
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regs[j] = IR_REG_NONE;
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}
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fp_param++;
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2023-03-02 15:56:15 +01:00
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#ifdef _WIN64
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/* WIN64 calling convention use common couter for int and fp registers */
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int_param++;
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#endif
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2022-11-17 21:30:35 +01:00
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} else {
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IR_ASSERT(0);
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}
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}
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return count;
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}
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2023-03-28 12:18:12 +02:00
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static bool ir_is_same_mem(const ir_ctx *ctx, ir_ref r1, ir_ref r2)
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2022-10-26 21:52:19 +02:00
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{
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ir_live_interval *ival1, *ival2;
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int32_t o1, o2;
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if (IR_IS_CONST_REF(r1) || IR_IS_CONST_REF(r2)) {
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return 0;
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}
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IR_ASSERT(ctx->vregs[r1] && ctx->vregs[r2]);
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ival1 = ctx->live_intervals[ctx->vregs[r1]];
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ival2 = ctx->live_intervals[ctx->vregs[r2]];
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IR_ASSERT(ival1 && ival2);
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o1 = ival1->stack_spill_pos;
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o2 = ival2->stack_spill_pos;
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IR_ASSERT(o1 != -1 && o2 != -1);
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return o1 == o2;
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}
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static void *ir_resolve_sym_name(const char *name)
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{
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void *handle = NULL;
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void *addr;
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2023-02-21 00:19:03 +01:00
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#ifndef _WIN32
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# ifdef RTLD_DEFAULT
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2022-10-26 21:52:19 +02:00
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handle = RTLD_DEFAULT;
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2023-02-21 00:19:03 +01:00
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# endif
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2022-10-26 21:52:19 +02:00
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addr = dlsym(handle, name);
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2023-02-21 00:19:03 +01:00
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#else
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HMODULE mods[256];
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DWORD cbNeeded;
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uint32_t i = 0;
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2023-03-01 18:31:14 +01:00
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/* Quick workaraund to prevent *.irt tests failures */
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// TODO: try to find a general solution ???
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if (strcmp(name, "printf") == 0) {
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return (void*)printf;
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}
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2023-02-21 00:19:03 +01:00
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addr = NULL;
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EnumProcessModules(GetCurrentProcess(), mods, sizeof(mods), &cbNeeded);
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2023-03-01 18:31:14 +01:00
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while(i < (cbNeeded / sizeof(HMODULE))) {
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2023-02-21 00:19:03 +01:00
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addr = GetProcAddress(mods[i], name);
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2023-03-01 18:31:14 +01:00
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if (addr) {
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return addr;
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}
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2023-02-21 00:19:03 +01:00
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i++;
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}
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#endif
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2022-10-26 21:52:19 +02:00
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IR_ASSERT(addr != NULL);
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return addr;
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}
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#ifdef IR_SNAPSHOT_HANDLER_DCL
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IR_SNAPSHOT_HANDLER_DCL();
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#endif
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static void *ir_jmp_addr(ir_ctx *ctx, ir_insn *insn, ir_insn *addr_insn)
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{
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void *addr;
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IR_ASSERT(addr_insn->type == IR_ADDR);
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if (addr_insn->op == IR_FUNC) {
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2023-02-28 00:11:09 +01:00
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addr = ir_resolve_sym_name(ir_get_str(ctx, addr_insn->val.i32));
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2022-10-26 21:52:19 +02:00
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} else {
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IR_ASSERT(addr_insn->op == IR_ADDR || addr_insn->op == IR_FUNC_ADDR);
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addr = (void*)addr_insn->val.addr;
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}
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#ifdef IR_SNAPSHOT_HANDLER
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if (ctx->ir_base[insn->op1].op == IR_SNAPSHOT) {
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addr = IR_SNAPSHOT_HANDLER(ctx, insn->op1, &ctx->ir_base[insn->op1], addr);
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}
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#endif
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return addr;
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}
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2022-11-08 21:09:35 +01:00
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#if defined(__GNUC__)
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2022-11-17 21:30:35 +01:00
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# pragma GCC diagnostic push
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2022-11-08 21:09:35 +01:00
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# pragma GCC diagnostic ignored "-Warray-bounds"
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# pragma GCC diagnostic ignored "-Wimplicit-fallthrough"
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#endif
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2022-10-26 21:06:07 +02:00
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#if defined(IR_TARGET_X86) || defined(IR_TARGET_X64)
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# include "dynasm/dasm_proto.h"
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# include "dynasm/dasm_x86.h"
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#elif defined(IR_TARGET_AARCH64)
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# include "dynasm/dasm_proto.h"
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# include "dynasm/dasm_arm64.h"
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2022-11-08 21:09:35 +01:00
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#else
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# error "Unknown IR target"
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#endif
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#if defined(__GNUC__)
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2022-11-17 21:30:35 +01:00
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# pragma GCC diagnostic pop
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2022-11-08 21:09:35 +01:00
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#endif
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2023-03-21 11:45:37 +01:00
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/* Forward Declarations */
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static void ir_emit_osr_entry_loads(ir_ctx *ctx, int b, ir_block *bb);
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2022-11-08 21:09:35 +01:00
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#if defined(IR_TARGET_X86) || defined(IR_TARGET_X64)
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# include "ir_emit_x86.h"
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#elif defined(IR_TARGET_AARCH64)
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2022-10-26 21:06:07 +02:00
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# include "ir_emit_aarch64.h"
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#else
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# error "Unknown IR target"
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#endif
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2022-10-26 21:52:19 +02:00
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2023-03-21 11:45:37 +01:00
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static IR_NEVER_INLINE void ir_emit_osr_entry_loads(ir_ctx *ctx, int b, ir_block *bb)
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{
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ir_list *list = (ir_list*)ctx->osr_entry_loads;
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int pos = 0, count, i;
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ir_ref ref;
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IR_ASSERT(ctx->binding);
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IR_ASSERT(list);
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while (1) {
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i = ir_list_at(list, pos);
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if (b == i) {
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break;
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}
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IR_ASSERT(i != 0); /* end marker */
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pos++;
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count = ir_list_at(list, pos);
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pos += count + 1;
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}
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pos++;
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count = ir_list_at(list, pos);
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pos++;
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for (i = 0; i < count; i++, pos++) {
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ref = ir_list_at(list, pos);
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IR_ASSERT(ref >= 0 && ctx->vregs[ref] && ctx->live_intervals[ctx->vregs[ref]]);
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if (ctx->live_intervals[ctx->vregs[ref]]->stack_spill_pos == -1) {
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/* not spilled */
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ir_reg reg = ctx->live_intervals[ctx->vregs[ref]]->reg;
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ir_type type = ctx->ir_base[ref].type;
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int32_t offset = -ir_binding_find(ctx, ref);
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IR_ASSERT(offset > 0);
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if (IR_IS_TYPE_INT(type)) {
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ir_emit_load_mem_int(ctx, type, reg, ctx->spill_base, offset);
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} else {
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ir_emit_load_mem_fp(ctx, type, reg, ctx->spill_base, offset);
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}
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}
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}
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}
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2022-10-26 21:52:19 +02:00
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int ir_match(ir_ctx *ctx)
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{
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2022-11-08 21:09:35 +01:00
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uint32_t b;
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2023-03-21 11:45:37 +01:00
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ir_ref start, ref, *prev_ref;
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2022-10-26 21:52:19 +02:00
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ir_block *bb;
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2023-03-21 11:45:37 +01:00
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ir_insn *insn;
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2023-03-22 08:21:56 +01:00
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uint32_t entries_count = 0;
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2022-10-26 21:52:19 +02:00
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2023-03-21 11:45:37 +01:00
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ctx->rules = ir_mem_calloc(ctx->insns_count, sizeof(uint32_t));
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prev_ref = ctx->prev_ref;
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if (!prev_ref) {
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2022-11-24 10:55:16 +01:00
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ir_build_prev_refs(ctx);
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2023-03-21 11:45:37 +01:00
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prev_ref = ctx->prev_ref;
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2022-10-26 21:52:19 +02:00
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}
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2023-03-22 08:21:56 +01:00
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if (ctx->entries_count) {
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ctx->entries = ir_mem_malloc(ctx->entries_count * sizeof(ir_ref));
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}
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2022-10-26 21:52:19 +02:00
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for (b = ctx->cfg_blocks_count, bb = ctx->cfg_blocks + b; b > 0; b--, bb--) {
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2022-11-29 18:02:07 +01:00
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IR_ASSERT(!(bb->flags & IR_BB_UNREACHABLE));
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2023-03-21 11:45:37 +01:00
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start = bb->start;
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2023-03-23 21:44:59 +01:00
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if (UNEXPECTED(bb->flags & IR_BB_ENTRY)) {
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2023-03-22 08:21:56 +01:00
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IR_ASSERT(entries_count < ctx->entries_count);
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2023-03-21 11:45:37 +01:00
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insn = &ctx->ir_base[start];
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2023-03-17 07:02:37 +01:00
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IR_ASSERT(insn->op == IR_ENTRY);
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2023-03-22 08:21:56 +01:00
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insn->op3 = entries_count;
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ctx->entries[entries_count] = b;
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entries_count++;
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2023-03-17 07:02:37 +01:00
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}
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2023-04-05 18:20:43 +02:00
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ctx->rules[start] = IR_SKIPPED | IR_NOP;
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2023-03-21 11:45:37 +01:00
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ref = bb->end;
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2023-03-23 21:44:59 +01:00
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if (bb->successors_count == 1) {
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insn = &ctx->ir_base[ref];
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if (insn->op == IR_END || insn->op == IR_LOOP_END) {
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ctx->rules[ref] = insn->op;
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ref = prev_ref[ref];
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if (ref == start) {
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if (EXPECTED(!(bb->flags & IR_BB_ENTRY))) {
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bb->flags |= IR_BB_EMPTY;
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} else if (ctx->flags & IR_MERGE_EMPTY_ENTRIES) {
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bb->flags |= IR_BB_EMPTY;
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if (ctx->cfg_edges[bb->successors] == b + 1) {
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(bb + 1)->flags |= IR_BB_PREV_EMPTY_ENTRY;
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}
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2023-03-21 11:45:37 +01:00
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}
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2023-03-23 21:44:59 +01:00
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continue;
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2023-03-21 11:45:37 +01:00
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}
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}
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}
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2023-03-29 00:21:54 +02:00
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ctx->bb_start = start; /* bb_start is used by matcher to avoid fusion of insns from different blocks */
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2023-03-23 21:44:59 +01:00
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while (ref != start) {
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uint32_t rule = ctx->rules[ref];
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if (!rule) {
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2023-03-29 00:21:54 +02:00
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ctx->rules[ref] = rule = ir_match_insn(ctx, ref);
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2023-03-21 11:45:37 +01:00
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}
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2023-03-29 00:21:54 +02:00
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ir_match_insn2(ctx, ref, rule);
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2023-03-21 11:45:37 +01:00
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ref = prev_ref[ref];
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}
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}
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if (ctx->entries_count) {
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2023-03-22 08:21:56 +01:00
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ctx->entries_count = entries_count;
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if (!entries_count) {
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ir_mem_free(ctx->entries);
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ctx->entries = NULL;
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2022-10-26 21:52:19 +02:00
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}
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}
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return 1;
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}
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