ir/tests/x86_64/ra_005.irt

--TEST--
005: Register Allocation (DIV + DIV)
--TARGET--
x86_64
--ARGS--
-S
--CODE--
{
	l_1 = START(l_4);
	uint32_t x_1 = PARAM(l_1, "x", 1);
	uint32_t y_1 = PARAM(l_1, "y", 2);
	uint32_t z_1 = PARAM(l_1, "z", 3);
	uint32_t x_2 = DIV(x_1, y_1);
	uint32_t x_3 = DIV(x_2, z_1);
	l_4 = RETURN(l_1, x_3);
}
--EXPECT--
test:
	movl %edx, %ecx
	movl %edi, %eax
	xorl %edx, %edx
	divl %esi
	xorl %edx, %edx
	divl %ecx
	retq