2022-11-08 09:32:46 +01:00
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/*
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* IR - Lightweight JIT Compilation Framework
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* (Aarch64 CPU specific definitions)
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* Copyright (C) 2022 Zend by Perforce.
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* Authors: Dmitry Stogov <dmitry@php.net>
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*/
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2022-05-31 10:22:31 +02:00
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#ifndef IR_AARCH64_H
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#define IR_AARCH64_H
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#define IR_GP_REGS(_) \
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_(X0, x0, w0) \
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_(X1, x1, w1) \
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_(X2, x2, w2) \
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_(X3, x3, w3) \
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_(X4, x4, w4) \
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_(X5, x5, w5) \
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_(X6, x6, w6) \
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_(X7, x7, w7) \
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_(X8, x8, w8) \
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_(X9, x9, w9) \
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_(X10, x10, w10) \
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_(X11, x11, w11) \
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_(X12, x12, w12) \
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_(X13, x13, w13) \
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_(X14, x14, w14) \
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_(X15, x15, w15) \
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_(X16, x16, w16) \
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_(X17, x17, w17) \
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_(X18, x18, w18) \
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_(X19, x19, w18) \
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_(X20, x20, w20) \
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_(X21, x21, w21) \
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_(X22, x22, w22) \
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_(X23, x23, w23) \
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_(X24, x24, w24) \
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_(X25, x25, w25) \
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_(X26, x26, w26) \
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_(X27, x27, w27) \
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_(X28, x28, w28) \
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_(X29, x29, w29) \
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_(X30, x30, w30) \
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_(X31, x31, w31) \
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# define IR_FP_REGS(_) \
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_(V0, d0, s0, h0, b0) \
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_(V1, d1, s1, h1, b1) \
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_(V2, d2, s2, h2, b2) \
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_(V3, d3, s3, h3, b3) \
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_(V4, d4, s4, h4, b4) \
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_(V5, d5, s5, h5, b5) \
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_(V6, d6, s6, h6, b6) \
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_(V7, d7, s7, h7, b7) \
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_(V8, d8, s8, h8, b8) \
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_(V9, d9, s9, h9, b9) \
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_(V10, d10, s10, h10, b10) \
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_(V11, d11, s11, h11, b11) \
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_(V12, d12, s12, h12, b12) \
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_(V13, d13, s13, h13, b13) \
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_(V14, d14, s14, h14, b14) \
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_(V15, d15, s15, h15, b15) \
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_(V16, d16, s16, h16, b16) \
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_(V17, d17, s17, h17, b17) \
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_(V18, d18, s18, h18, b18) \
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_(V19, d19, s19, h19, b18) \
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_(V20, d20, s20, h20, b20) \
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_(V21, d21, s21, h21, b21) \
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_(V22, d22, s22, h22, b22) \
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_(V23, d23, s23, h23, b23) \
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_(V24, d24, s24, h24, b24) \
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_(V25, d25, s25, h25, b25) \
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_(V26, d26, s26, h26, b26) \
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_(V27, d27, s27, h27, b27) \
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_(V28, d28, s28, h28, b28) \
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_(V29, d29, s29, h29, b29) \
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_(V30, d30, s30, h30, b30) \
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_(V31, d31, s31, h31, b31) \
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#define IR_GP_REG_ENUM(code, name64, name32) \
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IR_REG_ ## code,
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#define IR_FP_REG_ENUM(code, name64, name32, name16, name8) \
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IR_REG_ ## code,
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enum _ir_reg {
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2023-01-30 14:33:57 +01:00
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_IR_REG_NONE = -1,
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2022-05-31 10:22:31 +02:00
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IR_GP_REGS(IR_GP_REG_ENUM)
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IR_FP_REGS(IR_FP_REG_ENUM)
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IR_REG_NUM,
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};
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#define IR_REG_GP_FIRST IR_REG_X0
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#define IR_REG_FP_FIRST IR_REG_V0
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#define IR_REG_GP_LAST (IR_REG_FP_FIRST - 1)
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#define IR_REG_FP_LAST (IR_REG_NUM - 1)
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#define IR_REGSET_64BIT 1
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2022-06-02 17:34:47 +02:00
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#define IR_REG_INT_TMP IR_REG_X17 /* reserved temporary register used by code-generator */
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2022-05-31 10:22:31 +02:00
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#define IR_REG_STACK_POINTER \
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IR_REG_X31
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#define IR_REG_FRAME_POINTER \
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IR_REG_X29
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#define IR_REGSET_FIXED \
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2022-06-02 17:34:47 +02:00
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( IR_REGSET(IR_REG_INT_TMP) \
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| IR_REGSET(IR_REG_X18) /* platform specific register */ \
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| IR_REGSET_INTERVAL(IR_REG_X29, IR_REG_X31))
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2022-05-31 10:22:31 +02:00
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#define IR_REGSET_GP \
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IR_REGSET_DIFFERENCE(IR_REGSET_INTERVAL(IR_REG_GP_FIRST, IR_REG_GP_LAST), IR_REGSET_FIXED)
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#define IR_REGSET_FP \
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IR_REGSET_DIFFERENCE(IR_REGSET_INTERVAL(IR_REG_FP_FIRST, IR_REG_FP_LAST), IR_REGSET_FIXED)
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#define IR_REG_IP0 IR_REG_X16
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#define IR_REG_IP1 IR_REG_X17
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#define IR_REG_PR IR_REG_X18
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#define IR_REG_LR IR_REG_X30
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#define IR_REG_ZR IR_REG_X31
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/* Calling Convention */
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#define IR_REG_INT_RET1 IR_REG_X0
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#define IR_REG_FP_RET1 IR_REG_V0
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#define IR_REG_INT_ARGS 8
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#define IR_REG_FP_ARGS 8
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#define IR_REG_INT_ARG1 IR_REG_X0
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#define IR_REG_INT_ARG2 IR_REG_X1
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#define IR_REG_INT_ARG3 IR_REG_X2
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#define IR_REG_INT_ARG4 IR_REG_X3
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#define IR_REG_INT_ARG5 IR_REG_X4
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#define IR_REG_INT_ARG6 IR_REG_X5
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#define IR_REG_INT_ARG7 IR_REG_X6
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2022-05-31 23:34:45 +02:00
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#define IR_REG_INT_ARG8 IR_REG_X7
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2022-05-31 10:22:31 +02:00
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#define IR_REG_FP_ARG1 IR_REG_V0
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#define IR_REG_FP_ARG2 IR_REG_V1
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#define IR_REG_FP_ARG3 IR_REG_V2
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#define IR_REG_FP_ARG4 IR_REG_V3
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#define IR_REG_FP_ARG5 IR_REG_V4
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#define IR_REG_FP_ARG6 IR_REG_V5
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#define IR_REG_FP_ARG7 IR_REG_V6
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#define IR_REG_FP_ARG8 IR_REG_V7
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2022-11-17 21:30:35 +01:00
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#define IR_MAX_REG_ARGS 16
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2022-05-31 10:22:31 +02:00
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# define IR_REGSET_SCRATCH \
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2022-06-02 17:34:47 +02:00
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(IR_REGSET_INTERVAL(IR_REG_X0, IR_REG_X18) \
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2022-05-31 10:22:31 +02:00
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| IR_REGSET_INTERVAL(IR_REG_V0, IR_REG_V7) \
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| IR_REGSET_INTERVAL(IR_REG_V16, IR_REG_V31))
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# define IR_REGSET_PRESERVED \
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2022-05-31 23:34:45 +02:00
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(IR_REGSET_INTERVAL(IR_REG_X19, IR_REG_X30) \
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2022-05-31 10:22:31 +02:00
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| IR_REGSET_INTERVAL(IR_REG_V8, IR_REG_V15))
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2022-11-17 21:30:35 +01:00
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typedef struct _ir_tmp_reg {
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union {
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uint8_t num;
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int8_t reg;
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};
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uint8_t type;
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uint8_t start;
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uint8_t end;
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} ir_tmp_reg;
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struct _ir_target_constraints {
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int8_t def_reg;
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uint8_t tmps_count;
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uint8_t hints_count;
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ir_tmp_reg tmp_regs[3];
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int8_t hints[IR_MAX_REG_ARGS + 3];
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};
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2022-05-31 10:22:31 +02:00
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#endif /* IR_AARCH64_H */
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