2022-11-08 09:32:46 +01:00
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/*
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* IR - Lightweight JIT Compilation Framework
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2022-11-08 14:24:53 +01:00
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* (x86/x86_64 CPU specific definitions)
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2022-11-08 09:32:46 +01:00
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* Copyright (C) 2022 Zend by Perforce.
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* Authors: Dmitry Stogov <dmitry@php.net>
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*/
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2022-04-05 23:19:23 +02:00
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#ifndef IR_X86_H
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#define IR_X86_H
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#if defined(__x86_64__) || defined(_WIN64)
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# define IR_GP_REGS(_) \
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_(R0, rax, eax, ax, al, ah) \
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_(R1, rcx, ecx, cx, cl, ch) \
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_(R2, rdx, edx, dx, dl, dh) \
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_(R3, rbx, ebx, bx, bl, bh) \
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_(R4, rsp, esp, __, __, __) \
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_(R5, rbp, ebp, bp, r5b, __) \
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_(R6, rsi, esi, si, r6b, __) \
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_(R7, rdi, edi, di, r7b, __) \
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_(R8, r8, r8d, r8w, r8b, __) \
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_(R9, r9, r9d, r9w, r9b, __) \
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_(R10, r10, r10d, r10w, r10b, __) \
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_(R11, r11, r11d, r11w, r11b, __) \
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_(R12, r12, r12d, r12w, r12b, __) \
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_(R13, r13, r13d, r13w, r13b, __) \
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_(R14, r14, r14d, r14w, r14b, __) \
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_(R15, r15, r15d, r15w, r15b, __) \
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# define IR_FP_REGS(_) \
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_(XMM0, xmm0) \
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_(XMM1, xmm1) \
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_(XMM2, xmm2) \
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_(XMM3, xmm3) \
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_(XMM4, xmm4) \
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_(XMM5, xmm5) \
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_(XMM6, xmm6) \
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_(XMM7, xmm7) \
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_(XMM8, xmm8) \
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_(XMM9, xmm9) \
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_(XMM10, xmm10) \
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_(XMM11, xmm11) \
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_(XMM12, xmm12) \
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_(XMM13, xmm13) \
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_(XMM14, xmm14) \
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_(XMM15, xmm15) \
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#else
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# define IR_GP_REGS(_) \
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_(R0, ___, eax, ax, al, ah) \
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_(R1, ___, ecx, cx, cl, ch) \
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_(R2, ___, edx, dx, dl, dh) \
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_(R3, ___, ebx, bx, bl, bh) \
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_(R4, ___, esp, __, __, __) \
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_(R5, ___, ebp, bp, __, __) \
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_(R6, ___, esi, si, __, __) \
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_(R7, ___, edi, di, __, __) \
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# define IR_FP_REGS(_) \
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_(XMM0, xmm0) \
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_(XMM1, xmm1) \
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_(XMM2, xmm2) \
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_(XMM3, xmm3) \
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_(XMM4, xmm4) \
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_(XMM5, xmm5) \
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_(XMM6, xmm6) \
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_(XMM7, xmm7) \
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#endif
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2022-05-31 10:22:31 +02:00
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#define IR_GP_REG_ENUM(code, name64, name32, name16, name8, name8h) \
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IR_REG_ ## code,
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#define IR_FP_REG_ENUM(code, name) \
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IR_REG_ ## code,
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enum _ir_reg {
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IR_REG_NONE = -1,
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IR_GP_REGS(IR_GP_REG_ENUM)
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IR_FP_REGS(IR_FP_REG_ENUM)
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IR_REG_NUM,
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};
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2022-04-05 23:19:23 +02:00
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#define IR_REG_GP_FIRST IR_REG_R0
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#define IR_REG_FP_FIRST IR_REG_XMM0
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#define IR_REG_GP_LAST (IR_REG_FP_FIRST - 1)
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#define IR_REG_FP_LAST (IR_REG_NUM - 1)
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2022-05-31 10:22:31 +02:00
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#define IR_REGSET_64BIT 0
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2022-04-05 23:19:23 +02:00
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#define IR_REG_STACK_POINTER \
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IR_REG_RSP
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#define IR_REG_FRAME_POINTER \
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IR_REG_RBP
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#define IR_REGSET_FIXED \
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(IR_REGSET(IR_REG_RSP))
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#define IR_REGSET_GP \
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IR_REGSET_DIFFERENCE(IR_REGSET_INTERVAL(IR_REG_GP_FIRST, IR_REG_GP_LAST), IR_REGSET_FIXED)
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#define IR_REGSET_FP \
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IR_REGSET_DIFFERENCE(IR_REGSET_INTERVAL(IR_REG_FP_FIRST, IR_REG_FP_LAST), IR_REGSET_FIXED)
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2022-05-27 12:18:04 +02:00
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#define IR_REG_RAX IR_REG_R0
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#define IR_REG_RCX IR_REG_R1
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#define IR_REG_RDX IR_REG_R2
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#define IR_REG_RBX IR_REG_R3
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#define IR_REG_RSP IR_REG_R4
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#define IR_REG_RBP IR_REG_R5
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#define IR_REG_RSI IR_REG_R6
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#define IR_REG_RDI IR_REG_R7
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2022-04-05 23:19:23 +02:00
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/* Calling Convention */
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#ifdef _WIN64
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# define IR_REG_INT_RET1 IR_REG_RAX
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# define IR_REG_FP_RET1 IR_REG_XMM0
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# define IR_REG_INT_ARGS 4
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# define IR_REG_FP_ARGS 4
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# define IR_REG_INT_ARG1 IR_REG_RCX
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# define IR_REG_INT_ARG2 IR_REG_RDX
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# define IR_REG_INT_ARG3 IR_REG_R8
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# define IR_REG_INT_ARG4 IR_REG_R9
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# define IR_REG_FP_ARG1 IR_REG_XMM0
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# define IR_REG_FP_ARG2 IR_REG_XMM1
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# define IR_REG_FP_ARG3 IR_REG_XMM2
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# define IR_REG_FP_ARG4 IR_REG_XMM3
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2022-11-17 21:30:35 +01:00
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# define IR_MAX_REG_ARGS 8
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2022-04-05 23:19:23 +02:00
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# define IR_REGSET_SCRATCH \
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(IR_REGSET_INTERVAL(IR_REG_RAX, IR_REG_RDX) \
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| IR_REGSET_INTERVAL(IR_REG_R8, IR_REG_R11) \
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| IR_REGSET_FP)
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# define IR_REGSET_PRESERVED \
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(IR_REGSET(IR_REG_RBX) \
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| IR_REGSET_INTERVAL(IR_REG_RBP, IR_REG_RDI) \
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| IR_REGSET_INTERVAL(IR_REG_R12, IR_REG_R15))
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#elif defined(__x86_64__)
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# define IR_REG_INT_RET1 IR_REG_RAX
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# define IR_REG_FP_RET1 IR_REG_XMM0
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# define IR_REG_INT_ARGS 6
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# define IR_REG_FP_ARGS 8
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2022-04-07 13:18:59 +02:00
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# define IR_REG_INT_ARG1 IR_REG_RDI
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# define IR_REG_INT_ARG2 IR_REG_RSI
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# define IR_REG_INT_ARG3 IR_REG_RDX
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# define IR_REG_INT_ARG4 IR_REG_RCX
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2022-04-05 23:19:23 +02:00
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# define IR_REG_INT_ARG5 IR_REG_R8
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# define IR_REG_INT_ARG6 IR_REG_R9
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# define IR_REG_FP_ARG1 IR_REG_XMM0
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# define IR_REG_FP_ARG2 IR_REG_XMM1
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# define IR_REG_FP_ARG3 IR_REG_XMM2
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# define IR_REG_FP_ARG4 IR_REG_XMM3
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# define IR_REG_FP_ARG5 IR_REG_XMM4
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# define IR_REG_FP_ARG6 IR_REG_XMM5
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# define IR_REG_FP_ARG7 IR_REG_XMM6
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# define IR_REG_FP_ARG8 IR_REG_XMM7
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2022-11-17 21:30:35 +01:00
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# define IR_MAX_REG_ARGS 14
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2022-04-05 23:19:23 +02:00
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# define IR_REGSET_SCRATCH \
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(IR_REGSET_INTERVAL(IR_REG_RAX, IR_REG_RDX) \
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| IR_REGSET_INTERVAL(IR_REG_RSI, IR_REG_RDI) \
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| IR_REGSET_INTERVAL(IR_REG_R8, IR_REG_R11) \
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| IR_REGSET_FP)
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# define IR_REGSET_PRESERVED \
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(IR_REGSET(IR_REG_RBX) \
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| IR_REGSET(IR_REG_RBP) \
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| IR_REGSET_INTERVAL(IR_REG_R12, IR_REG_R15))
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#else
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# define IR_REG_INT_RET1 IR_REG_RAX
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2022-05-25 21:00:18 +02:00
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# define IR_REG_INT_RET2 IR_REG_RDX
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2022-04-05 23:19:23 +02:00
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# define IR_REG_INT_ARGS 0
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# define IR_REG_FP_ARGS 0
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2022-11-17 21:30:35 +01:00
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# define IR_HAVE_FASTCALL 1
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2022-04-05 23:19:23 +02:00
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# define IR_REG_INT_FCARGS 2
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# define IR_REG_FP_FCARGS 0
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# define IR_REG_INT_FCARG1 IR_REG_RCX
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# define IR_REG_INT_FCARG2 IR_REG_RDX
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2022-11-17 21:30:35 +01:00
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# define IR_MAX_REG_ARGS 2
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2022-04-05 23:19:23 +02:00
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# define IR_REGSET_SCRATCH \
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(IR_REGSET_INTERVAL(IR_REG_RAX, IR_REG_RDX) | IR_REGSET_FP)
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# define IR_REGSET_PRESERVED \
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(IR_REGSET(IR_REG_RBX) \
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| IR_REGSET(IR_REG_RBP) \
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2022-05-25 13:58:39 +02:00
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| IR_REGSET_INTERVAL(IR_REG_RSI, IR_REG_RDI))
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2022-04-05 23:19:23 +02:00
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#endif
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2022-11-17 21:30:35 +01:00
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typedef struct _ir_tmp_reg {
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union {
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uint8_t num;
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int8_t reg;
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};
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uint8_t type;
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uint8_t start;
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uint8_t end;
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} ir_tmp_reg;
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struct _ir_target_constraints {
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int8_t def_reg;
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uint8_t tmps_count;
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uint8_t hints_count;
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ir_tmp_reg tmp_regs[3];
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int8_t hints[IR_MAX_REG_ARGS + 3];
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};
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2022-04-05 23:19:23 +02:00
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#endif /* IR_X86_H */
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