2022-04-05 23:19:23 +02:00
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#ifndef IR_H
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#define IR_H
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#include <inttypes.h>
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#include <stdint.h>
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#include <string.h>
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#include <stdio.h>
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#include <malloc.h>
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#define IR_VERSION "0.0.1"
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typedef uint8_t bool;
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#ifdef IR_DEBUG
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# include <assert.h>
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# define IR_ASSERT(x) assert(x)
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2022-05-13 08:22:31 +02:00
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# ifndef IR_DEBUG_REGSET
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# define IR_DEBUG_REGSET
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# endif
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2022-04-05 23:19:23 +02:00
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#else
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# define IR_ASSERT(x)
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#endif
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#ifdef __has_builtin
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# if __has_builtin(__builtin_expect)
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# define EXPECTED(condition) __builtin_expect(!!(condition), 1)
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# define UNEXPECTED(condition) __builtin_expect(!!(condition), 0)
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# endif
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#endif
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#ifndef EXPECTED
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# define EXPECTED(condition) (condition)
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# define UNEXPECTED(condition) (condition)
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#endif
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#ifdef __has_attribute
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# if __has_attribute(always_inline)
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# define IR_ALWAYS_INLINE static inline __attribute__((always_inline))
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# endif
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# if __has_attribute(noinline)
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# define IR_NEVER_INLINE __attribute__((noinline))
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# endif
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# if __has_attribute(unused)
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# define IR_UNUSED_LABEL __attribute__((unused));
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# endif
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#endif
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#ifndef IR_ALWAYS_INLINE
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# define IR_ALWAYS_INLINE static inline
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#endif
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#ifndef IR_NEVER_INLINE
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# define IR_NEVER_INLINE
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#endif
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#ifndef IR_UNUSED_LABEL
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# define IR_UNUSED_LABEL
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#endif
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#if defined(__BYTE_ORDER__)
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# if defined(__ORDER_LITTLE_ENDIAN__)
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# if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
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# define IR_STRUCT_LOHI(lo, hi) struct {lo; hi;}
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# endif
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# endif
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# if defined(__ORDER_BIG_ENDIAN__)
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# if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
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# define IR_STRUCT_LOHI(lo, hi) struct {hi; lo;}
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# endif
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# endif
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#endif
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#ifndef IR_STRUCT_LOHI
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# error "Unknown byte order"
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#endif
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#if defined(__SIZEOF_SIZE_T__)
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# if __SIZEOF_SIZE_T__ == 8
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# define IR_64 1
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# elif __SIZEOF_SIZE_T__ != 4
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# error "Unknown addr size"
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# endif
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#else
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# error "Unknown addr size"
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#endif
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#define ir_mem_malloc(size) malloc(size)
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#define ir_mem_calloc(n, size) calloc(n, size)
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#define ir_mem_realloc(ptr, size) realloc(ptr, size)
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#define ir_mem_free(ptr) free(ptr)
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void *ir_mem_mmap(size_t size);
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int ir_mem_unmap(void *ptr, size_t size);
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int ir_mem_protect(void *ptr, size_t size);
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int ir_mem_unprotect(void *ptr, size_t size);
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int ir_mem_flush(void *ptr, size_t size);
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/* IR_TYPE flags (low 4 bits are used for type size) */
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#define IR_TYPE_SIGNED (1<<4)
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#define IR_TYPE_UNSIGNED (1<<5)
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#define IR_TYPE_FP (1<<6)
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#define IR_TYPE_SPECIAL (1<<7)
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#define IR_TYPE_BOOL (IR_TYPE_SPECIAL|IR_TYPE_UNSIGNED)
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#define IR_TYPE_ADDR (IR_TYPE_SPECIAL|IR_TYPE_UNSIGNED)
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#define IR_TYPE_CHAR (IR_TYPE_SPECIAL|IR_TYPE_SIGNED)
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#define IR_TYPES(_) \
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2022-04-20 11:00:36 +02:00
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_(BOOL, bool, b, IR_TYPE_BOOL) \
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_(U8, uint8_t, u8, IR_TYPE_UNSIGNED) \
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_(U16, uint16_t, u16, IR_TYPE_UNSIGNED) \
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_(U32, uint32_t, u32, IR_TYPE_UNSIGNED) \
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_(U64, uint64_t, u64, IR_TYPE_UNSIGNED) \
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_(ADDR, uintptr_t, addr, IR_TYPE_ADDR) \
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_(CHAR, char, c, IR_TYPE_CHAR) \
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_(I8, int8_t, i8, IR_TYPE_SIGNED) \
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_(I16, int16_t, i16, IR_TYPE_SIGNED) \
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_(I32, int32_t, i32, IR_TYPE_SIGNED) \
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_(I64, int64_t, i64, IR_TYPE_SIGNED) \
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_(DOUBLE, double, d, IR_TYPE_FP) \
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_(FLOAT, float, f, IR_TYPE_FP) \
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2022-04-05 23:19:23 +02:00
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#define IR_IS_TYPE_UNSIGNED(t) ((t) < IR_CHAR)
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#define IR_IS_TYPE_SIGNED(t) ((t) >= IR_CHAR && (t) < IR_DOUBLE)
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#define IR_IS_TYPE_INT(t) ((t) < IR_DOUBLE)
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#define IR_IS_TYPE_FP(t) ((t) >= IR_DOUBLE)
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/* List of IR opcodes
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* ==================
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*
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* Each instruction is described by a type (opcode, flags, op1_type, op2_type, op3_type)
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*
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* flags
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* -----
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* v - void
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* d - data IR_OP_FLAG_DATA
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* r - ref IR_OP_FLAG_DATA alias
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* c - control IR_OP_FLAG_CONTROL
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* l - load IR_OP_FLAG_MEM + IR_OP_FLAG_MEM_LOAD
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* s - store IR_OP_FLAG_MEM + IR_OP_FLAG_STORE
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* x - call IR_OP_FLAG_MEM + IR_OP_FLAG_CALL
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* a - alloc IR_OP_FLAG_MEM + IR_OP_FLAG_ALLOC
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* 0-3 - number of input edges
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* N - number of arguments is defined in the insn->inputs_count (MERGE)
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* P - number of arguments is defined in the op1->inputs_count (PHI)
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* X1-X3 - number of extra data ops
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2022-04-21 10:30:05 +02:00
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* C - commutative operation ("d2C" => IR_OP_FLAG_DATA + IR_OP_FLAG_COMMUTATIVE)
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2022-04-05 23:19:23 +02:00
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*
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* operand types
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* -------------
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* ___ - unused
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* def - reference to a definition op (data-flow use-def dependency edge)
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* ref - memory reference (data-flow use-def dependency edge)
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2022-04-19 21:35:29 +02:00
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* var - variable reference (data-flow use-def dependency edge)
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2022-04-05 23:19:23 +02:00
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* arg - argument referene CALL/TAILCALL/CARG->CARG
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* src - reference to a previous control region (IF, IF_TRUE, IF_FALSE, LOOP_BEGIN, LOOP_END, RETURN)
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* reg - data-control dependency on region (PHI, VAR, PARAM)
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* beg - reference to a LOOP_BEGIN region (LOOP_END, LOOP_EXIT)
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* ret - reference to a previous RETURN instruction (RETURN)
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* str - string: variable/argument name (VAR, PARAM, CALL, TAILCALL)
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* num - number: argument number (PARAM)
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2022-05-24 11:47:39 +02:00
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* prb - branch probability 1-99 (0 - unspecified): (IF_TRUE, IF_FALSE, CASE_VAL, CASE_DEFAULT)
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2022-04-05 23:19:23 +02:00
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*
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* The order of IR opcodes is carefully selected for efficient folding.
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* - foldable instruction go first
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* - NOP is never used (code 0 is used as ANY pattern)
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* - CONST is the most often used instruction (encode with 1 bit)
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* - equality inversion: EQ <-> NE => op =^ 1
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* - comparison inversio: [U]LT <-> [U]GT, [U]LE <-> [U]GE => op =^ 3
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*/
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#define IR_OPS(_) \
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/* special op (must be the first !!!) */ \
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_(NOP, v, ___, ___, ___) /* empty instruction */ \
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\
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/* constants reference */ \
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_(C_BOOL, r0, ___, ___, ___) /* constant */ \
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_(C_U8, r0, ___, ___, ___) /* constant */ \
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_(C_U16, r0, ___, ___, ___) /* constant */ \
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_(C_U32, r0, ___, ___, ___) /* constant */ \
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_(C_U64, r0, ___, ___, ___) /* constant */ \
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_(C_ADDR, r0, ___, ___, ___) /* constant */ \
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_(C_CHAR, r0, ___, ___, ___) /* constant */ \
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_(C_I8, r0, ___, ___, ___) /* constant */ \
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_(C_I16, r0, ___, ___, ___) /* constant */ \
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_(C_I32, r0, ___, ___, ___) /* constant */ \
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_(C_I64, r0, ___, ___, ___) /* constant */ \
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_(C_DOUBLE, r0, ___, ___, ___) /* constant */ \
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_(C_FLOAT, r0, ___, ___, ___) /* constant */ \
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\
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/* equality ops */ \
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2022-04-21 10:30:05 +02:00
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_(EQ, d2C, def, def, ___) /* equal */ \
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_(NE, d2C, def, def, ___) /* not equal */ \
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2022-04-05 23:19:23 +02:00
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/* comparison ops (order matters, LT must be a modulo of 4 !!!) */ \
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_(LT, d2, def, def, ___) /* less */ \
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_(GE, d2, def, def, ___) /* greater or equal */ \
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_(LE, d2, def, def, ___) /* less or equal */ \
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_(GT, d2, def, def, ___) /* greater */ \
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_(ULT, d2, def, def, ___) /* unsigned less */ \
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_(UGE, d2, def, def, ___) /* unsigned greater or equal */ \
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_(ULE, d2, def, def, ___) /* unsigned less or equal */ \
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_(UGT, d2, def, def, ___) /* unsigned greater */ \
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/* arithmetic ops */ \
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2022-04-21 10:30:05 +02:00
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_(ADD, d2C, def, def, ___) /* addition */ \
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2022-04-05 23:19:23 +02:00
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_(SUB, d2, def, def, ___) /* subtraction (must be ADD+1) */ \
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2022-04-21 10:30:05 +02:00
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_(MUL, d2C, def, def, ___) /* multiplication */ \
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2022-04-05 23:19:23 +02:00
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_(DIV, d2, def, def, ___) /* division */ \
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_(MOD, d2, def, def, ___) /* modulo */ \
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_(NEG, d1, def, ___, ___) /* change sign */ \
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_(ABS, d1, def, ___, ___) /* absolute value */ \
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/* (LDEXP, MIN, MAX, FPMATH) */ \
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2022-05-20 08:00:13 +02:00
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/* type conversion ops */ \
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2022-05-20 00:01:48 +02:00
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_(SEXT, d1, def, ___, ___) /* sign extension */ \
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_(ZEXT, d1, def, ___, ___) /* zero extension */ \
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2022-05-20 08:00:13 +02:00
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_(TRUNC, d1, def, ___, ___) /* truncates to int type */ \
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_(BITCAST, d1, def, ___, ___) /* binary representation */ \
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2022-05-20 00:01:48 +02:00
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_(INT2FP, d1, def, ___, ___) /* int to float conversion */ \
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_(FP2INT, d1, def, ___, ___) /* float to int conversion */ \
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2022-05-20 08:00:13 +02:00
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_(FP2FP, d1, def, ___, ___) /* float to float conversion */ \
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2022-04-05 23:19:23 +02:00
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/* overflow-check ??? */ \
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2022-04-21 10:30:05 +02:00
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_(ADD_OV, d2C, def, def, ___) /* addition */ \
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2022-04-05 23:19:23 +02:00
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_(SUB_OV, d2, def, def, ___) /* subtraction */ \
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2022-04-21 10:30:05 +02:00
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_(MUL_OV, d2C, def, def, ___) /* multiplication */ \
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2022-04-05 23:19:23 +02:00
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_(OVERFLOW, d1, def, ___, ___) /* overflow check add/sub/mul */ \
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/* bitwise and shift ops */ \
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_(NOT, d1, def, ___, ___) /* bitwise NOT */ \
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2022-04-21 10:30:05 +02:00
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_(OR, d2C, def, def, ___) /* bitwise OR */ \
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_(AND, d2C, def, def, ___) /* bitwise AND */ \
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_(XOR, d2C, def, def, ___) /* bitwise XOR */ \
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2022-04-05 23:19:23 +02:00
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_(SHL, d2, def, def, ___) /* logic shift left */ \
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_(SHR, d2, def, def, ___) /* logic shift right */ \
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_(SAR, d2, def, def, ___) /* arithmetic shift right */ \
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_(ROL, d2, def, def, ___) /* rotate left */ \
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_(ROR, d2, def, def, ___) /* rotate right */ \
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_(BSWAP, d1, def, ___, ___) /* byte swap */ \
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\
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/* branch-less conditional ops */ \
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2022-04-21 10:30:05 +02:00
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_(MIN, d2C, def, def, ___) /* min(op1, op2) */ \
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_(MAX, d2C, def, def, ___) /* max(op1, op2) */ \
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2022-04-05 23:19:23 +02:00
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_(COND, d3, def, def, def) /* op1 ? op2 : op3 */ \
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\
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/* data-flow and miscellaneous ops */ \
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_(PHI, dP, reg, def, def) /* SSA Phi function */ \
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_(COPY, d1, def, ___, ___) /* COPY (last foldable op) */ \
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_(PI, d2, reg, def, ___) /* e-SSA Pi constraint ??? */ \
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/* (USE, RENAME) */ \
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\
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/* data ops */ \
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_(PARAM, r1X2, reg, str, num) /* incoming parameter proj. */ \
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_(VAR, r1X1, reg, str, ___) /* local variable */ \
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_(FUNC, r0, ___, ___, ___) /* constant func ref */ \
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_(STR, r0, ___, ___, ___) /* constant str ref */ \
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\
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/* call ops */ \
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_(CALL, xN, src, def, def) /* CALL(src, func, args...) */ \
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_(TAILCALL, xN, src, def, def) /* CALL+RETURN */ \
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\
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/* memory reference and load/store ops */ \
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2022-04-19 22:42:05 +02:00
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_(ALLOCA, a2, src, def, ___) /* alloca(def) */ \
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2022-04-20 11:00:36 +02:00
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_(VADDR, d1, var, ___, ___) /* load address of local var */ \
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2022-04-19 21:35:29 +02:00
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_(VLOAD, l2, src, var, ___) /* load value of local var */ \
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_(VSTORE, s3, src, var, def) /* store value to local var */ \
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2022-04-11 21:39:52 +02:00
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_(LOAD, l2, src, ref, ___) /* load from memory */ \
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_(STORE, s3, src, ref, def) /* store to memory */ \
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2022-04-05 23:19:23 +02:00
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/* memory reference ops (A, H, U, S, TMP, STR, NEW, X, V) ??? */ \
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\
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/* control-flow nodes */ \
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_(START, c0X1, ret, ___, ___) /* function start */ \
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_(RETURN, c2X1, src, def, ret) /* function return */ \
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_(UNREACHABLE, c2X1, src, def, ret) /* unreachable (tailcall, etc) */ \
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_(BEGIN, c1, src, ___, ___) /* block start */ \
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_(END, c1, src, ___, ___) /* block end */ \
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_(IF, c2, src, def, ___) /* conditional control split */ \
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2022-05-24 11:47:39 +02:00
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_(IF_TRUE, c1X1, src, prb, ___) /* IF TRUE proj. */ \
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_(IF_FALSE, c1X1, src, prb, ___) /* IF FALSE proj. */ \
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2022-04-05 23:19:23 +02:00
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_(SWITCH, c2, src, def, ___) /* multi-way control split */ \
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2022-05-24 11:47:39 +02:00
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_(CASE_VAL, c2X1, src, def, prb) /* switch proj. */ \
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_(CASE_DEFAULT, c1X1, src, prb, ___) /* switch proj. */ \
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2022-04-05 23:19:23 +02:00
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_(MERGE, cN, src, src, src) /* control merge */ \
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_(LOOP_BEGIN, c2, src, src, ___) /* loop start */ \
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_(LOOP_END, c1X1, src, beg, ___) /* loop end */ \
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_(LOOP_EXIT, c1X1, src, beg, ___) /* loop exit */ \
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2022-05-19 17:56:48 +02:00
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|
_(IJMP, c2X1, src, def, ret) /* computed goto */ \
|
2022-04-05 23:19:23 +02:00
|
|
|
\
|
|
|
|
/* guards (floating or not) ??? */ \
|
|
|
|
_(GUARD_TRUE, c2, src, def, ___) /* IF without second successor */ \
|
|
|
|
_(GUARD_FALSE, c2, src, def, ___) /* IF without second successor */ \
|
|
|
|
|
2022-05-24 11:47:39 +02:00
|
|
|
#define IR_OP_FLAG_OPERANDS_SHIFT 3
|
2022-04-05 23:19:23 +02:00
|
|
|
|
2022-05-24 11:47:39 +02:00
|
|
|
#define IR_OP_FLAG_EDGES_MSK 0x07
|
|
|
|
#define IR_OP_FLAG_OPERANDS_MSK 0x38
|
|
|
|
#define IR_OP_FLAG_MEM_MASK ((1<<6)|(1<<7))
|
2022-04-05 23:19:23 +02:00
|
|
|
|
2022-05-24 11:47:39 +02:00
|
|
|
#define IR_OP_FLAG_DATA (1<<8)
|
|
|
|
#define IR_OP_FLAG_CONTROL (1<<9)
|
|
|
|
#define IR_OP_FLAG_MEM (1<<10)
|
|
|
|
#define IR_OP_FLAG_COMMUTATIVE (1<<11)
|
2022-04-05 23:19:23 +02:00
|
|
|
|
2022-05-24 11:47:39 +02:00
|
|
|
#define IR_OP_FLAG_MEM_LOAD ((0<<6)|(0<<7))
|
|
|
|
#define IR_OP_FLAG_MEM_STORE ((0<<6)|(1<<7))
|
|
|
|
#define IR_OP_FLAG_MEM_CALL ((1<<6)|(0<<7))
|
|
|
|
#define IR_OP_FLAG_MEM_ALLOC ((1<<6)|(1<<7))
|
2022-04-05 23:19:23 +02:00
|
|
|
|
|
|
|
#define IR_OPND_UNUSED 0x0
|
|
|
|
#define IR_OPND_DATA 0x1
|
|
|
|
#define IR_OPND_CONTROL 0x2
|
|
|
|
#define IR_OPND_CONTROL_DEP 0x3
|
|
|
|
#define IR_OPND_CONTROL_REF 0x4
|
|
|
|
#define IR_OPND_STR 0x5
|
|
|
|
#define IR_OPND_NUM 0x6
|
2022-04-19 21:35:29 +02:00
|
|
|
#define IR_OPND_VAR 0x7
|
2022-05-24 11:47:39 +02:00
|
|
|
#define IR_OPND_PROB 0x8
|
2022-04-05 23:19:23 +02:00
|
|
|
|
|
|
|
#define IR_OP_FLAGS(op_flags, op1_flags, op2_flags, op3_flags) \
|
|
|
|
((op_flags) | ((op1_flags) << 20) | ((op2_flags) << 24) | ((op3_flags) << 28))
|
|
|
|
|
|
|
|
#define IR_INPUT_EDGES_COUNT(flags) (flags & IR_OP_FLAG_EDGES_MSK)
|
2022-05-24 11:47:39 +02:00
|
|
|
#define IR_OPERANDS_COUNT(flags) ((flags & IR_OP_FLAG_OPERANDS_MSK) >> IR_OP_FLAG_OPERANDS_SHIFT)
|
2022-04-05 23:19:23 +02:00
|
|
|
|
|
|
|
#define IR_OPND_KIND(flags, i) \
|
|
|
|
(((flags) >> (16 + (4 * (((i) > 3) ? 3 : (i))))) & 0xf)
|
|
|
|
|
2022-04-20 11:00:36 +02:00
|
|
|
#define IR_TYPE_ENUM(name, type, field, flags) IR_ ## name,
|
2022-04-05 23:19:23 +02:00
|
|
|
#define IR_OP_ENUM(name, flags, op1, op2, op3) IR_ ## name,
|
|
|
|
|
|
|
|
typedef enum _ir_type {
|
|
|
|
IR_VOID,
|
|
|
|
IR_TYPES(IR_TYPE_ENUM)
|
|
|
|
IR_LAST_TYPE
|
|
|
|
} ir_type;
|
|
|
|
|
|
|
|
typedef enum _ir_op {
|
|
|
|
IR_OPS(IR_OP_ENUM)
|
|
|
|
IR_LAST_OP
|
|
|
|
} ir_op;
|
|
|
|
|
|
|
|
typedef int32_t ir_ref;
|
|
|
|
|
|
|
|
#define IR_IS_CONST_REF(ref) ((ref) < 0)
|
|
|
|
|
|
|
|
#define IR_UNUSED 0
|
|
|
|
#define IR_NULL (-1)
|
|
|
|
#define IR_FALSE (-2)
|
|
|
|
#define IR_TRUE (-3)
|
|
|
|
#define IR_LAST_FOLDABLE IR_COPY
|
|
|
|
|
|
|
|
#define IR_IS_CONST(op) ((op) > IR_NOP && (op) <= IR_C_FLOAT)
|
|
|
|
#define IR_IS_FOLDABLE(op) ((op) <= IR_LAST_FOLDABLE)
|
|
|
|
|
|
|
|
#define IR_OPT_OP_MASK 0x00ff
|
|
|
|
#define IR_OPT_TYPE_MASK 0xff00
|
|
|
|
#define IR_OPT_TYPE_SHIFT 8
|
|
|
|
|
|
|
|
#define IR_OPT(op, type) ((uint16_t)(op) | ((uint16_t)(type) << IR_OPT_TYPE_SHIFT))
|
|
|
|
|
|
|
|
#define IR_OPT_TYPE(opt) (((opt) & IR_OPT_TYPE_MASK) >> IR_OPT_TYPE_SHIFT)
|
|
|
|
|
|
|
|
typedef union _ir_val {
|
|
|
|
double d;
|
|
|
|
uint64_t u64;
|
|
|
|
int64_t i64;
|
|
|
|
#ifdef IR_64
|
|
|
|
uintptr_t addr;
|
|
|
|
#endif
|
|
|
|
IR_STRUCT_LOHI(
|
|
|
|
union {
|
|
|
|
uint32_t u32;
|
|
|
|
int32_t i32;
|
|
|
|
float f;
|
|
|
|
#ifndef IR_64
|
|
|
|
uintptr_t addr;
|
|
|
|
#endif
|
|
|
|
IR_STRUCT_LOHI(
|
|
|
|
union {
|
|
|
|
uint16_t u16;
|
|
|
|
int16_t i16;
|
|
|
|
IR_STRUCT_LOHI(
|
|
|
|
union {
|
|
|
|
uint8_t u8;
|
|
|
|
int8_t i8;
|
|
|
|
bool b;
|
|
|
|
char c;
|
|
|
|
},
|
|
|
|
uint8_t u8_hi
|
|
|
|
);
|
|
|
|
},
|
|
|
|
uint16_t u16_hi
|
|
|
|
);
|
|
|
|
},
|
|
|
|
uint32_t u32_hi
|
|
|
|
);
|
|
|
|
} ir_val;
|
|
|
|
|
|
|
|
typedef struct _ir_insn {
|
|
|
|
IR_STRUCT_LOHI(
|
|
|
|
union {
|
|
|
|
IR_STRUCT_LOHI(
|
|
|
|
union {
|
|
|
|
IR_STRUCT_LOHI(
|
|
|
|
uint8_t op,
|
|
|
|
uint8_t type;
|
|
|
|
);
|
|
|
|
uint16_t opt;
|
|
|
|
},
|
|
|
|
union {
|
|
|
|
uint16_t inputs_count; /* number of input control edges for MERGE, CALL, TAILCALL */
|
|
|
|
uint16_t prev_insn_offset; /* 16-bit backward offset from current instruction for CSE */
|
|
|
|
uint16_t emit_const; /* flag to emit constant in rodat section */
|
|
|
|
}
|
|
|
|
);
|
|
|
|
uint32_t optx;
|
|
|
|
ir_ref ops[1];
|
|
|
|
},
|
|
|
|
union {
|
|
|
|
ir_ref op1;
|
|
|
|
ir_ref prev_const;
|
|
|
|
}
|
|
|
|
);
|
|
|
|
union {
|
|
|
|
IR_STRUCT_LOHI(
|
|
|
|
ir_ref op2,
|
|
|
|
ir_ref op3
|
|
|
|
);
|
|
|
|
ir_val val;
|
|
|
|
};
|
|
|
|
} ir_insn;
|
|
|
|
|
|
|
|
typedef struct _ir_strtab {
|
|
|
|
void *data;
|
|
|
|
uint32_t mask;
|
|
|
|
uint32_t size;
|
|
|
|
uint32_t count;
|
|
|
|
uint32_t pos;
|
|
|
|
char *buf;
|
|
|
|
uint32_t buf_size;
|
|
|
|
uint32_t buf_top;
|
|
|
|
} ir_strtab;
|
|
|
|
|
|
|
|
#define IR_IS_BB_START(op) \
|
|
|
|
((op) == IR_START || (op) == IR_BEGIN || (op) == IR_MERGE || (op) == IR_LOOP_BEGIN || \
|
|
|
|
(op) == IR_IF_TRUE || (op) == IR_IF_FALSE || (op) == IR_CASE_VAL || (op) == IR_CASE_DEFAULT)
|
|
|
|
|
|
|
|
#define IR_IS_BB_MERGE(op) \
|
|
|
|
((op) == IR_MERGE || (op) == IR_LOOP_BEGIN)
|
|
|
|
|
|
|
|
#define IR_IS_BB_END(op) \
|
2022-05-19 17:56:48 +02:00
|
|
|
((op) == IR_RETURN || (op) == IR_END || (op) == IR_LOOP_END || (op) == IR_IF || \
|
|
|
|
(op) == IR_SWITCH || (op) == IR_IJMP || (op) == IR_UNREACHABLE)
|
2022-04-05 23:19:23 +02:00
|
|
|
|
|
|
|
#define IR_BB_UNREACHABLE (1<<0)
|
|
|
|
#define IR_BB_LOOP_HEADER (1<<1)
|
|
|
|
#define IR_BB_IRREDUCIBLE_LOOP (1<<2)
|
|
|
|
#define IR_BB_DESSA_MOVES (1<<3) /* translation out of SSA requires MOVEs */
|
|
|
|
#define IR_BB_MAY_SKIP (1<<4) /* empty BB */
|
|
|
|
|
|
|
|
typedef struct _ir_block {
|
|
|
|
uint32_t flags;
|
|
|
|
ir_ref start; /* index of first instruction */
|
|
|
|
ir_ref end; /* index of last instruction */
|
|
|
|
uint32_t successors; /* index in ir_ctx->cfg_edges[] array */
|
|
|
|
uint32_t successors_count;
|
|
|
|
uint32_t predecessors; /* index in ir_ctx->cfg_edges[] array */
|
|
|
|
uint32_t predecessors_count;
|
|
|
|
union {
|
|
|
|
int dom_parent; /* immediate dominator block */
|
|
|
|
int idom; /* immediate dominator block */
|
|
|
|
};
|
|
|
|
union {
|
|
|
|
int dom_depth; /* depth from the root of the dominators tree */
|
|
|
|
int postnum; /* used temporary during tree constructon */
|
|
|
|
};
|
|
|
|
int dom_child; /* first dominated blocks */
|
|
|
|
int dom_next_child; /* next dominated block (linked list) */
|
|
|
|
int loop_header;
|
|
|
|
int loop_depth;
|
|
|
|
} ir_block;
|
|
|
|
|
|
|
|
typedef struct _ir_use_list {
|
|
|
|
ir_ref refs; /* index in ir_cts->use_edges[] array */
|
|
|
|
ir_ref count;
|
|
|
|
} ir_use_list;
|
|
|
|
|
2022-05-17 12:15:41 +02:00
|
|
|
#define IR_FUNCTION (1<<0)
|
|
|
|
#define IR_USE_FRAME_POINTER (1<<1)
|
|
|
|
#define IR_PREALLOCATED_STACK (1<<2)
|
|
|
|
#define IR_IRREDUCIBLE_CFG (1<<3)
|
|
|
|
|
|
|
|
#define IR_OPT_FOLDING (1<<16)
|
|
|
|
#define IR_OPT_CODEGEN (1<<17)
|
|
|
|
#define IR_OPT_IN_SCCP (1<<18)
|
|
|
|
#define IR_LINEAR (1<<19)
|
|
|
|
#define IR_GEN_NATIVE (1<<20)
|
|
|
|
#define IR_GEN_C (1<<22)
|
2022-04-05 23:19:23 +02:00
|
|
|
|
|
|
|
/* x86 related */
|
2022-05-17 12:15:41 +02:00
|
|
|
#define IR_AVX (1<<24)
|
|
|
|
#define IR_HAS_CALLS (1<<25)
|
2022-04-05 23:19:23 +02:00
|
|
|
|
2022-04-27 13:47:52 +02:00
|
|
|
/* debug relted */
|
|
|
|
#ifdef IR_DEBUG
|
|
|
|
# define IR_DEBUG_SCCP (1<<28)
|
|
|
|
# define IR_DEBUG_GCM (1<<29)
|
|
|
|
# define IR_DEBUG_RA (1<<30)
|
|
|
|
#endif
|
|
|
|
|
2022-04-05 23:19:23 +02:00
|
|
|
typedef enum _ir_fold_action {
|
|
|
|
IR_FOLD_DO_RESTART,
|
|
|
|
IR_FOLD_DO_CSE,
|
|
|
|
IR_FOLD_DO_EMIT,
|
|
|
|
IR_FOLD_DO_COPY,
|
|
|
|
IR_FOLD_DO_CONST
|
|
|
|
} ir_fold_action;
|
|
|
|
|
2022-04-14 21:40:13 +02:00
|
|
|
typedef ir_ref ir_live_pos;
|
2022-04-07 10:11:57 +02:00
|
|
|
typedef struct _ir_use_pos ir_use_pos;
|
2022-04-05 23:19:23 +02:00
|
|
|
typedef struct _ir_live_range ir_live_range;
|
|
|
|
typedef struct _ir_live_interval ir_live_interval;
|
|
|
|
|
2022-05-05 21:35:39 +02:00
|
|
|
#define IR_SUB_REFS_COUNT 4
|
2022-04-14 21:40:13 +02:00
|
|
|
|
2022-05-05 21:35:39 +02:00
|
|
|
#define IR_LOAD_SUB_REF 0
|
|
|
|
#define IR_USE_SUB_REF 1
|
|
|
|
#define IR_DEF_SUB_REF 2
|
|
|
|
#define IR_SAVE_SUB_REF 3
|
2022-04-14 21:40:13 +02:00
|
|
|
|
2022-05-05 21:35:39 +02:00
|
|
|
#define IR_LIVE_POS_TO_REF(pos) ((pos) / IR_SUB_REFS_COUNT)
|
|
|
|
#define IR_LIVE_POS_TO_SUB_REF(pos) ((pos) % IR_SUB_REFS_COUNT)
|
2022-04-14 21:40:13 +02:00
|
|
|
|
2022-05-05 21:35:39 +02:00
|
|
|
#define IR_LIVE_POS_FROM_REF(ref) ((ref) * IR_SUB_REFS_COUNT)
|
|
|
|
|
|
|
|
#define IR_START_LIVE_POS_FROM_REF(ref) ((ref) * IR_SUB_REFS_COUNT)
|
|
|
|
#define IR_LOAD_LIVE_POS_FROM_REF(ref) ((ref) * IR_SUB_REFS_COUNT + IR_LOAD_SUB_REF)
|
|
|
|
#define IR_USE_LIVE_POS_FROM_REF(ref) ((ref) * IR_SUB_REFS_COUNT + IR_USE_SUB_REF)
|
|
|
|
#define IR_DEF_LIVE_POS_FROM_REF(ref) ((ref) * IR_SUB_REFS_COUNT + IR_DEF_SUB_REF)
|
|
|
|
#define IR_SAVE_LIVE_POS_FROM_REF(ref) ((ref) * IR_SUB_REFS_COUNT + IR_SAVE_SUB_REF)
|
|
|
|
#define IR_END_LIVE_POS_FROM_REF(ref) ((ref) * IR_SUB_REFS_COUNT + IR_SUB_REFS_COUNT)
|
|
|
|
|
2022-05-06 08:23:14 +02:00
|
|
|
/* ir_use_pos.flags bits */
|
2022-04-28 13:48:43 +02:00
|
|
|
#define IR_USE_MUST_BE_IN_REG (1<<0)
|
|
|
|
#define IR_USE_SHOULD_BE_IN_REG (1<<1)
|
2022-05-12 23:32:37 +02:00
|
|
|
#define IR_PHI_USE (1<<2)
|
2022-04-28 13:48:43 +02:00
|
|
|
|
2022-04-07 10:11:57 +02:00
|
|
|
struct _ir_use_pos {
|
2022-04-14 21:40:13 +02:00
|
|
|
uint16_t op_num; /* 0 - means result */
|
2022-04-07 10:11:57 +02:00
|
|
|
int8_t hint;
|
2022-04-28 13:48:43 +02:00
|
|
|
uint8_t flags;
|
2022-04-21 15:38:18 +02:00
|
|
|
ir_ref hint_ref;
|
2022-04-14 21:40:13 +02:00
|
|
|
ir_live_pos pos;
|
2022-04-07 10:11:57 +02:00
|
|
|
ir_use_pos *next;
|
|
|
|
};
|
|
|
|
|
2022-04-05 23:19:23 +02:00
|
|
|
struct _ir_live_range {
|
2022-04-14 21:40:13 +02:00
|
|
|
ir_live_pos start; /* inclusive */
|
|
|
|
ir_live_pos end; /* exclusive */
|
2022-04-05 23:19:23 +02:00
|
|
|
ir_live_range *next;
|
|
|
|
};
|
|
|
|
|
2022-05-19 08:15:45 +02:00
|
|
|
/* ir_live_interval.flags bits (two low bits are reserved for temporary register number) */
|
|
|
|
#define IR_LIVE_INTERVAL_TEMP_NUM_MASK 0x3
|
2022-05-06 08:23:14 +02:00
|
|
|
#define IR_LIVE_INTERVAL_FIXED (1<<2)
|
|
|
|
#define IR_LIVE_INTERVAL_TEMP (1<<3)
|
|
|
|
#define IR_LIVE_INTERVAL_VAR (1<<4)
|
|
|
|
#define IR_LIVE_INTERVAL_COALESCED (1<<5)
|
2022-05-12 16:43:08 +02:00
|
|
|
#define IR_LIVE_INTERVAL_HAS_HINTS (1<<6)
|
2022-05-19 09:53:08 +02:00
|
|
|
#define IR_LIVE_INTERVAL_MEM_PARAM (1<<7)
|
|
|
|
#define IR_LIVE_INTERVAL_MEM_LOAD (1<<8)
|
2022-05-06 08:23:14 +02:00
|
|
|
|
2022-04-05 23:19:23 +02:00
|
|
|
struct _ir_live_interval {
|
2022-04-21 15:38:18 +02:00
|
|
|
uint8_t type;
|
|
|
|
int8_t reg;
|
2022-05-19 09:53:08 +02:00
|
|
|
uint16_t flags;
|
2022-05-12 16:43:08 +02:00
|
|
|
int32_t vreg;
|
2022-04-21 15:38:18 +02:00
|
|
|
int32_t stack_spill_pos;
|
|
|
|
ir_live_range range;
|
|
|
|
ir_use_pos *use_pos;
|
2022-04-14 21:40:13 +02:00
|
|
|
ir_live_interval *top;
|
|
|
|
ir_live_interval *next;
|
2022-05-12 16:43:08 +02:00
|
|
|
ir_live_interval *list_next; /* linked list of active, inactive or unhandled intervals */
|
2022-04-05 23:19:23 +02:00
|
|
|
};
|
|
|
|
|
2022-05-05 21:35:39 +02:00
|
|
|
#define IR_REG_SPILL_LOAD (1<<6)
|
|
|
|
#define IR_REG_SPILL_STORE (1<<5)
|
|
|
|
#define IR_REG_NUM(r) \
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((r) == IR_REG_NONE ? IR_REG_NONE : ((r) & ~(IR_REG_SPILL_LOAD|IR_REG_SPILL_STORE)))
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typedef int8_t ir_regs[4];
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2022-04-05 23:19:23 +02:00
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typedef struct _ir_ctx {
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ir_insn *ir_base;
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ir_ref insns_count;
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ir_ref insns_limit;
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ir_ref consts_count;
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ir_ref consts_limit;
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uint32_t flags;
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ir_ref fold_cse_limit;
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ir_insn fold_insn;
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ir_use_list *use_lists;
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ir_ref *use_edges;
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uint32_t cfg_blocks_count;
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uint32_t cfg_edges_count;
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ir_block *cfg_blocks;
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uint32_t *cfg_edges;
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int *gcm_blocks;
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uint32_t *rules;
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uint32_t vregs_count;
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uint32_t *vregs;
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ir_live_interval **live_intervals;
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ir_live_range *unused_live_ranges;
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2022-05-05 21:35:39 +02:00
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ir_regs *regs;
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2022-04-05 23:19:23 +02:00
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union {
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uint32_t *prev_insn_len;
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uint32_t *bb_num;
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};
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void *data;
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ir_strtab strtab;
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ir_ref prev_insn_chain[IR_LAST_FOLDABLE + 1];
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ir_ref prev_const_chain[IR_LAST_TYPE];
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} ir_ctx;
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extern const uint8_t ir_type_flags[IR_LAST_TYPE];
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extern const char *ir_type_name[IR_LAST_TYPE];
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extern const char *ir_type_cname[IR_LAST_TYPE];
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extern const uint8_t ir_type_size[IR_LAST_TYPE];
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extern const uint32_t ir_op_flags[IR_LAST_OP];
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extern const char *ir_op_name[IR_LAST_OP];
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IR_ALWAYS_INLINE ir_ref ir_variable_inputs_count(ir_insn *insn)
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{
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uint32_t n = insn->inputs_count;
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if (n == 0) {
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n = 2;
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}
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return n;
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}
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IR_ALWAYS_INLINE ir_ref ir_operands_count(ir_ctx *ctx, ir_insn *insn)
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{
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uint32_t flags = ir_op_flags[insn->op];
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uint32_t n = IR_OPERANDS_COUNT(flags);
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if (n == 4) {
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/* MERGE or CALL */
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n = ir_variable_inputs_count(insn);
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if (n == 0) {
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n = 2;
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}
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} else if (n == 5) {
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/* PHI */
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n = ir_variable_inputs_count(&ctx->ir_base[insn->op1]) + 1;
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}
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return n;
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}
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IR_ALWAYS_INLINE ir_ref ir_input_edges_count(ir_ctx *ctx, ir_insn *insn)
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{
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uint32_t flags = ir_op_flags[insn->op];
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uint32_t n = IR_INPUT_EDGES_COUNT(flags);
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if (n == 4) {
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/* MERGE or CALL */
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n = ir_variable_inputs_count(insn);
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} else if (n == 5) {
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/* PHI */
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n = ir_variable_inputs_count(&ctx->ir_base[insn->op1]) + 1;
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}
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return n;
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}
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/* Basic IR Construction API (implementation in ir.c) */
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void ir_init(ir_ctx *ctx, ir_ref consts_limit, ir_ref insns_limit);
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ir_ref ir_const(ir_ctx *ctx, ir_val val, uint8_t type);
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ir_ref ir_const_i8(ir_ctx *ctx, int8_t c);
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ir_ref ir_const_i16(ir_ctx *ctx, int16_t c);
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ir_ref ir_const_i32(ir_ctx *ctx, int32_t c);
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ir_ref ir_const_i64(ir_ctx *ctx, int64_t c);
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ir_ref ir_const_u8(ir_ctx *ctx, uint8_t c);
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ir_ref ir_const_u16(ir_ctx *ctx, uint16_t c);
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ir_ref ir_const_u32(ir_ctx *ctx, uint32_t c);
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ir_ref ir_const_u64(ir_ctx *ctx, uint64_t c);
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ir_ref ir_const_bool(ir_ctx *ctx, bool c);
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ir_ref ir_const_char(ir_ctx *ctx, char c);
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ir_ref ir_const_float(ir_ctx *ctx, float c);
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ir_ref ir_const_double(ir_ctx *ctx, double c);
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ir_ref ir_const_addr(ir_ctx *ctx, uintptr_t c);
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ir_ref ir_const_func(ir_ctx *ctx, ir_ref str);
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ir_ref ir_const_str(ir_ctx *ctx, ir_ref str);
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ir_ref ir_str(ir_ctx *ctx, const char *s);
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ir_ref ir_strl(ir_ctx *ctx, const char *s, size_t len);
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const char *ir_get_str(ir_ctx *ctx, ir_ref idx);
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ir_ref ir_emit0(ir_ctx *ctx, uint32_t opt);
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ir_ref ir_emit1(ir_ctx *ctx, uint32_t opt, ir_ref op1);
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ir_ref ir_emit2(ir_ctx *ctx, uint32_t opt, ir_ref op1, ir_ref op2);
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ir_ref ir_emit3(ir_ctx *ctx, uint32_t opt, ir_ref op1, ir_ref op2, ir_ref op3);
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ir_ref ir_emit_N(ir_ctx *ctx, uint32_t opt, uint32_t count);
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void ir_set_op(ir_ctx *ctx, ir_ref ref, uint32_t n, ir_ref val);
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ir_ref ir_fold(ir_ctx *ctx, uint32_t opt, ir_ref op1, ir_ref op2, ir_ref op3, ir_insn *op1_insn, ir_insn *op2_insn, ir_insn *op3_insn);
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ir_ref ir_fold0(ir_ctx *ctx, uint32_t opt);
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ir_ref ir_fold1(ir_ctx *ctx, uint32_t opt, ir_ref op1);
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ir_ref ir_fold2(ir_ctx *ctx, uint32_t opt, ir_ref op1, ir_ref op2);
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ir_ref ir_fold3(ir_ctx *ctx, uint32_t opt, ir_ref op1, ir_ref op2, ir_ref op3);
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void ir_bind(ir_ctx *ctx, ir_ref var, ir_ref def);
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#define ir_param(ctx, type, region, name, pos) \
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ir_emit3((ctx), IR_OPT(IR_PARAM, (type)), (region), ir_str((ctx), (name)), (pos))
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#define ir_var(ctx, type, region, name) \
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ir_emit2((ctx), IR_OPT(IR_VAR, (type)), (region), ir_str((ctx), (name)))
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#define ir_set_op1(ctx, ins, val) do { \
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(ctx)->ir_base[(ins)].op1 = (val); \
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} while (0)
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#define ir_set_op2(ctx, ins, val) do { \
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(ctx)->ir_base[(ins)].op2 = (val); \
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} while (0)
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#define ir_set_op3(ctx, ins, val) do { \
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(ctx)->ir_base[(ins)].op3 = (val); \
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} while (0)
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void ir_truncate(ir_ctx *ctx);
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void ir_free(ir_ctx *ctx);
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void ir_print_const(ir_ctx *ctx, ir_insn *insn, FILE *f);
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/* Def -> Use lists */
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void ir_build_def_use_lists(ir_ctx *ctx);
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/* CFG - Control Flow Graph (implementation in ir_cfg.c) */
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int ir_build_cfg(ir_ctx *ctx);
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int ir_build_dominators_tree(ir_ctx *ctx);
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int ir_find_loops(ir_ctx *ctx);
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2022-05-23 23:43:35 +02:00
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int ir_schedule_blocks(ir_ctx *ctx);
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2022-04-05 23:19:23 +02:00
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/* SCCP - Sparse Conditional Constant Propagation (implementation in ir_sccp.c) */
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int ir_sccp(ir_ctx *ctx);
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/* GCM - Global Code Motion (implementation in ir_gcm.c) */
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int ir_gcm(ir_ctx *ctx);
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int ir_schedule(ir_ctx *ctx);
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/* Liveness & Register Allocation (implementation in ir_ra.c) */
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2022-05-06 15:19:57 +02:00
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typedef int (*emit_copy_t)(ir_ctx *ctx, uint8_t type, ir_ref from, ir_ref to);
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2022-04-05 23:19:23 +02:00
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2022-05-13 08:22:31 +02:00
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#ifdef IR_DEBUG_REGSET
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2022-04-27 13:47:52 +02:00
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extern uint32_t debug_regset;
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#endif
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2022-04-05 23:19:23 +02:00
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int ir_assign_virtual_registers(ir_ctx *ctx);
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int ir_compute_live_ranges(ir_ctx *ctx);
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int ir_coalesce(ir_ctx *ctx);
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int ir_reg_alloc(ir_ctx *ctx);
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int ir_compute_dessa_moves(ir_ctx *ctx);
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int ir_gen_dessa_moves(ir_ctx *ctx, int b, emit_copy_t emit_copy);
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void ir_free_live_ranges(ir_live_range *live_range);
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void ir_free_live_intervals(ir_live_interval **live_intervals, int count);
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/* Target CPU instruction selection and code geneartion (see ir_x86.c) */
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int ir_match(ir_ctx *ctx);
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void *ir_emit(ir_ctx *ctx, size_t *size);
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const char *ir_reg_name(int8_t reg, ir_type type);
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/* Target CPU disassembler (implementation in ir_disasm.c) */
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int ir_disasm_init(void);
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void ir_disasm_free(void);
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void ir_disasm_add_symbol(const char *name, uint64_t addr, uint64_t size);
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int ir_disasm(const char *name, const void *start, size_t size);
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/* Linux perf interface (implementation in ir_perf.c) */
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void ir_perf_jitdump_open(void);
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void ir_perf_jitdump_close(void);
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void ir_perf_jitdump_register(const char *name, const void *start, size_t size);
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void ir_perf_map_register(const char *name, const void *start, size_t size);
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/* GDB JIT interface (implementation in ir_gdb.c) */
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int ir_gdb_register(const char *name,
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const void *start,
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size_t size,
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uint32_t sp_offset,
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uint32_t sp_adjustment);
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void ir_gdb_unregister_all(void);
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bool ir_gdb_present(void);
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/* IR load API (implementation in ir_load.c) */
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void ir_loader_init(void);
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void ir_loader_free(void);
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int ir_load(ir_ctx *ctx, FILE *f);
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/* IR save API (implementation in ir_save.c) */
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void ir_save(ir_ctx *ctx, FILE *f);
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/* IR debug dump API (implementation in ir_dump.c) */
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void ir_dump(ir_ctx *ctx, FILE *f);
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void ir_dump_dot(ir_ctx *ctx, FILE *f);
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void ir_dump_use_lists(ir_ctx *ctx, FILE *f);
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void ir_dump_cfg(ir_ctx *ctx, FILE *f);
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void ir_dump_gcm(ir_ctx *ctx, FILE *f);
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void ir_dump_live_ranges(ir_ctx *ctx, FILE *f);
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/* IR to C conversion (implementation in ir_emit_c.c) */
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int ir_emit_c(ir_ctx *ctx, FILE *f);
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/* IR verification API (implementation in ir_check.c) */
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void ir_check(ir_ctx *ctx);
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/* String Tables API (implementation in ir_strtab.c) */
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#define ir_strtab_count(strtab) (strtab)->count
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typedef void (*ir_strtab_apply_t)(const char *str, uint32_t len, ir_ref val);
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void ir_strtab_init(ir_strtab *strtab, uint32_t count, uint32_t buf_size);
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ir_ref ir_strtab_lookup(ir_strtab *strtab, const char *str, uint32_t len, ir_ref val);
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ir_ref ir_strtab_find(ir_strtab *strtab, const char *str, uint32_t len);
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ir_ref ir_strtab_update(ir_strtab *strtab, const char *str, uint32_t len, ir_ref val);
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const char *ir_strtab_str(ir_strtab *strtab, ir_ref idx);
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void ir_strtab_apply(ir_strtab *strtab, ir_strtab_apply_t func);
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void ir_strtab_free(ir_strtab *strtab);
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#endif /* IR_H */
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