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26 lines
420 B
Plaintext
26 lines
420 B
Plaintext
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--TEST--
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015: Register Allocation (SHL + SHL + reuse/vreg hint)
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--TARGET--
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x86
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--ARGS--
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-S
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--CODE--
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{
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l_1 = START(l_4);
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uint32_t x = PARAM(l_1, "x", 1);
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uint32_t y = PARAM(l_1, "y", 2);
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uint32_t ret = SHL(x, y);
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uint32_t ret2 = SHL(y, ret);
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l_4 = RETURN(l_1, ret2);
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}
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--EXPECT--
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test:
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movl 4(%esp), %ecx
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movl 8(%esp), %eax
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movl %ecx, %edx
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movl %eax, %ecx
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shll %cl, %edx
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movl %edx, %ecx
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shll %cl, %eax
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retl
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