From 16b8e1cf4b5cf62135f7632bf944539dea69ec9d Mon Sep 17 00:00:00 2001
From: Dmitry Stogov <dmitry@zend.com>
Date: Thu, 14 Dec 2023 14:19:27 +0300
Subject: [PATCH] Fixed code generation for imul

---
 ir_x86.dasc | 40 ++++++++++++++++++++++++++++------------
 1 file changed, 28 insertions(+), 12 deletions(-)

diff --git a/ir_x86.dasc b/ir_x86.dasc
index 4e8b998..5b5689b 100644
--- a/ir_x86.dasc
+++ b/ir_x86.dasc
@@ -3899,20 +3899,36 @@ static void ir_emit_mul_div_mod(ir_ctx *ctx, ir_ref def, ir_insn *insn)
 		ir_emit_load(ctx, type, op2_reg, op2);
 	}
 	if (insn->op == IR_MUL || insn->op == IR_MUL_OV) {
-		IR_ASSERT(!IR_IS_TYPE_SIGNED(insn->type));
-		if (op2_reg != IR_REG_NONE) {
-			if (IR_REG_SPILLED(op2_reg)) {
-				op2_reg = IR_REG_NUM(op2_reg);
-				ir_emit_load(ctx, type, op2_reg, op2);
-			}
-			|	ASM_REG_OP mul, type, op2_reg
-		} else {
-			if (ir_rule(ctx, op2) & IR_FUSED) {
-				offset = ir_fuse_load(ctx, op2, &op2_reg);
+		if (IR_IS_TYPE_SIGNED(insn->type)) {
+			if (op2_reg != IR_REG_NONE) {
+				if (IR_REG_SPILLED(op2_reg)) {
+					op2_reg = IR_REG_NUM(op2_reg);
+					ir_emit_load(ctx, type, op2_reg, op2);
+				}
+				|	ASM_REG_OP imul, type, op2_reg
 			} else {
-				offset = ir_ref_spill_slot(ctx, op2, &op2_reg);
+				if (ir_rule(ctx, op2) & IR_FUSED) {
+					offset = ir_fuse_load(ctx, op2, &op2_reg);
+				} else {
+					offset = ir_ref_spill_slot(ctx, op2, &op2_reg);
+				}
+				|	ASM_MEM_OP imul, type, [Ra(op2_reg)+offset]
+			}
+		} else {
+			if (op2_reg != IR_REG_NONE) {
+				if (IR_REG_SPILLED(op2_reg)) {
+					op2_reg = IR_REG_NUM(op2_reg);
+					ir_emit_load(ctx, type, op2_reg, op2);
+				}
+				|	ASM_REG_OP mul, type, op2_reg
+			} else {
+				if (ir_rule(ctx, op2) & IR_FUSED) {
+					offset = ir_fuse_load(ctx, op2, &op2_reg);
+				} else {
+					offset = ir_ref_spill_slot(ctx, op2, &op2_reg);
+				}
+				|	ASM_MEM_OP mul, type, [Ra(op2_reg)+offset]
 			}
-			|	ASM_MEM_OP mul, type, [Ra(op2_reg)+offset]
 		}
 	} else {
 		if (IR_IS_TYPE_SIGNED(type)) {