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https://github.com/danog/ir.git
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Better debug logging
This commit is contained in:
Dmitry Stogov
parent
2e3ba321f8
commit
23945c4bdc
151
ir_ra.c
151
ir_ra.c
@ -991,6 +991,68 @@ typedef struct _ir_lsra_data {
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uint32_t stack_frame_size;
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} ir_lsra_data;
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#ifdef IR_DEBUG
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# define IR_LOG_LSRA(action, vreg, ival, comment) do { \
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if (ctx->flags & IR_DEBUG_RA) { \
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int _vreg = (vreg); \
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ir_live_interval *_ival = (ival); \
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ir_live_pos _start = _ival->range.start; \
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ir_live_pos _end = ir_live_range_end(_ival); \
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fprintf(stderr, action " R%d [%d.%d...%d.%d)" comment "\n", \
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_vreg, \
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IR_LIVE_POS_TO_REF(_start), IR_LIVE_POS_TO_SUB_REF(_start), \
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IR_LIVE_POS_TO_REF(_end), IR_LIVE_POS_TO_SUB_REF(_end)); \
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} \
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} while (0)
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# define IR_LOG_LSRA_ASSIGN(action, vreg, ival, comment) do { \
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if (ctx->flags & IR_DEBUG_RA) { \
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int _vreg = (vreg); \
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ir_live_interval *_ival = (ival); \
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ir_live_pos _start = _ival->range.start; \
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ir_live_pos _end = ir_live_range_end(_ival); \
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fprintf(stderr, action " R%d [%d.%d...%d.%d) to %s" comment "\n", \
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_vreg, \
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IR_LIVE_POS_TO_REF(_start), IR_LIVE_POS_TO_SUB_REF(_start), \
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IR_LIVE_POS_TO_REF(_end), IR_LIVE_POS_TO_SUB_REF(_end), \
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ir_reg_name(_ival->reg, _ival->type)); \
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} \
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} while (0)
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# define IR_LOG_LSRA_SPLIT(vreg, ival, pos) do { \
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if (ctx->flags & IR_DEBUG_RA) { \
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int _vreg = (vreg); \
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ir_live_interval *_ival = (ival); \
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ir_live_pos _start = _ival->range.start; \
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ir_live_pos _end = ir_live_range_end(_ival); \
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ir_live_pos _pos = (pos); \
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fprintf(stderr, " ---- Split R%d [%d.%d...%d.%d) at %d.%d\n", \
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_vreg, \
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IR_LIVE_POS_TO_REF(_start), IR_LIVE_POS_TO_SUB_REF(_start), \
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IR_LIVE_POS_TO_REF(_end), IR_LIVE_POS_TO_SUB_REF(_end), \
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IR_LIVE_POS_TO_REF(_pos), IR_LIVE_POS_TO_SUB_REF(_pos)); \
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} \
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} while (0)
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# define IR_LOG_LSRA_CONFLICT(action, vreg, ival, pos) do { \
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if (ctx->flags & IR_DEBUG_RA) { \
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int _vreg = (vreg); \
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ir_live_interval *_ival = (ival); \
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ir_live_pos _start = _ival->range.start; \
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ir_live_pos _end = ir_live_range_end(_ival); \
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ir_live_pos _pos = (pos); \
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fprintf(stderr, action " R%d [%d.%d...%d.%d) assigned to %s at %d.%d\n", \
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_vreg, \
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IR_LIVE_POS_TO_REF(_start), IR_LIVE_POS_TO_SUB_REF(_start), \
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IR_LIVE_POS_TO_REF(_end), IR_LIVE_POS_TO_SUB_REF(_end), \
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ir_reg_name(_ival->reg, _ival->type), \
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IR_LIVE_POS_TO_REF(_pos), IR_LIVE_POS_TO_SUB_REF(_pos)); \
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} \
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} while (0)
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#else
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# define IR_LOG_LSRA(action, vreg, ival, comment)
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# define IR_LOG_LSRA_ASSIGN(vreg, ival, comment)
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# define IR_LOG_LSRA_SPLIT(vreg, ival, pos)
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# define IR_LOG_LSRA_CONFLICT(action, vreg, ival, pos);
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#endif
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static ir_live_pos ir_live_range_end(ir_live_interval *ival)
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{
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ir_live_range *live_range = &ival->range;
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@ -1015,12 +1077,13 @@ static bool ir_live_range_covers(ir_live_interval *ival, ir_live_pos position)
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return 0;
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}
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static ir_live_interval *ir_split_interval_at(ir_live_interval *ival, ir_live_pos pos)
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static ir_live_interval *ir_split_interval_at(ir_ctx *ctx, int v, ir_live_interval *ival, ir_live_pos pos)
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{
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ir_live_interval *child;
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ir_live_range *p, *prev;
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ir_use_pos *use_pos, *prev_use_pos;
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IR_LOG_LSRA_SPLIT(v, ival, pos);
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IR_ASSERT(pos > ival->range.start);
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p = &ival->range;
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@ -1232,6 +1295,7 @@ static ir_reg ir_try_allocate_free_reg(ir_ctx *ctx, int current, uint32_t len, i
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reg = ir_try_allocate_preferred_reg(ctx, ival, freeUntilPos);
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if (reg != IR_REG_NONE) {
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ival->reg = reg;
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IR_LOG_LSRA_ASSIGN(" ---- Assign", current, ival, " (hint available without spilling)");
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return reg;
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}
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@ -1258,19 +1322,19 @@ static ir_reg ir_try_allocate_free_reg(ir_ctx *ctx, int current, uint32_t len, i
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} else if (ir_live_range_end(ival) <= pos) {
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/* register available for the whole interval */
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ival->reg = reg;
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IR_LOG_LSRA_ASSIGN(" ---- Assign", current, ival, " (available without spilling)");
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return reg;
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} else if (pos > ival->range.start) {
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/* register available for the first part of the interval */
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ival->reg = reg;
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/* split current before freeUntilPos[reg] */
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ir_split_interval_at(ival, pos); // TODO: Split/Spill Pos
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ir_split_interval_at(ctx, current, ival, pos); // TODO: Split/Spill Pos
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ival->reg = reg;
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IR_LOG_LSRA_ASSIGN(" ---- Assign", current, ival, " (available without spilling for the first part)");
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#ifdef IR_DEBUG
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if (ctx->flags & IR_DEBUG_RA) {
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ir_dump_live_ranges(ctx, stderr);
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}
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// if (ctx->flags & IR_DEBUG_RA) {
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// ir_dump_live_ranges(ctx, stderr);
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// }
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#endif
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return reg;
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} else {
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return IR_REG_NONE;
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@ -1297,6 +1361,7 @@ static ir_reg ir_allocate_blocked_reg(ir_ctx *ctx, int current, uint32_t len, ir
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}
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if (!use_pos) {
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/* spill */
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IR_LOG_LSRA(" ---- Spill", current, ival, " (no use pos that must be in reg)");
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return IR_REG_NONE;
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}
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next_use_pos = use_pos->pos;
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@ -1405,47 +1470,52 @@ static ir_reg ir_allocate_blocked_reg(ir_ctx *ctx, int current, uint32_t len, ir
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ir_live_pos split_pos = ir_find_optimal_split_position(ctx, ival->range.start, next_use_pos - 1);
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if (split_pos > ival->range.start) {
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ir_live_interval *child = ir_split_interval_at(ival, split_pos);
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ir_live_interval *child = ir_split_interval_at(ctx, current, ival, split_pos);
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ctx->live_intervals[current] = child;
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ir_add_to_unhandled(ctx, unhandled, current);
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IR_LOG_LSRA(" ---- Spill", current, ival, " (all others are used before)");
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#ifdef IR_DEBUG
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if (ctx->flags & IR_DEBUG_RA) {
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ir_dump_live_ranges(ctx, stderr);
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}
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// if (ctx->flags & IR_DEBUG_RA) {
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// ir_dump_live_ranges(ctx, stderr);
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// }
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#endif
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return IR_REG_NONE;
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}
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}
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/* current.reg = reg */
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ival->reg = reg;
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if (ir_live_range_end(ival) > blockPos[reg]) {
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/* spilling make a register free only for the first part of current */
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/* split current at optimal position before block_pos[reg] */
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ir_split_interval_at(ival, blockPos[reg]); // TODO: Split Pos
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ir_split_interval_at(ctx, current, ival, blockPos[reg]); // TODO: Split Pos
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}
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/* spill intervals that currently block reg */
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IR_BITSET_FOREACH(active, len, i) {
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if (reg == ctx->live_intervals[i]->reg) {
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ir_live_interval *other = ctx->live_intervals[i];
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if (reg == other->reg) {
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/* split active interval for reg at position */
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ir_live_pos overlap = ir_vregs_overlap(ctx, current, i);
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if (overlap) {
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IR_ASSERT(ctx->live_intervals[i]->type != IR_VOID);
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ir_live_interval *child = ir_split_interval_at(ctx->live_intervals[i], ival->range.start); // TODO: Split Pos
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IR_ASSERT(other->type != IR_VOID);
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IR_LOG_LSRA_CONFLICT(" ---- Conflict with active", i, other, overlap);
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ir_live_interval *child = ir_split_interval_at(ctx, i, other, ival->range.start); // TODO: Split Pos
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ir_bitset_excl(active, i);
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ctx->live_intervals[i] = child;
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IR_LOG_LSRA(" ---- Finish", i, other, "");
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if (child->use_pos) {
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ir_live_pos split_pos = ir_find_optimal_split_position(ctx, ival->range.start, child->use_pos->pos - 1);
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if (split_pos > ival->range.start) {
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child = ir_split_interval_at(child, split_pos);
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other = child;
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child = ir_split_interval_at(ctx, i, child, split_pos);
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ctx->live_intervals[i] = child;
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IR_LOG_LSRA(" ---- Spill", i, other, "");
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}
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IR_LOG_LSRA(" ---- Queue", i, child, "");
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ir_add_to_unhandled(ctx, unhandled, i);
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}
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}
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@ -1456,20 +1526,26 @@ static ir_reg ir_allocate_blocked_reg(ir_ctx *ctx, int current, uint32_t len, ir
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/* split any inactive interval for reg at the end of its lifetime hole */
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IR_BITSET_FOREACH(inactive, len, i) {
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/* freeUntilPos[it.reg] = next intersection of it with current */
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if (reg == ctx->live_intervals[i]->reg) {
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ir_live_interval *other = ctx->live_intervals[i];
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if (reg == other->reg) {
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ir_live_pos overlap = ir_vregs_overlap(ctx, current, i);
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if (overlap) {
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IR_ASSERT(ctx->live_intervals[i]->type != IR_VOID);
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ir_split_interval_at(ctx->live_intervals[i], overlap); // TODO: Split Pos
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IR_ASSERT(other->type != IR_VOID);
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IR_LOG_LSRA_CONFLICT(" ---- Conflict with inactive", i, other, overlap);
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ir_split_interval_at(ctx, i, other, overlap); // TODO: Split Pos
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}
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}
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} IR_BITSET_FOREACH_END();
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/* current.reg = reg */
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ival->reg = reg;
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IR_LOG_LSRA_ASSIGN(" ---- Assign", current, ival, " (after splitting others)");
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#ifdef IR_DEBUG
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if (ctx->flags & IR_DEBUG_RA) {
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ir_dump_live_ranges(ctx, stderr);
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}
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// if (ctx->flags & IR_DEBUG_RA) {
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// ir_dump_live_ranges(ctx, stderr);
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// }
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#endif
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return reg;
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@ -1551,6 +1627,14 @@ static int ir_linear_scan(ir_ctx *ctx)
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qsort_r(unhandled.a.refs, ir_list_len(&unhandled), sizeof(ir_ref), ir_live_range_cmp, ctx);
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#ifdef IR_DEBUG
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if (ctx->flags & IR_DEBUG_RA) {
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fprintf(stderr, "----\n");
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ir_dump_live_ranges(ctx, stderr);
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fprintf(stderr, "---- Start LSRA\n");
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}
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#endif
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while (1) {
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if (ir_list_len(&unhandled) == 0) {
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position = 0x7fffffff;
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@ -1566,15 +1650,18 @@ static int ir_linear_scan(ir_ctx *ctx)
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if (position < 0x7fffffff) {
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ir_bitset_excl(active, current);
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ctx->live_intervals[current] = ctx->live_intervals[current]->next;
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ival = ctx->live_intervals[current] = ctx->live_intervals[current]->next;
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} else {
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break;
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}
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} else {
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current = ir_list_pop(&unhandled);
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position = ctx->live_intervals[current]->range.start;
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ival = ctx->live_intervals[current];
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position = ival->range.start;
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}
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IR_LOG_LSRA(" ---- Processing", current, ival, "...");
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/* for each interval i in active */
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IR_BITSET_FOREACH(active, len, i) {
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ival = ctx->live_intervals[i];
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@ -1683,6 +1770,14 @@ static int ir_linear_scan(ir_ctx *ctx)
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}
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}
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#ifdef IR_DEBUG
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if (ctx->flags & IR_DEBUG_RA) {
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fprintf(stderr, "---- Finish LSRA\n");
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ir_dump_live_ranges(ctx, stderr);
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fprintf(stderr, "----\n");
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}
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#endif
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return 1;
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}
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