From 37dececa71b80bfe0087e56ab4671aba6526964d Mon Sep 17 00:00:00 2001 From: Dmitry Stogov Date: Tue, 8 Nov 2022 11:56:22 +0300 Subject: [PATCH] Add more tests (8 tests ara failed on 32-bit x86) --- tests/aarch64/abs_001.irt | 18 +++ tests/aarch64/abs_002.irt | 17 +++ tests/aarch64/abs_003.irt | 17 +++ tests/aarch64/add_001.irt | 18 +++ tests/aarch64/add_002.irt | 18 +++ tests/aarch64/add_003.irt | 18 +++ tests/aarch64/add_004.irt | 18 +++ tests/aarch64/add_005.irt | 18 +++ tests/aarch64/add_006.irt | 18 +++ tests/aarch64/add_007.irt | 18 +++ tests/aarch64/add_008.irt | 18 +++ tests/aarch64/add_009.irt | 19 +++ tests/aarch64/add_010.irt | 18 +++ tests/aarch64/add_011.irt | 23 +++ tests/aarch64/add_012.irt | 23 +++ tests/aarch64/add_ov_001.irt | 20 +++ tests/aarch64/add_ov_002.irt | 20 +++ tests/aarch64/add_ov_003.irt | 30 ++++ tests/aarch64/add_ov_004.irt | 32 +++++ tests/aarch64/alloca_001.irt | 22 +++ tests/aarch64/alloca_002.irt | 24 ++++ tests/aarch64/bswap_001.irt | 17 +++ tests/aarch64/conv_001.irt | 17 +++ tests/aarch64/conv_002.irt | 17 +++ tests/aarch64/conv_003.irt | 16 +++ tests/aarch64/conv_004.irt | 17 +++ tests/aarch64/conv_005.irt | 17 +++ tests/aarch64/conv_006.irt | 17 +++ tests/aarch64/conv_007.irt | 17 +++ tests/aarch64/conv_008.irt | 17 +++ tests/aarch64/conv_009.irt | 17 +++ tests/aarch64/conv_010.irt | 17 +++ tests/aarch64/conv_011.irt | 16 +++ tests/aarch64/div_001.irt | 18 +++ tests/aarch64/div_002.irt | 19 +++ tests/aarch64/div_003.irt | 18 +++ tests/aarch64/div_004.irt | 19 +++ tests/aarch64/div_005.irt | 18 +++ tests/aarch64/div_006.irt | 18 +++ tests/aarch64/eq_001.irt | 19 +++ tests/aarch64/eq_002.irt | 19 +++ tests/aarch64/eq_003.irt | 19 +++ tests/aarch64/eq_004.irt | 20 +++ tests/aarch64/eq_005.irt | 20 +++ tests/aarch64/ge_001.irt | 19 +++ tests/aarch64/ge_002.irt | 19 +++ tests/aarch64/ge_003.irt | 19 +++ tests/aarch64/ge_004.irt | 20 +++ tests/aarch64/ge_005.irt | 20 +++ tests/aarch64/gt_001.irt | 19 +++ tests/aarch64/gt_002.irt | 19 +++ tests/aarch64/gt_003.irt | 19 +++ tests/aarch64/gt_004.irt | 20 +++ tests/aarch64/gt_005.irt | 20 +++ tests/aarch64/if_001.irt | 31 ++++ tests/aarch64/le_001.irt | 19 +++ tests/aarch64/le_002.irt | 19 +++ tests/aarch64/le_003.irt | 19 +++ tests/aarch64/le_004.irt | 20 +++ tests/aarch64/le_005.irt | 20 +++ tests/aarch64/lt_001.irt | 19 +++ tests/aarch64/lt_002.irt | 19 +++ tests/aarch64/lt_003.irt | 19 +++ tests/aarch64/lt_004.irt | 20 +++ tests/aarch64/lt_005.irt | 20 +++ tests/aarch64/min_001.irt | 18 +++ tests/aarch64/min_002.irt | 18 +++ tests/aarch64/min_003.irt | 18 +++ tests/aarch64/min_004.irt | 18 +++ tests/aarch64/min_005.irt | 19 +++ tests/aarch64/min_006.irt | 19 +++ tests/aarch64/min_007.irt | 20 +++ tests/aarch64/mod_001.irt | 19 +++ tests/aarch64/mod_002.irt | 20 +++ tests/aarch64/mod_003.irt | 19 +++ tests/aarch64/mod_004.irt | 20 +++ tests/aarch64/mod_005.irt | 18 +++ tests/aarch64/mul_001.irt | 18 +++ tests/aarch64/mul_002.irt | 19 +++ tests/aarch64/mul_003.irt | 18 +++ tests/aarch64/mul_004.irt | 19 +++ tests/aarch64/mul_005.irt | 18 +++ tests/aarch64/mul_006.irt | 18 +++ tests/aarch64/mul_007.irt | 18 +++ tests/aarch64/mul_ov_001.irt | 23 +++ tests/aarch64/mul_ov_002.irt | 22 +++ tests/aarch64/ne_001.irt | 19 +++ tests/aarch64/ne_002.irt | 19 +++ tests/aarch64/ne_003.irt | 19 +++ tests/aarch64/ne_004.irt | 20 +++ tests/aarch64/ne_005.irt | 20 +++ tests/aarch64/neg_001.irt | 17 +++ tests/aarch64/neg_002.irt | 17 +++ tests/aarch64/neg_003.irt | 17 +++ tests/aarch64/not_001.irt | 17 +++ tests/aarch64/not_002.irt | 18 +++ tests/aarch64/ra_001.irt | 21 +++ tests/aarch64/ra_002.irt | 21 +++ tests/aarch64/ra_003.irt | 22 +++ tests/aarch64/ra_004.irt | 21 +++ tests/aarch64/ra_005.irt | 21 +++ tests/aarch64/ra_006.irt | 22 +++ tests/aarch64/ra_007.irt | 22 +++ tests/aarch64/ra_008.irt | 22 +++ tests/aarch64/ra_009.irt | 23 +++ tests/aarch64/ra_010.irt | 21 +++ tests/aarch64/ra_011.irt | 21 +++ tests/aarch64/ra_012.irt | 22 +++ tests/aarch64/ra_013.irt | 27 ++++ tests/aarch64/ra_014.irt | 21 +++ tests/aarch64/ra_015.irt | 20 +++ tests/aarch64/rol_001.irt | 19 +++ tests/aarch64/rol_002.irt | 18 +++ tests/aarch64/rol_003.irt | 19 +++ tests/aarch64/rol_004.irt | 20 +++ tests/aarch64/ror_001.irt | 18 +++ tests/aarch64/ror_002.irt | 18 +++ tests/aarch64/ror_003.irt | 18 +++ tests/aarch64/ror_004.irt | 19 +++ tests/aarch64/shl_001.irt | 18 +++ tests/aarch64/shl_002.irt | 18 +++ tests/aarch64/shl_003.irt | 18 +++ tests/aarch64/shl_004.irt | 19 +++ tests/aarch64/sub_001.irt | 18 +++ tests/aarch64/sub_002.irt | 18 +++ tests/aarch64/sub_003.irt | 18 +++ tests/aarch64/sub_004.irt | 19 +++ tests/aarch64/sub_005.irt | 18 +++ tests/aarch64/sub_006.irt | 18 +++ tests/aarch64/sub_007.irt | 18 +++ tests/aarch64/sub_008.irt | 18 +++ tests/aarch64/sub_009.irt | 19 +++ tests/aarch64/sub_010.irt | 18 +++ tests/aarch64/sub_011.irt | 23 +++ tests/aarch64/sub_012.irt | 23 +++ tests/aarch64/uge_001.irt | 19 +++ tests/aarch64/uge_002.irt | 19 +++ tests/aarch64/uge_003.irt | 18 +++ tests/aarch64/ugt_001.irt | 19 +++ tests/aarch64/ugt_002.irt | 19 +++ tests/aarch64/ugt_003.irt | 19 +++ tests/aarch64/ule_001.irt | 19 +++ tests/aarch64/ule_002.irt | 19 +++ tests/aarch64/ule_003.irt | 19 +++ tests/aarch64/ult_001.irt | 19 +++ tests/aarch64/ult_002.irt | 19 +++ tests/aarch64/ult_003.irt | 18 +++ tests/debug.aarch64/args_001.irt | 57 ++++++++ tests/debug.aarch64/args_002.irt | 72 ++++++++++ tests/debug.aarch64/call-O0.irt | 37 +++++ tests/debug.aarch64/call.irt | 35 +++++ tests/debug.aarch64/call2.irt | 42 ++++++ tests/debug.aarch64/call3.irt | 41 ++++++ tests/debug.aarch64/call_002.irt | 28 ++++ tests/debug.aarch64/call_alloca.irt | 68 +++++++++ tests/debug.aarch64/call_vaddr.irt | 66 +++++++++ tests/debug.aarch64/combo_001.irt | 43 ++++++ tests/debug.aarch64/combo_002.irt | 55 +++++++ tests/debug.aarch64/combo_003.irt | 55 +++++++ tests/debug.aarch64/combo_004.irt | 46 ++++++ tests/debug.aarch64/dce_001.irt | 41 ++++++ tests/debug.aarch64/dessa_001.irt | 32 +++++ tests/debug.aarch64/dessa_002.irt | 34 +++++ tests/debug.aarch64/dessa_003.irt | 45 ++++++ tests/debug.aarch64/fig-O0.irt | 198 ++++++++++++++++++++++++++ tests/debug.aarch64/fig.irt | 96 +++++++++++++ tests/debug.aarch64/ijmp_001.irt | 15 ++ tests/debug.aarch64/loop_001.irt | 40 ++++++ tests/debug.aarch64/loop_002.irt | 68 +++++++++ tests/debug.aarch64/memop_001.irt | 27 ++++ tests/debug.aarch64/memop_002.irt | 27 ++++ tests/debug.aarch64/memop_003.irt | 29 ++++ tests/debug.aarch64/memop_004.irt | 27 ++++ tests/debug.aarch64/memop_005.irt | 27 ++++ tests/debug.aarch64/memop_006.irt | 26 ++++ tests/debug.aarch64/memop_007.irt | 27 ++++ tests/debug.aarch64/memop_008.irt | 22 +++ tests/debug.aarch64/params_001.irt | 44 ++++++ tests/debug.aarch64/params_002.irt | 44 ++++++ tests/debug.aarch64/params_003.irt | 52 +++++++ tests/debug.aarch64/regset-fib.irt | 135 ++++++++++++++++++ tests/debug.aarch64/regset-fib2.irt | 158 +++++++++++++++++++++ tests/debug.aarch64/regset-fibi.irt | 113 +++++++++++++++ tests/debug.aarch64/regset-test.irt | 205 +++++++++++++++++++++++++++ tests/debug.aarch64/sccp_001.irt | 19 +++ tests/debug.aarch64/sccp_002.irt | 81 +++++++++++ tests/debug.aarch64/switch_001.irt | 62 ++++++++ tests/debug.aarch64/switch_002.irt | 38 +++++ tests/debug.aarch64/switch_003.irt | 64 +++++++++ tests/debug.aarch64/tailcall_001.irt | 31 ++++ tests/debug.aarch64/tailcall_002.irt | 24 ++++ tests/debug.aarch64/test-O0.irt | 131 +++++++++++++++++ tests/debug.aarch64/test.irt | 89 ++++++++++++ tests/debug.aarch64/test_mem.irt | 141 ++++++++++++++++++ tests/debug.aarch64/test_var-O0.irt | 144 +++++++++++++++++++ tests/debug.aarch64/test_var.irt | 132 +++++++++++++++++ tests/debug.x86/args_001.irt | 51 +++++++ tests/debug.x86/args_002.irt | 79 +++++++++++ tests/debug.x86/call-O0.irt | 39 +++++ tests/debug.x86/call.irt | 35 +++++ tests/debug.x86/call2.irt | 45 ++++++ tests/debug.x86/call3.irt | 44 ++++++ tests/debug.x86/call_002.irt | 29 ++++ tests/debug.x86/call_alloca.irt | 66 +++++++++ tests/debug.x86/call_vaddr.irt | 60 ++++++++ tests/debug.x86/combo_001.irt | 44 ++++++ tests/debug.x86/combo_002.irt | 56 ++++++++ tests/debug.x86/combo_003.irt | 56 ++++++++ tests/debug.x86/combo_004.irt | 48 +++++++ tests/debug.x86/dce_001.irt | 42 ++++++ tests/debug.x86/dessa_001.irt | 33 +++++ tests/debug.x86/dessa_002.irt | 35 +++++ tests/debug.x86/dessa_003.irt | 55 +++++++ tests/debug.x86/fig-O0.irt | 175 +++++++++++++++++++++++ tests/debug.x86/fig.irt | 114 +++++++++++++++ tests/debug.x86/ijmp_001.irt | 15 ++ tests/debug.x86/lea_001.irt | 24 ++++ tests/debug.x86/loop_001.irt | 41 ++++++ tests/debug.x86/loop_002.irt | 68 +++++++++ tests/debug.x86/memop_001.irt | 26 ++++ tests/debug.x86/memop_002.irt | 26 ++++ tests/debug.x86/memop_003.irt | 28 ++++ tests/debug.x86/memop_004.irt | 26 ++++ tests/debug.x86/memop_005.irt | 26 ++++ tests/debug.x86/memop_006.irt | 25 ++++ tests/debug.x86/memop_007.irt | 26 ++++ tests/debug.x86/memop_008.irt | 21 +++ tests/debug.x86/params_001.irt | 59 ++++++++ tests/debug.x86/params_002.irt | 47 ++++++ tests/debug.x86/params_003.irt | 57 ++++++++ tests/debug.x86/regset-fib.irt | 137 ++++++++++++++++++ tests/debug.x86/regset-fib2.irt | 163 +++++++++++++++++++++ tests/debug.x86/regset-fibi.irt | 117 +++++++++++++++ tests/debug.x86/regset-test.irt | 181 +++++++++++++++++++++++ tests/debug.x86/sccp_001.irt | 19 +++ tests/debug.x86/sccp_002.irt | 82 +++++++++++ tests/debug.x86/swap_001.irt | 28 ++++ tests/debug.x86/swap_002.irt | 30 ++++ tests/debug.x86/switch_001.irt | 62 ++++++++ tests/debug.x86/switch_002.irt | 38 +++++ tests/debug.x86/tailcall_001.irt | 31 ++++ tests/debug.x86/tailcall_002.irt | 24 ++++ tests/debug.x86/test-O0.irt | 120 ++++++++++++++++ tests/debug.x86/test-mavx.irt | 89 ++++++++++++ tests/debug.x86/test.irt | 93 ++++++++++++ tests/debug.x86/test_mem.irt | 137 ++++++++++++++++++ tests/debug.x86/test_var-O0.irt | 134 +++++++++++++++++ tests/debug.x86/test_var.irt | 126 ++++++++++++++++ tests/debug/regset-fib.irt | 138 ++++++++++++++++++ tests/debug/regset-fib2.irt | 163 +++++++++++++++++++++ tests/debug/regset-fibi.irt | 119 ++++++++++++++++ tests/debug/regset-test.irt | 184 ++++++++++++++++++++++++ tests/x86/abs_001.irt | 21 +++ tests/x86/abs_002.irt | 26 ++++ tests/x86/abs_003.irt | 26 ++++ tests/x86/add_001.irt | 20 +++ tests/x86/add_002.irt | 19 +++ tests/x86/add_003.irt | 20 +++ tests/x86/add_004.irt | 19 +++ tests/x86/add_005.irt | 23 +++ tests/x86/add_006.irt | 23 +++ tests/x86/add_007.irt | 23 +++ tests/x86/add_008.irt | 23 +++ tests/x86/add_009.irt | 20 +++ tests/x86/add_010.irt | 19 +++ tests/x86/add_011.irt | 27 ++++ tests/x86/add_012.irt | 27 ++++ tests/x86/add_ov_001.irt | 21 +++ tests/x86/add_ov_002.irt | 21 +++ tests/x86/add_ov_003.irt | 31 ++++ tests/x86/add_ov_004.irt | 33 +++++ tests/x86/alloca_001.irt | 22 +++ tests/x86/alloca_002.irt | 25 ++++ tests/x86/bswap_001.irt | 18 +++ tests/x86/conv_001.irt | 17 +++ tests/x86/conv_002.irt | 17 +++ tests/x86/conv_003.irt | 18 +++ tests/x86/conv_004.irt | 17 +++ tests/x86/conv_005.irt | 18 +++ tests/x86/conv_006.irt | 22 +++ tests/x86/conv_007.irt | 18 +++ tests/x86/conv_008.irt | 22 +++ tests/x86/conv_009.irt | 22 +++ tests/x86/conv_010.irt | 17 +++ tests/x86/conv_011.irt | 17 +++ tests/x86/div_001.irt | 20 +++ tests/x86/div_002.irt | 21 +++ tests/x86/div_003.irt | 20 +++ tests/x86/div_004.irt | 20 +++ tests/x86/div_005.irt | 19 +++ tests/x86/div_006.irt | 20 +++ tests/x86/eq_001.irt | 20 +++ tests/x86/eq_002.irt | 19 +++ tests/x86/eq_003.irt | 19 +++ tests/x86/eq_004.irt | 26 ++++ tests/x86/eq_005.irt | 26 ++++ tests/x86/ge_001.irt | 20 +++ tests/x86/ge_002.irt | 19 +++ tests/x86/ge_003.irt | 19 +++ tests/x86/ge_004.irt | 24 ++++ tests/x86/ge_005.irt | 24 ++++ tests/x86/gt_001.irt | 20 +++ tests/x86/gt_002.irt | 19 +++ tests/x86/gt_003.irt | 19 +++ tests/x86/gt_004.irt | 24 ++++ tests/x86/gt_005.irt | 24 ++++ tests/x86/if_001.irt | 31 ++++ tests/x86/jcc_001.irt | 31 ++++ tests/x86/le_001.irt | 20 +++ tests/x86/le_002.irt | 19 +++ tests/x86/le_003.irt | 19 +++ tests/x86/le_004.irt | 20 +++ tests/x86/le_005.irt | 20 +++ tests/x86/lt_001.irt | 20 +++ tests/x86/lt_002.irt | 19 +++ tests/x86/lt_003.irt | 19 +++ tests/x86/lt_004.irt | 20 +++ tests/x86/lt_005.irt | 20 +++ tests/x86/min_001.irt | 23 +++ tests/x86/min_002.irt | 23 +++ tests/x86/min_003.irt | 23 +++ tests/x86/min_004.irt | 23 +++ tests/x86/min_005.irt | 22 +++ tests/x86/min_006.irt | 22 +++ tests/x86/min_007.irt | 21 +++ tests/x86/mod_001.irt | 21 +++ tests/x86/mod_002.irt | 22 +++ tests/x86/mod_003.irt | 21 +++ tests/x86/mod_004.irt | 21 +++ tests/x86/mod_005.irt | 19 +++ tests/x86/mul_001.irt | 19 +++ tests/x86/mul_002.irt | 20 +++ tests/x86/mul_003.irt | 19 +++ tests/x86/mul_004.irt | 20 +++ tests/x86/mul_005.irt | 19 +++ tests/x86/mul_006.irt | 19 +++ tests/x86/mul_007.irt | 19 +++ tests/x86/mul_ov_001.irt | 20 +++ tests/x86/mul_ov_002.irt | 22 +++ tests/x86/ne_001.irt | 20 +++ tests/x86/ne_002.irt | 19 +++ tests/x86/ne_003.irt | 19 +++ tests/x86/ne_004.irt | 26 ++++ tests/x86/ne_005.irt | 26 ++++ tests/x86/neg_001.irt | 18 +++ tests/x86/neg_002.irt | 26 ++++ tests/x86/neg_003.irt | 26 ++++ tests/x86/not_001.irt | 18 +++ tests/x86/not_002.irt | 19 +++ tests/x86/ra_001.irt | 22 +++ tests/x86/ra_002.irt | 23 +++ tests/x86/ra_003.irt | 24 ++++ tests/x86/ra_004.irt | 23 +++ tests/x86/ra_005.irt | 24 ++++ tests/x86/ra_006.irt | 25 ++++ tests/x86/ra_007.irt | 24 ++++ tests/x86/ra_008.irt | 25 ++++ tests/x86/ra_009.irt | 26 ++++ tests/x86/ra_010.irt | 23 +++ tests/x86/ra_011.irt | 24 ++++ tests/x86/ra_012.irt | 25 ++++ tests/x86/ra_013.irt | 32 +++++ tests/x86/ra_014.irt | 25 ++++ tests/x86/ra_015.irt | 25 ++++ tests/x86/setcc_001.irt | 22 +++ tests/x86/shl_001.irt | 20 +++ tests/x86/shl_002.irt | 19 +++ tests/x86/shl_003.irt | 20 +++ tests/x86/shl_004.irt | 20 +++ tests/x86/sub_001.irt | 19 +++ tests/x86/sub_002.irt | 19 +++ tests/x86/sub_003.irt | 19 +++ tests/x86/sub_004.irt | 19 +++ tests/x86/sub_005.irt | 23 +++ tests/x86/sub_006.irt | 23 +++ tests/x86/sub_007.irt | 23 +++ tests/x86/sub_008.irt | 23 +++ tests/x86/sub_009.irt | 19 +++ tests/x86/sub_010.irt | 19 +++ tests/x86/sub_011.irt | 27 ++++ tests/x86/sub_012.irt | 27 ++++ tests/x86/test_001.irt | 21 +++ tests/x86/uge_001.irt | 20 +++ tests/x86/uge_002.irt | 19 +++ tests/x86/uge_003.irt | 18 +++ tests/x86/ugt_001.irt | 20 +++ tests/x86/ugt_002.irt | 19 +++ tests/x86/ugt_003.irt | 19 +++ tests/x86/ule_001.irt | 20 +++ tests/x86/ule_002.irt | 19 +++ tests/x86/ule_003.irt | 19 +++ tests/x86/ult_001.irt | 20 +++ tests/x86/ult_002.irt | 19 +++ tests/x86/ult_003.irt | 18 +++ 394 files changed, 12858 insertions(+) create mode 100644 tests/aarch64/abs_001.irt create mode 100644 tests/aarch64/abs_002.irt create mode 100644 tests/aarch64/abs_003.irt create mode 100644 tests/aarch64/add_001.irt create mode 100644 tests/aarch64/add_002.irt create mode 100644 tests/aarch64/add_003.irt create mode 100644 tests/aarch64/add_004.irt create mode 100644 tests/aarch64/add_005.irt create mode 100644 tests/aarch64/add_006.irt create mode 100644 tests/aarch64/add_007.irt create mode 100644 tests/aarch64/add_008.irt create mode 100644 tests/aarch64/add_009.irt create mode 100644 tests/aarch64/add_010.irt create mode 100644 tests/aarch64/add_011.irt create mode 100644 tests/aarch64/add_012.irt create mode 100644 tests/aarch64/add_ov_001.irt create mode 100644 tests/aarch64/add_ov_002.irt create mode 100644 tests/aarch64/add_ov_003.irt create mode 100644 tests/aarch64/add_ov_004.irt create mode 100644 tests/aarch64/alloca_001.irt create mode 100644 tests/aarch64/alloca_002.irt create mode 100644 tests/aarch64/bswap_001.irt create mode 100644 tests/aarch64/conv_001.irt create mode 100644 tests/aarch64/conv_002.irt create mode 100644 tests/aarch64/conv_003.irt create mode 100644 tests/aarch64/conv_004.irt create mode 100644 tests/aarch64/conv_005.irt create mode 100644 tests/aarch64/conv_006.irt create mode 100644 tests/aarch64/conv_007.irt create mode 100644 tests/aarch64/conv_008.irt create mode 100644 tests/aarch64/conv_009.irt create mode 100644 tests/aarch64/conv_010.irt create mode 100644 tests/aarch64/conv_011.irt create mode 100644 tests/aarch64/div_001.irt create mode 100644 tests/aarch64/div_002.irt create mode 100644 tests/aarch64/div_003.irt create mode 100644 tests/aarch64/div_004.irt create mode 100644 tests/aarch64/div_005.irt create mode 100644 tests/aarch64/div_006.irt create mode 100644 tests/aarch64/eq_001.irt create mode 100644 tests/aarch64/eq_002.irt create mode 100644 tests/aarch64/eq_003.irt create mode 100644 tests/aarch64/eq_004.irt create mode 100644 tests/aarch64/eq_005.irt create mode 100644 tests/aarch64/ge_001.irt create mode 100644 tests/aarch64/ge_002.irt create mode 100644 tests/aarch64/ge_003.irt create mode 100644 tests/aarch64/ge_004.irt create mode 100644 tests/aarch64/ge_005.irt create mode 100644 tests/aarch64/gt_001.irt create mode 100644 tests/aarch64/gt_002.irt create mode 100644 tests/aarch64/gt_003.irt create mode 100644 tests/aarch64/gt_004.irt create mode 100644 tests/aarch64/gt_005.irt create mode 100644 tests/aarch64/if_001.irt create mode 100644 tests/aarch64/le_001.irt create mode 100644 tests/aarch64/le_002.irt create mode 100644 tests/aarch64/le_003.irt create mode 100644 tests/aarch64/le_004.irt create mode 100644 tests/aarch64/le_005.irt create mode 100644 tests/aarch64/lt_001.irt create mode 100644 tests/aarch64/lt_002.irt create mode 100644 tests/aarch64/lt_003.irt create mode 100644 tests/aarch64/lt_004.irt create mode 100644 tests/aarch64/lt_005.irt create mode 100644 tests/aarch64/min_001.irt create mode 100644 tests/aarch64/min_002.irt create mode 100644 tests/aarch64/min_003.irt create mode 100644 tests/aarch64/min_004.irt create mode 100644 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create mode 100644 tests/x86/sub_009.irt create mode 100644 tests/x86/sub_010.irt create mode 100644 tests/x86/sub_011.irt create mode 100644 tests/x86/sub_012.irt create mode 100644 tests/x86/test_001.irt create mode 100644 tests/x86/uge_001.irt create mode 100644 tests/x86/uge_002.irt create mode 100644 tests/x86/uge_003.irt create mode 100644 tests/x86/ugt_001.irt create mode 100644 tests/x86/ugt_002.irt create mode 100644 tests/x86/ugt_003.irt create mode 100644 tests/x86/ule_001.irt create mode 100644 tests/x86/ule_002.irt create mode 100644 tests/x86/ule_003.irt create mode 100644 tests/x86/ult_001.irt create mode 100644 tests/x86/ult_002.irt create mode 100644 tests/x86/ult_003.irt diff --git a/tests/aarch64/abs_001.irt b/tests/aarch64/abs_001.irt new file mode 100644 index 0000000..a5a0d0c --- /dev/null +++ b/tests/aarch64/abs_001.irt @@ -0,0 +1,18 @@ +--TEST-- +001: abs function +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + l_1 = START(l_4); + int32_t x = PARAM(l_1, "x", 1); + int32_t ret = ABS(x); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + cmp w0, #0 + cneg w0, w0, lt + ret diff --git a/tests/aarch64/abs_002.irt b/tests/aarch64/abs_002.irt new file mode 100644 index 0000000..45e5641 --- /dev/null +++ b/tests/aarch64/abs_002.irt @@ -0,0 +1,17 @@ +--TEST-- +002: abs function +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + l_1 = START(l_4); + double x = PARAM(l_1, "x", 1); + double ret = ABS(x); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + fabs d0, d0 + ret diff --git a/tests/aarch64/abs_003.irt b/tests/aarch64/abs_003.irt new file mode 100644 index 0000000..216c79d --- /dev/null +++ b/tests/aarch64/abs_003.irt @@ -0,0 +1,17 @@ +--TEST-- +003: abs function +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + l_1 = START(l_4); + float x = PARAM(l_1, "x", 1); + float ret = ABS(x); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + fabs s0, s0 + ret diff --git a/tests/aarch64/add_001.irt b/tests/aarch64/add_001.irt new file mode 100644 index 0000000..a9d881d --- /dev/null +++ b/tests/aarch64/add_001.irt @@ -0,0 +1,18 @@ +--TEST-- +001: add function +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + l_1 = START(l_4); + int32_t x = PARAM(l_1, "x", 1); + int32_t y = PARAM(l_1, "y", 2); + int32_t ret = ADD(x, y); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + add w0, w1, w0 + ret diff --git a/tests/aarch64/add_002.irt b/tests/aarch64/add_002.irt new file mode 100644 index 0000000..4b245a2 --- /dev/null +++ b/tests/aarch64/add_002.irt @@ -0,0 +1,18 @@ +--TEST-- +002: add function +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + int32_t c = 17; + l_1 = START(l_4); + int32_t x = PARAM(l_1, "x", 1); + int32_t ret = ADD(x, c); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + add w0, w0, #0x11 + ret diff --git a/tests/aarch64/add_003.irt b/tests/aarch64/add_003.irt new file mode 100644 index 0000000..451d38a --- /dev/null +++ b/tests/aarch64/add_003.irt @@ -0,0 +1,18 @@ +--TEST-- +003: add function +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + l_1 = START(l_4); + int32_t x = PARAM(l_1, "x", 1); + int32_t y = PARAM(l_1, "y", 2); + int32_t ret = ADD(y, x); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + add w0, w1, w0 + ret diff --git a/tests/aarch64/add_004.irt b/tests/aarch64/add_004.irt new file mode 100644 index 0000000..98c5ae5 --- /dev/null +++ b/tests/aarch64/add_004.irt @@ -0,0 +1,18 @@ +--TEST-- +004: add function +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + int32_t c = 17; + l_1 = START(l_4); + int32_t x = PARAM(l_1, "x", 1); + int32_t ret = ADD(c, x); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + add w0, w0, #0x11 + ret diff --git a/tests/aarch64/add_005.irt b/tests/aarch64/add_005.irt new file mode 100644 index 0000000..08b37a4 --- /dev/null +++ b/tests/aarch64/add_005.irt @@ -0,0 +1,18 @@ +--TEST-- +005: add function +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + l_1 = START(l_4); + double x = PARAM(l_1, "x", 1); + double y = PARAM(l_1, "y", 2); + double ret = ADD(x, y); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + fadd d0, d1, d0 + ret diff --git a/tests/aarch64/add_006.irt b/tests/aarch64/add_006.irt new file mode 100644 index 0000000..cf80ac1 --- /dev/null +++ b/tests/aarch64/add_006.irt @@ -0,0 +1,18 @@ +--TEST-- +006: add function +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + l_1 = START(l_4); + double x = PARAM(l_1, "x", 1); + double y = PARAM(l_1, "y", 2); + double ret = ADD(y, x); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + fadd d0, d1, d0 + ret diff --git a/tests/aarch64/add_007.irt b/tests/aarch64/add_007.irt new file mode 100644 index 0000000..a4413df --- /dev/null +++ b/tests/aarch64/add_007.irt @@ -0,0 +1,18 @@ +--TEST-- +007: add function +--TARGET-- +aarch64 +--ARGS-- +-S -mavx +--CODE-- +{ + l_1 = START(l_4); + double x = PARAM(l_1, "x", 1); + double y = PARAM(l_1, "y", 2); + double ret = ADD(x, y); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + fadd d0, d1, d0 + ret diff --git a/tests/aarch64/add_008.irt b/tests/aarch64/add_008.irt new file mode 100644 index 0000000..a33b230 --- /dev/null +++ b/tests/aarch64/add_008.irt @@ -0,0 +1,18 @@ +--TEST-- +008: add function +--TARGET-- +aarch64 +--ARGS-- +-S -mavx +--CODE-- +{ + l_1 = START(l_4); + double x = PARAM(l_1, "x", 1); + double y = PARAM(l_1, "y", 2); + double ret = ADD(y, x); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + fadd d0, d1, d0 + ret diff --git a/tests/aarch64/add_009.irt b/tests/aarch64/add_009.irt new file mode 100644 index 0000000..e4a7f30 --- /dev/null +++ b/tests/aarch64/add_009.irt @@ -0,0 +1,19 @@ +--TEST-- +009: add function +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + uint64_t c = 0x100000000; + l_1 = START(l_4); + uint64_t x = PARAM(l_1, "x", 1); + uint64_t ret = ADD(x, c); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + movz x1, #0x1, lsl #32 + add x0, x0, x1 + ret diff --git a/tests/aarch64/add_010.irt b/tests/aarch64/add_010.irt new file mode 100644 index 0000000..a3a3d4e --- /dev/null +++ b/tests/aarch64/add_010.irt @@ -0,0 +1,18 @@ +--TEST-- +010: add function +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + uint16_t c = 1; + l_1 = START(l_4); + uint16_t x = PARAM(l_1, "x", 1); + uint16_t ret = ADD(x, c); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + add w0, w0, #1 + ret diff --git a/tests/aarch64/add_011.irt b/tests/aarch64/add_011.irt new file mode 100644 index 0000000..0f262d9 --- /dev/null +++ b/tests/aarch64/add_011.irt @@ -0,0 +1,23 @@ +--TEST-- +011: add function +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + double c = 0.5; + l_1 = START(l_4); + double x = PARAM(l_1, "x", 1); + double ret = ADD(x, c); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + ldr d1, .L1 + fadd d0, d0, d1 + ret +.rodata + .db 0x1f, 0x20, 0x03, 0xd5 +.L1: + .db 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x3f diff --git a/tests/aarch64/add_012.irt b/tests/aarch64/add_012.irt new file mode 100644 index 0000000..555aa21 --- /dev/null +++ b/tests/aarch64/add_012.irt @@ -0,0 +1,23 @@ +--TEST-- +012: add function +--TARGET-- +aarch64 +--ARGS-- +-S -mavx +--CODE-- +{ + double c = 0.5; + l_1 = START(l_4); + double x = PARAM(l_1, "x", 1); + double ret = ADD(x, c); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + ldr d1, .L1 + fadd d0, d0, d1 + ret +.rodata + .db 0x1f, 0x20, 0x03, 0xd5 +.L1: + .db 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x3f diff --git a/tests/aarch64/add_ov_001.irt b/tests/aarch64/add_ov_001.irt new file mode 100644 index 0000000..18cf84b --- /dev/null +++ b/tests/aarch64/add_ov_001.irt @@ -0,0 +1,20 @@ +--TEST-- +001: add_ov function +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + int32_t c = 2; + l_1 = START(l_2); + int32_t x = PARAM(l_1, "x", 1); + int32_t ret = ADD_OV(x, c); + bool ov = OVERFLOW(ret); + l_2 = RETURN(l_1, ov); +} +--EXPECT-- +test: + adds w0, w0, #2 + cset w0, vs + ret diff --git a/tests/aarch64/add_ov_002.irt b/tests/aarch64/add_ov_002.irt new file mode 100644 index 0000000..4df099d --- /dev/null +++ b/tests/aarch64/add_ov_002.irt @@ -0,0 +1,20 @@ +--TEST-- +002: add_ov function +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + uint32_t c = 2; + l_1 = START(l_2); + uint32_t x = PARAM(l_1, "x", 1); + uint32_t ret = ADD_OV(x, c); + bool ov = OVERFLOW(ret); + l_2 = RETURN(l_1, ov); +} +--EXPECT-- +test: + adds w0, w0, #2 + cset w0, hs + ret diff --git a/tests/aarch64/add_ov_003.irt b/tests/aarch64/add_ov_003.irt new file mode 100644 index 0000000..57a41d5 --- /dev/null +++ b/tests/aarch64/add_ov_003.irt @@ -0,0 +1,30 @@ +--TEST-- +003: add_ov function +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + int32_t c_1 = 0; + int32_t c = 2; + l_1 = START(l_8); + int32_t x = PARAM(l_1, "x", 1); + int32_t ret1 = ADD_OV(x, c); + bool ov = OVERFLOW(ret1); + l_2 = IF(l_1, ov); + l_3 = IF_TRUE(l_2); + l_4 = END(l_3); + l_5 = IF_FALSE(l_2); + l_6 = END(l_5); + l_7 = MERGE(l_4, l_6); + int32_t ret = PHI(l_7, c_1, ret1); + l_8 = RETURN(l_7, ret); +} +--EXPECT-- +test: + adds w0, w0, #2 + b.vc .L1 + mov w0, wzr +.L1: + ret diff --git a/tests/aarch64/add_ov_004.irt b/tests/aarch64/add_ov_004.irt new file mode 100644 index 0000000..ec521c0 --- /dev/null +++ b/tests/aarch64/add_ov_004.irt @@ -0,0 +1,32 @@ +--TEST-- +004: add_ov function (jmp probability) +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + int32_t c_1 = 0; + int32_t c = 2; + l_1 = START(l_8); + int32_t x = PARAM(l_1, "x", 1); + int32_t ret1 = ADD_OV(x, c); + bool ov = OVERFLOW(ret1); + l_2 = IF(l_1, ov); + l_3 = IF_TRUE(l_2, 1); + l_4 = END(l_3); + l_5 = IF_FALSE(l_2); + l_6 = END(l_5); + l_7 = MERGE(l_4, l_6); + int32_t ret = PHI(l_7, c_1, ret1); + l_8 = RETURN(l_7, ret); +} +--EXPECT-- +test: + adds w0, w0, #2 + b.vs .L2 +.L1: + ret +.L2: + mov w0, wzr + b .L1 diff --git a/tests/aarch64/alloca_001.irt b/tests/aarch64/alloca_001.irt new file mode 100644 index 0000000..226db19 --- /dev/null +++ b/tests/aarch64/alloca_001.irt @@ -0,0 +1,22 @@ +--TEST-- +001: alloca function +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + int32_t size = 10; + l_1 = START(l_4); + uintptr_t ret, l_2 = ALLOCA(l_1, size); + l_4 = RETURN(l_2, ret); +} +--EXPECT-- +test: + stp x29, x30, [sp, #-0x10]! + mov x29, sp + sub sp, sp, #0x10 + mov x0, sp + mov sp, x29 + ldp x29, x30, [sp], #0x10 + ret diff --git a/tests/aarch64/alloca_002.irt b/tests/aarch64/alloca_002.irt new file mode 100644 index 0000000..1f93666 --- /dev/null +++ b/tests/aarch64/alloca_002.irt @@ -0,0 +1,24 @@ +--TEST-- +002: alloca function +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + l_1 = START(l_4); + int32_t x = PARAM(l_1, "x", 1); + uintptr_t ret, l_2 = ALLOCA(l_1, x); + l_4 = RETURN(l_2, ret); +} +--EXPECT-- +test: + stp x29, x30, [sp, #-0x10]! + mov x29, sp + add x0, x0, #7 + and x0, x0, #0xfffffffffffffff8 + sub sp, sp, x0 + mov x0, sp + mov sp, x29 + ldp x29, x30, [sp], #0x10 + ret diff --git a/tests/aarch64/bswap_001.irt b/tests/aarch64/bswap_001.irt new file mode 100644 index 0000000..9898549 --- /dev/null +++ b/tests/aarch64/bswap_001.irt @@ -0,0 +1,17 @@ +--TEST-- +001: bswap function +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + l_1 = START(l_4); + int32_t x = PARAM(l_1, "x", 1); + int32_t ret = BSWAP(x); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + rev w0, w0 + ret diff --git a/tests/aarch64/conv_001.irt b/tests/aarch64/conv_001.irt new file mode 100644 index 0000000..7171931 --- /dev/null +++ b/tests/aarch64/conv_001.irt @@ -0,0 +1,17 @@ +--TEST-- +001: type conversion SEXT +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + l_1 = START(l_4); + int32_t x = PARAM(l_1, "x", 1); + int64_t ret = SEXT(x); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + sxtw x0, w0 + ret diff --git a/tests/aarch64/conv_002.irt b/tests/aarch64/conv_002.irt new file mode 100644 index 0000000..730c48d --- /dev/null +++ b/tests/aarch64/conv_002.irt @@ -0,0 +1,17 @@ +--TEST-- +002: type conversion ZEXT +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + l_1 = START(l_4); + uint32_t x = PARAM(l_1, "x", 1); + uint64_t ret = ZEXT(x); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + mov w0, w0 + ret diff --git a/tests/aarch64/conv_003.irt b/tests/aarch64/conv_003.irt new file mode 100644 index 0000000..ce8eb41 --- /dev/null +++ b/tests/aarch64/conv_003.irt @@ -0,0 +1,16 @@ +--TEST-- +003: type conversion BITCAST +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + l_1 = START(l_4); + int32_t x = PARAM(l_1, "x", 1); + uint32_t ret = BITCAST(x); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + ret diff --git a/tests/aarch64/conv_004.irt b/tests/aarch64/conv_004.irt new file mode 100644 index 0000000..410271a --- /dev/null +++ b/tests/aarch64/conv_004.irt @@ -0,0 +1,17 @@ +--TEST-- +004: type conversion BITCAST +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + l_1 = START(l_4); + double x = PARAM(l_1, "x", 1); + uint64_t ret = BITCAST(x); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + fmov x0, d0 + ret diff --git a/tests/aarch64/conv_005.irt b/tests/aarch64/conv_005.irt new file mode 100644 index 0000000..3947c26 --- /dev/null +++ b/tests/aarch64/conv_005.irt @@ -0,0 +1,17 @@ +--TEST-- +005: type conversion BITCAST +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + l_1 = START(l_4); + float x = PARAM(l_1, "x", 1); + uint32_t ret = BITCAST(x); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + fmov w0, s0 + ret diff --git a/tests/aarch64/conv_006.irt b/tests/aarch64/conv_006.irt new file mode 100644 index 0000000..0fe1a3f --- /dev/null +++ b/tests/aarch64/conv_006.irt @@ -0,0 +1,17 @@ +--TEST-- +006: type conversion INT2FP +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + l_1 = START(l_4); + int32_t x = PARAM(l_1, "x", 1); + double ret = INT2FP(x); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + scvtf d0, w0 + ret diff --git a/tests/aarch64/conv_007.irt b/tests/aarch64/conv_007.irt new file mode 100644 index 0000000..7ee305b --- /dev/null +++ b/tests/aarch64/conv_007.irt @@ -0,0 +1,17 @@ +--TEST-- +007: type conversion FP2INT +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + l_1 = START(l_4); + float x = PARAM(l_1, "x", 1); + uint32_t ret = FP2INT(x); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + fcvtzu w0, s0 + ret diff --git a/tests/aarch64/conv_008.irt b/tests/aarch64/conv_008.irt new file mode 100644 index 0000000..c2ab2b6 --- /dev/null +++ b/tests/aarch64/conv_008.irt @@ -0,0 +1,17 @@ +--TEST-- +008: type conversion FP2FP +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + l_1 = START(l_4); + float x = PARAM(l_1, "x", 1); + double ret = FP2FP(x); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + fcvt d0, s0 + ret diff --git a/tests/aarch64/conv_009.irt b/tests/aarch64/conv_009.irt new file mode 100644 index 0000000..480c4f4 --- /dev/null +++ b/tests/aarch64/conv_009.irt @@ -0,0 +1,17 @@ +--TEST-- +009: type conversion FP2FP +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + l_1 = START(l_4); + double x = PARAM(l_1, "x", 1); + float ret = FP2FP(x); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + fcvt s0, d0 + ret diff --git a/tests/aarch64/conv_010.irt b/tests/aarch64/conv_010.irt new file mode 100644 index 0000000..97486b8 --- /dev/null +++ b/tests/aarch64/conv_010.irt @@ -0,0 +1,17 @@ +--TEST-- +010: type conversion BITCAST +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + l_1 = START(l_4); + uint64_t x = PARAM(l_1, "x", 1); + double ret = BITCAST(x); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + fmov d0, x0 + ret diff --git a/tests/aarch64/conv_011.irt b/tests/aarch64/conv_011.irt new file mode 100644 index 0000000..1ae1397 --- /dev/null +++ b/tests/aarch64/conv_011.irt @@ -0,0 +1,16 @@ +--TEST-- +011: type conversion TRUNC +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + l_1 = START(l_4); + int32_t x = PARAM(l_1, "x", 1); + int8_t ret = TRUNC(x); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + ret diff --git a/tests/aarch64/div_001.irt b/tests/aarch64/div_001.irt new file mode 100644 index 0000000..c4c7174 --- /dev/null +++ b/tests/aarch64/div_001.irt @@ -0,0 +1,18 @@ +--TEST-- +001: div function +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + l_1 = START(l_4); + int32_t x = PARAM(l_1, "x", 1); + int32_t y = PARAM(l_1, "y", 2); + int32_t ret = DIV(x, y); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + sdiv w0, w0, w1 + ret diff --git a/tests/aarch64/div_002.irt b/tests/aarch64/div_002.irt new file mode 100644 index 0000000..506a73b --- /dev/null +++ b/tests/aarch64/div_002.irt @@ -0,0 +1,19 @@ +--TEST-- +002: div function +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + int32_t c = 17; + l_1 = START(l_4); + int32_t x = PARAM(l_1, "x", 1); + int32_t ret = DIV(x, c); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + movz w1, #0x11 + sdiv w0, w0, w1 + ret diff --git a/tests/aarch64/div_003.irt b/tests/aarch64/div_003.irt new file mode 100644 index 0000000..2259c0c --- /dev/null +++ b/tests/aarch64/div_003.irt @@ -0,0 +1,18 @@ +--TEST-- +003: div function +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + l_1 = START(l_4); + int32_t x = PARAM(l_1, "x", 1); + int32_t y = PARAM(l_1, "y", 2); + int32_t ret = DIV(y, x); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + sdiv w0, w1, w0 + ret diff --git a/tests/aarch64/div_004.irt b/tests/aarch64/div_004.irt new file mode 100644 index 0000000..ba19ad1 --- /dev/null +++ b/tests/aarch64/div_004.irt @@ -0,0 +1,19 @@ +--TEST-- +004: div function +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + int32_t c = 17; + l_1 = START(l_4); + int32_t x = PARAM(l_1, "x", 1); + int32_t ret = DIV(c, x); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + movz w1, #0x11 + sdiv w0, w1, w0 + ret diff --git a/tests/aarch64/div_005.irt b/tests/aarch64/div_005.irt new file mode 100644 index 0000000..cb2a813 --- /dev/null +++ b/tests/aarch64/div_005.irt @@ -0,0 +1,18 @@ +--TEST-- +005: div function +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + uint32_t c = 16; + l_1 = START(l_4); + uint32_t x = PARAM(l_1, "x", 1); + uint32_t ret = DIV(x, c); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + lsr w0, w0, #4 + ret diff --git a/tests/aarch64/div_006.irt b/tests/aarch64/div_006.irt new file mode 100644 index 0000000..0245643 --- /dev/null +++ b/tests/aarch64/div_006.irt @@ -0,0 +1,18 @@ +--TEST-- +006: div function +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + l_1 = START(l_4); + uint32_t x = PARAM(l_1, "x", 1); + uint32_t y = PARAM(l_1, "y", 2); + uint32_t ret = DIV(x, y); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + udiv w0, w0, w1 + ret diff --git a/tests/aarch64/eq_001.irt b/tests/aarch64/eq_001.irt new file mode 100644 index 0000000..2173ab4 --- /dev/null +++ b/tests/aarch64/eq_001.irt @@ -0,0 +1,19 @@ +--TEST-- +001: eq function +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + l_1 = START(l_4); + int32_t x = PARAM(l_1, "x", 1); + int32_t y = PARAM(l_1, "y", 2); + bool ret = EQ(x, y); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + cmp w1, w0 + cset w0, eq + ret diff --git a/tests/aarch64/eq_002.irt b/tests/aarch64/eq_002.irt new file mode 100644 index 0000000..65eb0c2 --- /dev/null +++ b/tests/aarch64/eq_002.irt @@ -0,0 +1,19 @@ +--TEST-- +002: eq function +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + int32_t c = 17; + l_1 = START(l_4); + int32_t x = PARAM(l_1, "x", 1); + bool ret = EQ(x, c); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + cmp w0, #0x11 + cset w0, eq + ret diff --git a/tests/aarch64/eq_003.irt b/tests/aarch64/eq_003.irt new file mode 100644 index 0000000..832c8c0 --- /dev/null +++ b/tests/aarch64/eq_003.irt @@ -0,0 +1,19 @@ +--TEST-- +003: eq function +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + int32_t c = 0; + l_1 = START(l_4); + int32_t x = PARAM(l_1, "x", 1); + bool ret = EQ(x, c); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + cmp w0, #0 + cset w0, eq + ret diff --git a/tests/aarch64/eq_004.irt b/tests/aarch64/eq_004.irt new file mode 100644 index 0000000..f5cc261 --- /dev/null +++ b/tests/aarch64/eq_004.irt @@ -0,0 +1,20 @@ +--TEST-- +004: eq function +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + double c = 0; + l_1 = START(l_4); + double x = PARAM(l_1, "x", 1); + bool ret = EQ(x, c); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + fmov d1, xzr + fcmp d0, d1 + cset w0, eq + ret diff --git a/tests/aarch64/eq_005.irt b/tests/aarch64/eq_005.irt new file mode 100644 index 0000000..8abc1bb --- /dev/null +++ b/tests/aarch64/eq_005.irt @@ -0,0 +1,20 @@ +--TEST-- +005: eq function +--TARGET-- +aarch64 +--ARGS-- +-S -mavx +--CODE-- +{ + double c = 0; + l_1 = START(l_4); + double x = PARAM(l_1, "x", 1); + bool ret = EQ(x, c); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + fmov d1, xzr + fcmp d0, d1 + cset w0, eq + ret diff --git a/tests/aarch64/ge_001.irt b/tests/aarch64/ge_001.irt new file mode 100644 index 0000000..383d58e --- /dev/null +++ b/tests/aarch64/ge_001.irt @@ -0,0 +1,19 @@ +--TEST-- +001: ge function +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + l_1 = START(l_4); + int32_t x = PARAM(l_1, "x", 1); + int32_t y = PARAM(l_1, "y", 2); + bool ret = GE(x, y); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + cmp w1, w0 + cset w0, le + ret diff --git a/tests/aarch64/ge_002.irt b/tests/aarch64/ge_002.irt new file mode 100644 index 0000000..3585c41 --- /dev/null +++ b/tests/aarch64/ge_002.irt @@ -0,0 +1,19 @@ +--TEST-- +002: ge function +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + int32_t c = 17; + l_1 = START(l_4); + int32_t x = PARAM(l_1, "x", 1); + bool ret = GE(x, c); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + cmp w0, #0x11 + cset w0, ge + ret diff --git a/tests/aarch64/ge_003.irt b/tests/aarch64/ge_003.irt new file mode 100644 index 0000000..4946e1b --- /dev/null +++ b/tests/aarch64/ge_003.irt @@ -0,0 +1,19 @@ +--TEST-- +003: ge function +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + int32_t c = 0; + l_1 = START(l_4); + int32_t x = PARAM(l_1, "x", 1); + bool ret = GE(x, c); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + cmp w0, #0 + cset w0, ge + ret diff --git a/tests/aarch64/ge_004.irt b/tests/aarch64/ge_004.irt new file mode 100644 index 0000000..7769c68 --- /dev/null +++ b/tests/aarch64/ge_004.irt @@ -0,0 +1,20 @@ +--TEST-- +004: ge function +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + double c = 0; + l_1 = START(l_4); + double x = PARAM(l_1, "x", 1); + bool ret = GE(x, c); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + fmov d1, xzr + fcmp d0, d1 + cset w0, ge + ret diff --git a/tests/aarch64/ge_005.irt b/tests/aarch64/ge_005.irt new file mode 100644 index 0000000..991afe4 --- /dev/null +++ b/tests/aarch64/ge_005.irt @@ -0,0 +1,20 @@ +--TEST-- +005: ge function +--TARGET-- +aarch64 +--ARGS-- +-S -mavx +--CODE-- +{ + double c = 0; + l_1 = START(l_4); + double x = PARAM(l_1, "x", 1); + bool ret = GE(x, c); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + fmov d1, xzr + fcmp d0, d1 + cset w0, ge + ret diff --git a/tests/aarch64/gt_001.irt b/tests/aarch64/gt_001.irt new file mode 100644 index 0000000..180c155 --- /dev/null +++ b/tests/aarch64/gt_001.irt @@ -0,0 +1,19 @@ +--TEST-- +001: gt function +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + l_1 = START(l_4); + int32_t x = PARAM(l_1, "x", 1); + int32_t y = PARAM(l_1, "y", 2); + bool ret = GT(x, y); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + cmp w1, w0 + cset w0, lt + ret diff --git a/tests/aarch64/gt_002.irt b/tests/aarch64/gt_002.irt new file mode 100644 index 0000000..59e6165 --- /dev/null +++ b/tests/aarch64/gt_002.irt @@ -0,0 +1,19 @@ +--TEST-- +002: gt function +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + int32_t c = 17; + l_1 = START(l_4); + int32_t x = PARAM(l_1, "x", 1); + bool ret = GT(x, c); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + cmp w0, #0x11 + cset w0, gt + ret diff --git a/tests/aarch64/gt_003.irt b/tests/aarch64/gt_003.irt new file mode 100644 index 0000000..fc8b9b5 --- /dev/null +++ b/tests/aarch64/gt_003.irt @@ -0,0 +1,19 @@ +--TEST-- +003: gt function +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + int32_t c = 0; + l_1 = START(l_4); + int32_t x = PARAM(l_1, "x", 1); + bool ret = GT(x, c); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + cmp w0, #0 + cset w0, gt + ret diff --git a/tests/aarch64/gt_004.irt b/tests/aarch64/gt_004.irt new file mode 100644 index 0000000..685a533 --- /dev/null +++ b/tests/aarch64/gt_004.irt @@ -0,0 +1,20 @@ +--TEST-- +004: gt function +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + double c = 0; + l_1 = START(l_4); + double x = PARAM(l_1, "x", 1); + bool ret = GT(x, c); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + fmov d1, xzr + fcmp d0, d1 + cset w0, gt + ret diff --git a/tests/aarch64/gt_005.irt b/tests/aarch64/gt_005.irt new file mode 100644 index 0000000..0658cef --- /dev/null +++ b/tests/aarch64/gt_005.irt @@ -0,0 +1,20 @@ +--TEST-- +005: gt function +--TARGET-- +aarch64 +--ARGS-- +-S -mavx +--CODE-- +{ + double c = 0; + l_1 = START(l_4); + double x = PARAM(l_1, "x", 1); + bool ret = GT(x, c); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + fmov d1, xzr + fcmp d0, d1 + cset w0, gt + ret diff --git a/tests/aarch64/if_001.irt b/tests/aarch64/if_001.irt new file mode 100644 index 0000000..b550e72 --- /dev/null +++ b/tests/aarch64/if_001.irt @@ -0,0 +1,31 @@ +--TEST-- +001: if function +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + int32_t c_1 = 0; + int32_t c_2 = 42; + l_1 = START(l_8); + int32_t x = PARAM(l_1, "x", 1); + l_2 = IF(l_1, x); + l_3 = IF_TRUE(l_2); + l_4 = END(l_3); + l_5 = IF_FALSE(l_2); + l_6 = END(l_5); + l_7 = MERGE(l_4, l_6); + int32_t ret = PHI(l_7, c_1, c_2); + l_8 = RETURN(l_7, ret); +} +--EXPECT-- +test: + cmp w0, #0 + b.eq .L2 + mov w0, wzr +.L1: + ret +.L2: + movz w0, #0x2a + b .L1 diff --git a/tests/aarch64/le_001.irt b/tests/aarch64/le_001.irt new file mode 100644 index 0000000..5f3391b --- /dev/null +++ b/tests/aarch64/le_001.irt @@ -0,0 +1,19 @@ +--TEST-- +001: le function +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + l_1 = START(l_4); + int32_t x = PARAM(l_1, "x", 1); + int32_t y = PARAM(l_1, "y", 2); + bool ret = LE(x, y); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + cmp w1, w0 + cset w0, ge + ret diff --git a/tests/aarch64/le_002.irt b/tests/aarch64/le_002.irt new file mode 100644 index 0000000..67cfd4d --- /dev/null +++ b/tests/aarch64/le_002.irt @@ -0,0 +1,19 @@ +--TEST-- +002: le function +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + int32_t c = 17; + l_1 = START(l_4); + int32_t x = PARAM(l_1, "x", 1); + bool ret = LE(x, c); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + cmp w0, #0x11 + cset w0, le + ret diff --git a/tests/aarch64/le_003.irt b/tests/aarch64/le_003.irt new file mode 100644 index 0000000..cd31ca9 --- /dev/null +++ b/tests/aarch64/le_003.irt @@ -0,0 +1,19 @@ +--TEST-- +003: le function +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + int32_t c = 0; + l_1 = START(l_4); + int32_t x = PARAM(l_1, "x", 1); + bool ret = LE(x, c); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + cmp w0, #0 + cset w0, le + ret diff --git a/tests/aarch64/le_004.irt b/tests/aarch64/le_004.irt new file mode 100644 index 0000000..b1c2f82 --- /dev/null +++ b/tests/aarch64/le_004.irt @@ -0,0 +1,20 @@ +--TEST-- +004: le function +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + double c = 0; + l_1 = START(l_4); + double x = PARAM(l_1, "x", 1); + bool ret = LE(x, c); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + fmov d1, xzr + fcmp d1, d0 + cset w0, ge + ret diff --git a/tests/aarch64/le_005.irt b/tests/aarch64/le_005.irt new file mode 100644 index 0000000..bd99dbd --- /dev/null +++ b/tests/aarch64/le_005.irt @@ -0,0 +1,20 @@ +--TEST-- +005: le function +--TARGET-- +aarch64 +--ARGS-- +-S -mavx +--CODE-- +{ + double c = 0; + l_1 = START(l_4); + double x = PARAM(l_1, "x", 1); + bool ret = LE(x, c); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + fmov d1, xzr + fcmp d1, d0 + cset w0, ge + ret diff --git a/tests/aarch64/lt_001.irt b/tests/aarch64/lt_001.irt new file mode 100644 index 0000000..f022fba --- /dev/null +++ b/tests/aarch64/lt_001.irt @@ -0,0 +1,19 @@ +--TEST-- +001: lt function +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + l_1 = START(l_4); + int32_t x = PARAM(l_1, "x", 1); + int32_t y = PARAM(l_1, "y", 2); + bool ret = LT(x, y); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + cmp w1, w0 + cset w0, gt + ret diff --git a/tests/aarch64/lt_002.irt b/tests/aarch64/lt_002.irt new file mode 100644 index 0000000..19b3d4e --- /dev/null +++ b/tests/aarch64/lt_002.irt @@ -0,0 +1,19 @@ +--TEST-- +002: lt function +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + int32_t c = 17; + l_1 = START(l_4); + int32_t x = PARAM(l_1, "x", 1); + bool ret = LT(x, c); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + cmp w0, #0x11 + cset w0, lt + ret diff --git a/tests/aarch64/lt_003.irt b/tests/aarch64/lt_003.irt new file mode 100644 index 0000000..0a2e5be --- /dev/null +++ b/tests/aarch64/lt_003.irt @@ -0,0 +1,19 @@ +--TEST-- +003: lt function +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + int32_t c = 0; + l_1 = START(l_4); + int32_t x = PARAM(l_1, "x", 1); + bool ret = LT(x, c); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + cmp w0, #0 + cset w0, lt + ret diff --git a/tests/aarch64/lt_004.irt b/tests/aarch64/lt_004.irt new file mode 100644 index 0000000..1428ce0 --- /dev/null +++ b/tests/aarch64/lt_004.irt @@ -0,0 +1,20 @@ +--TEST-- +004: lt function +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + double c = 0; + l_1 = START(l_4); + double x = PARAM(l_1, "x", 1); + bool ret = LT(x, c); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + fmov d1, xzr + fcmp d1, d0 + cset w0, gt + ret diff --git a/tests/aarch64/lt_005.irt b/tests/aarch64/lt_005.irt new file mode 100644 index 0000000..f3b3f5c --- /dev/null +++ b/tests/aarch64/lt_005.irt @@ -0,0 +1,20 @@ +--TEST-- +005: lt function +--TARGET-- +aarch64 +--ARGS-- +-S -mavx +--CODE-- +{ + double c = 0; + l_1 = START(l_4); + double x = PARAM(l_1, "x", 1); + bool ret = LT(x, c); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + fmov d1, xzr + fcmp d1, d0 + cset w0, gt + ret diff --git a/tests/aarch64/min_001.irt b/tests/aarch64/min_001.irt new file mode 100644 index 0000000..40e6b12 --- /dev/null +++ b/tests/aarch64/min_001.irt @@ -0,0 +1,18 @@ +--TEST-- +001: min function +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + l_1 = START(l_4); + float x = PARAM(l_1, "x", 1); + float y = PARAM(l_1, "y", 2); + float ret = MIN(x, y); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + fmin s0, s1, s0 + ret diff --git a/tests/aarch64/min_002.irt b/tests/aarch64/min_002.irt new file mode 100644 index 0000000..99f51cd --- /dev/null +++ b/tests/aarch64/min_002.irt @@ -0,0 +1,18 @@ +--TEST-- +002: min function +--TARGET-- +aarch64 +--ARGS-- +-S -mavx +--CODE-- +{ + l_1 = START(l_4); + float x = PARAM(l_1, "x", 1); + float y = PARAM(l_1, "y", 2); + float ret = MIN(x, y); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + fmin s0, s1, s0 + ret diff --git a/tests/aarch64/min_003.irt b/tests/aarch64/min_003.irt new file mode 100644 index 0000000..46392d7 --- /dev/null +++ b/tests/aarch64/min_003.irt @@ -0,0 +1,18 @@ +--TEST-- +003: min function +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + l_1 = START(l_4); + double x = PARAM(l_1, "x", 1); + double y = PARAM(l_1, "y", 2); + double ret = MIN(x, y); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + fmin d0, d1, d0 + ret diff --git a/tests/aarch64/min_004.irt b/tests/aarch64/min_004.irt new file mode 100644 index 0000000..8bdb6e2 --- /dev/null +++ b/tests/aarch64/min_004.irt @@ -0,0 +1,18 @@ +--TEST-- +004: min function +--TARGET-- +aarch64 +--ARGS-- +-S -mavx +--CODE-- +{ + l_1 = START(l_4); + double x = PARAM(l_1, "x", 1); + double y = PARAM(l_1, "y", 2); + double ret = MIN(x, y); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + fmin d0, d1, d0 + ret diff --git a/tests/aarch64/min_005.irt b/tests/aarch64/min_005.irt new file mode 100644 index 0000000..ed13d85 --- /dev/null +++ b/tests/aarch64/min_005.irt @@ -0,0 +1,19 @@ +--TEST-- +005: min function +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + l_1 = START(l_4); + int32_t x = PARAM(l_1, "x", 1); + int32_t y = PARAM(l_1, "y", 2); + int32_t ret = MIN(x, y); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + cmp w1, w0 + csel w0, w1, w0, le + ret diff --git a/tests/aarch64/min_006.irt b/tests/aarch64/min_006.irt new file mode 100644 index 0000000..3246dc8 --- /dev/null +++ b/tests/aarch64/min_006.irt @@ -0,0 +1,19 @@ +--TEST-- +006: min function +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + l_1 = START(l_4); + uint8_t x = PARAM(l_1, "x", 1); + uint8_t y = PARAM(l_1, "y", 2); + uint8_t ret = MIN(x, y); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + cmp w1, w0 + csel w0, w1, w0, ls + ret diff --git a/tests/aarch64/min_007.irt b/tests/aarch64/min_007.irt new file mode 100644 index 0000000..1e15cd5 --- /dev/null +++ b/tests/aarch64/min_007.irt @@ -0,0 +1,20 @@ +--TEST-- +007: min function +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + int32_t c = 47; + l_1 = START(l_4); + int32_t x = PARAM(l_1, "x", 1); + int32_t ret = MIN(x, c); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + movz w1, #0x2f + cmp w0, w1 + csel w0, w0, w1, le + ret diff --git a/tests/aarch64/mod_001.irt b/tests/aarch64/mod_001.irt new file mode 100644 index 0000000..52b6220 --- /dev/null +++ b/tests/aarch64/mod_001.irt @@ -0,0 +1,19 @@ +--TEST-- +001: mod function +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + l_1 = START(l_4); + int32_t x = PARAM(l_1, "x", 1); + int32_t y = PARAM(l_1, "y", 2); + int32_t ret = MOD(x, y); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + sdiv w2, w0, w1 + msub w0, w2, w1, w0 + ret diff --git a/tests/aarch64/mod_002.irt b/tests/aarch64/mod_002.irt new file mode 100644 index 0000000..4598d67 --- /dev/null +++ b/tests/aarch64/mod_002.irt @@ -0,0 +1,20 @@ +--TEST-- +002: mod function +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + int32_t c = 17; + l_1 = START(l_4); + int32_t x = PARAM(l_1, "x", 1); + int32_t ret = MOD(x, c); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + movz w2, #0x11 + sdiv w1, w0, w2 + msub w0, w1, w2, w0 + ret diff --git a/tests/aarch64/mod_003.irt b/tests/aarch64/mod_003.irt new file mode 100644 index 0000000..aee8b46 --- /dev/null +++ b/tests/aarch64/mod_003.irt @@ -0,0 +1,19 @@ +--TEST-- +003: mod function +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + l_1 = START(l_4); + int32_t x = PARAM(l_1, "x", 1); + int32_t y = PARAM(l_1, "y", 2); + int32_t ret = MOD(y, x); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + sdiv w2, w1, w0 + msub w0, w2, w0, w1 + ret diff --git a/tests/aarch64/mod_004.irt b/tests/aarch64/mod_004.irt new file mode 100644 index 0000000..c799b76 --- /dev/null +++ b/tests/aarch64/mod_004.irt @@ -0,0 +1,20 @@ +--TEST-- +004: mod function +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + int32_t c = 17; + l_1 = START(l_4); + int32_t x = PARAM(l_1, "x", 1); + int32_t ret = MOD(c, x); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + movz w2, #0x11 + sdiv w1, w2, w0 + msub w0, w1, w0, w2 + ret diff --git a/tests/aarch64/mod_005.irt b/tests/aarch64/mod_005.irt new file mode 100644 index 0000000..2d68896 --- /dev/null +++ b/tests/aarch64/mod_005.irt @@ -0,0 +1,18 @@ +--TEST-- +005: mod function +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + uint32_t c = 16; + l_1 = START(l_4); + uint32_t x = PARAM(l_1, "x", 1); + uint32_t ret = MOD(x, c); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + and w0, w0, #0xf + ret diff --git a/tests/aarch64/mul_001.irt b/tests/aarch64/mul_001.irt new file mode 100644 index 0000000..a6f80d7 --- /dev/null +++ b/tests/aarch64/mul_001.irt @@ -0,0 +1,18 @@ +--TEST-- +001: mul function +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + l_1 = START(l_4); + uint32_t x = PARAM(l_1, "x", 1); + uint32_t y = PARAM(l_1, "y", 2); + uint32_t ret = MUL(x, y); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + mul w0, w1, w0 + ret diff --git a/tests/aarch64/mul_002.irt b/tests/aarch64/mul_002.irt new file mode 100644 index 0000000..972e9cb --- /dev/null +++ b/tests/aarch64/mul_002.irt @@ -0,0 +1,19 @@ +--TEST-- +002: mul function +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + uint32_t c = 17; + l_1 = START(l_4); + uint32_t x = PARAM(l_1, "x", 1); + uint32_t ret = MUL(x, c); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + movz w1, #0x11 + mul w0, w0, w1 + ret diff --git a/tests/aarch64/mul_003.irt b/tests/aarch64/mul_003.irt new file mode 100644 index 0000000..6289947 --- /dev/null +++ b/tests/aarch64/mul_003.irt @@ -0,0 +1,18 @@ +--TEST-- +003: mul function +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + l_1 = START(l_4); + uint32_t x = PARAM(l_1, "x", 1); + uint32_t y = PARAM(l_1, "y", 2); + uint32_t ret = MUL(y, x); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + mul w0, w1, w0 + ret diff --git a/tests/aarch64/mul_004.irt b/tests/aarch64/mul_004.irt new file mode 100644 index 0000000..81eeae5 --- /dev/null +++ b/tests/aarch64/mul_004.irt @@ -0,0 +1,19 @@ +--TEST-- +004: mul function +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + uint32_t c = 17; + l_1 = START(l_4); + uint32_t x = PARAM(l_1, "x", 1); + uint32_t ret = MUL(c, x); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + movz w1, #0x11 + mul w0, w0, w1 + ret diff --git a/tests/aarch64/mul_005.irt b/tests/aarch64/mul_005.irt new file mode 100644 index 0000000..28de3e2 --- /dev/null +++ b/tests/aarch64/mul_005.irt @@ -0,0 +1,18 @@ +--TEST-- +005: mul function +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + uint32_t c = 2; + l_1 = START(l_4); + uint16_t x = PARAM(l_1, "x", 1); + uint16_t ret = MUL(c, x); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + add w0, w0, w0 + ret diff --git a/tests/aarch64/mul_006.irt b/tests/aarch64/mul_006.irt new file mode 100644 index 0000000..a85c038 --- /dev/null +++ b/tests/aarch64/mul_006.irt @@ -0,0 +1,18 @@ +--TEST-- +006: mul function +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + uint32_t c = 16; + l_1 = START(l_4); + uint16_t x = PARAM(l_1, "x", 1); + uint16_t ret = MUL(c, x); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + lsl w0, w0, #4 + ret diff --git a/tests/aarch64/mul_007.irt b/tests/aarch64/mul_007.irt new file mode 100644 index 0000000..18f24b4 --- /dev/null +++ b/tests/aarch64/mul_007.irt @@ -0,0 +1,18 @@ +--TEST-- +007: mul function +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + l_1 = START(l_4); + int32_t x = PARAM(l_1, "x", 1); + int32_t y = PARAM(l_1, "y", 2); + int32_t ret = MUL(x, y); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + mul w0, w1, w0 + ret diff --git a/tests/aarch64/mul_ov_001.irt b/tests/aarch64/mul_ov_001.irt new file mode 100644 index 0000000..b1241bf --- /dev/null +++ b/tests/aarch64/mul_ov_001.irt @@ -0,0 +1,23 @@ +--TEST-- +001: mul_ov function +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + int32_t c = 2; + l_1 = START(l_2); + int32_t x = PARAM(l_1, "x", 1); + int32_t ret = MUL_OV(x, c); + bool ov = OVERFLOW(ret); + l_2 = RETURN(l_1, ov); +} +--EXPECT-- +test: + movz w2, #0x2 + smull x0, w0, w2 + asr x1, x0, #0x20 + cmp x1, x0, asr #31 + cset w0, ne + ret diff --git a/tests/aarch64/mul_ov_002.irt b/tests/aarch64/mul_ov_002.irt new file mode 100644 index 0000000..eb0f9d3 --- /dev/null +++ b/tests/aarch64/mul_ov_002.irt @@ -0,0 +1,22 @@ +--TEST-- +002: mul_ov function +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + uint32_t c = 2; + l_1 = START(l_2); + uint32_t x = PARAM(l_1, "x", 1); + uint32_t ret = MUL_OV(x, c); + bool ov = OVERFLOW(ret); + l_2 = RETURN(l_1, ov); +} +--EXPECT-- +test: + movz w1, #0x2 + umull x0, w0, w1 + cmp xzr, x0, lsr #32 + cset w0, ne + ret diff --git a/tests/aarch64/ne_001.irt b/tests/aarch64/ne_001.irt new file mode 100644 index 0000000..1e7c9ac --- /dev/null +++ b/tests/aarch64/ne_001.irt @@ -0,0 +1,19 @@ +--TEST-- +001: ne function +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + l_1 = START(l_4); + int32_t x = PARAM(l_1, "x", 1); + int32_t y = PARAM(l_1, "y", 2); + bool ret = NE(x, y); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + cmp w1, w0 + cset w0, ne + ret diff --git a/tests/aarch64/ne_002.irt b/tests/aarch64/ne_002.irt new file mode 100644 index 0000000..358b3f3 --- /dev/null +++ b/tests/aarch64/ne_002.irt @@ -0,0 +1,19 @@ +--TEST-- +002: ne function +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + int32_t c = 17; + l_1 = START(l_4); + int32_t x = PARAM(l_1, "x", 1); + bool ret = NE(x, c); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + cmp w0, #0x11 + cset w0, ne + ret diff --git a/tests/aarch64/ne_003.irt b/tests/aarch64/ne_003.irt new file mode 100644 index 0000000..4ad80a3 --- /dev/null +++ b/tests/aarch64/ne_003.irt @@ -0,0 +1,19 @@ +--TEST-- +003: ne function +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + int32_t c = 0; + l_1 = START(l_4); + int32_t x = PARAM(l_1, "x", 1); + bool ret = NE(x, c); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + cmp w0, #0 + cset w0, ne + ret diff --git a/tests/aarch64/ne_004.irt b/tests/aarch64/ne_004.irt new file mode 100644 index 0000000..a4137fe --- /dev/null +++ b/tests/aarch64/ne_004.irt @@ -0,0 +1,20 @@ +--TEST-- +004: ne function +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + double c = 0; + l_1 = START(l_4); + double x = PARAM(l_1, "x", 1); + bool ret = NE(x, c); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + fmov d1, xzr + fcmp d0, d1 + cset w0, ne + ret diff --git a/tests/aarch64/ne_005.irt b/tests/aarch64/ne_005.irt new file mode 100644 index 0000000..a58f711 --- /dev/null +++ b/tests/aarch64/ne_005.irt @@ -0,0 +1,20 @@ +--TEST-- +005: ne function +--TARGET-- +aarch64 +--ARGS-- +-S -mavx +--CODE-- +{ + double c = 0; + l_1 = START(l_4); + double x = PARAM(l_1, "x", 1); + bool ret = NE(x, c); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + fmov d1, xzr + fcmp d0, d1 + cset w0, ne + ret diff --git a/tests/aarch64/neg_001.irt b/tests/aarch64/neg_001.irt new file mode 100644 index 0000000..f5d2b13 --- /dev/null +++ b/tests/aarch64/neg_001.irt @@ -0,0 +1,17 @@ +--TEST-- +001: neg function +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + l_1 = START(l_4); + int32_t x = PARAM(l_1, "x", 1); + int32_t ret = NEG(x); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + neg w0, w0 + ret diff --git a/tests/aarch64/neg_002.irt b/tests/aarch64/neg_002.irt new file mode 100644 index 0000000..3c1732a --- /dev/null +++ b/tests/aarch64/neg_002.irt @@ -0,0 +1,17 @@ +--TEST-- +002: neg function +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + l_1 = START(l_4); + double x = PARAM(l_1, "x", 1); + double ret = NEG(x); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + fneg d0, d0 + ret diff --git a/tests/aarch64/neg_003.irt b/tests/aarch64/neg_003.irt new file mode 100644 index 0000000..2fde097 --- /dev/null +++ b/tests/aarch64/neg_003.irt @@ -0,0 +1,17 @@ +--TEST-- +003: neg function +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + l_1 = START(l_4); + float x = PARAM(l_1, "x", 1); + float ret = NEG(x); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + fneg s0, s0 + ret diff --git a/tests/aarch64/not_001.irt b/tests/aarch64/not_001.irt new file mode 100644 index 0000000..2e4d209 --- /dev/null +++ b/tests/aarch64/not_001.irt @@ -0,0 +1,17 @@ +--TEST-- +001: not function +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + l_1 = START(l_4); + int32_t x = PARAM(l_1, "x", 1); + int32_t ret = NOT(x); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + mvn w0, w0 + ret diff --git a/tests/aarch64/not_002.irt b/tests/aarch64/not_002.irt new file mode 100644 index 0000000..40a04d6 --- /dev/null +++ b/tests/aarch64/not_002.irt @@ -0,0 +1,18 @@ +--TEST-- +002: not function +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + l_1 = START(l_4); + bool x = PARAM(l_1, "x", 1); + bool ret = NOT(x); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + cmp w2, #0 + cset w0, eq + ret diff --git a/tests/aarch64/ra_001.irt b/tests/aarch64/ra_001.irt new file mode 100644 index 0000000..4e7884b --- /dev/null +++ b/tests/aarch64/ra_001.irt @@ -0,0 +1,21 @@ +--TEST-- +001: Register Allocation (MUL + MUL) +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + l_1 = START(l_4); + uint32_t x_1 = PARAM(l_1, "x", 1); + uint32_t y_1 = PARAM(l_1, "y", 2); + uint32_t z_1 = PARAM(l_1, "z", 3); + uint32_t x_2 = MUL(x_1, y_1); + uint32_t x_3 = MUL(x_2, z_1); + l_4 = RETURN(l_1, x_3); +} +--EXPECT-- +test: + mul w0, w1, w0 + mul w0, w0, w2 + ret diff --git a/tests/aarch64/ra_002.irt b/tests/aarch64/ra_002.irt new file mode 100644 index 0000000..f009fa3 --- /dev/null +++ b/tests/aarch64/ra_002.irt @@ -0,0 +1,21 @@ +--TEST-- +002: Register Allocation (MUL + DIV) +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + l_1 = START(l_4); + uint32_t x_1 = PARAM(l_1, "x", 1); + uint32_t y_1 = PARAM(l_1, "y", 2); + uint32_t z_1 = PARAM(l_1, "z", 3); + uint32_t x_2 = MUL(x_1, y_1); + uint32_t x_3 = DIV(x_2, z_1); + l_4 = RETURN(l_1, x_3); +} +--EXPECT-- +test: + mul w0, w1, w0 + udiv w0, w0, w2 + ret diff --git a/tests/aarch64/ra_003.irt b/tests/aarch64/ra_003.irt new file mode 100644 index 0000000..07e3378 --- /dev/null +++ b/tests/aarch64/ra_003.irt @@ -0,0 +1,22 @@ +--TEST-- +003: Register Allocation (MUL + MOD) +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + l_1 = START(l_4); + uint32_t x_1 = PARAM(l_1, "x", 1); + uint32_t y_1 = PARAM(l_1, "y", 2); + uint32_t z_1 = PARAM(l_1, "z", 3); + uint32_t x_2 = MUL(x_1, y_1); + uint32_t x_3 = MOD(x_2, z_1); + l_4 = RETURN(l_1, x_3); +} +--EXPECT-- +test: + mul w0, w1, w0 + udiv w1, w0, w2 + msub w0, w1, w2, w0 + ret diff --git a/tests/aarch64/ra_004.irt b/tests/aarch64/ra_004.irt new file mode 100644 index 0000000..bca46b0 --- /dev/null +++ b/tests/aarch64/ra_004.irt @@ -0,0 +1,21 @@ +--TEST-- +004: Register Allocation (DIV + MUL) +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + l_1 = START(l_4); + uint32_t x_1 = PARAM(l_1, "x", 1); + uint32_t y_1 = PARAM(l_1, "y", 2); + uint32_t z_1 = PARAM(l_1, "z", 3); + uint32_t x_2 = DIV(x_1, y_1); + uint32_t x_3 = MUL(x_2, z_1); + l_4 = RETURN(l_1, x_3); +} +--EXPECT-- +test: + udiv w0, w0, w1 + mul w0, w0, w2 + ret diff --git a/tests/aarch64/ra_005.irt b/tests/aarch64/ra_005.irt new file mode 100644 index 0000000..ae5c637 --- /dev/null +++ b/tests/aarch64/ra_005.irt @@ -0,0 +1,21 @@ +--TEST-- +005: Register Allocation (DIV + DIV) +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + l_1 = START(l_4); + uint32_t x_1 = PARAM(l_1, "x", 1); + uint32_t y_1 = PARAM(l_1, "y", 2); + uint32_t z_1 = PARAM(l_1, "z", 3); + uint32_t x_2 = DIV(x_1, y_1); + uint32_t x_3 = DIV(x_2, z_1); + l_4 = RETURN(l_1, x_3); +} +--EXPECT-- +test: + udiv w0, w0, w1 + udiv w0, w0, w2 + ret diff --git a/tests/aarch64/ra_006.irt b/tests/aarch64/ra_006.irt new file mode 100644 index 0000000..5658068 --- /dev/null +++ b/tests/aarch64/ra_006.irt @@ -0,0 +1,22 @@ +--TEST-- +006: Register Allocation (DIV + MOD) +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + l_1 = START(l_4); + uint32_t x_1 = PARAM(l_1, "x", 1); + uint32_t y_1 = PARAM(l_1, "y", 2); + uint32_t z_1 = PARAM(l_1, "z", 3); + uint32_t x_2 = DIV(x_1, y_1); + uint32_t x_3 = MOD(x_2, z_1); + l_4 = RETURN(l_1, x_3); +} +--EXPECT-- +test: + udiv w0, w0, w1 + udiv w1, w0, w2 + msub w0, w1, w2, w0 + ret diff --git a/tests/aarch64/ra_007.irt b/tests/aarch64/ra_007.irt new file mode 100644 index 0000000..1dc6cda --- /dev/null +++ b/tests/aarch64/ra_007.irt @@ -0,0 +1,22 @@ +--TEST-- +007: Register Allocation (MOD + MUL) +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + l_1 = START(l_4); + uint32_t x_1 = PARAM(l_1, "x", 1); + uint32_t y_1 = PARAM(l_1, "y", 2); + uint32_t z_1 = PARAM(l_1, "z", 3); + uint32_t x_2 = MOD(x_1, y_1); + uint32_t x_3 = MUL(x_2, z_1); + l_4 = RETURN(l_1, x_3); +} +--EXPECT-- +test: + udiv w3, w0, w1 + msub w0, w3, w1, w0 + mul w0, w0, w2 + ret diff --git a/tests/aarch64/ra_008.irt b/tests/aarch64/ra_008.irt new file mode 100644 index 0000000..10d6d67 --- /dev/null +++ b/tests/aarch64/ra_008.irt @@ -0,0 +1,22 @@ +--TEST-- +008: Register Allocation (MOD + DIV) +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + l_1 = START(l_4); + uint32_t x_1 = PARAM(l_1, "x", 1); + uint32_t y_1 = PARAM(l_1, "y", 2); + uint32_t z_1 = PARAM(l_1, "z", 3); + uint32_t x_2 = MOD(x_1, y_1); + uint32_t x_3 = DIV(x_2, z_1); + l_4 = RETURN(l_1, x_3); +} +--EXPECT-- +test: + udiv w3, w0, w1 + msub w0, w3, w1, w0 + udiv w0, w0, w2 + ret diff --git a/tests/aarch64/ra_009.irt b/tests/aarch64/ra_009.irt new file mode 100644 index 0000000..19a36a7 --- /dev/null +++ b/tests/aarch64/ra_009.irt @@ -0,0 +1,23 @@ +--TEST-- +009: Register Allocation (MOD + MOD) +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + l_1 = START(l_4); + uint32_t x_1 = PARAM(l_1, "x", 1); + uint32_t y_1 = PARAM(l_1, "y", 2); + uint32_t z_1 = PARAM(l_1, "z", 3); + uint32_t x_2 = MOD(x_1, y_1); + uint32_t x_3 = MOD(x_2, z_1); + l_4 = RETURN(l_1, x_3); +} +--EXPECT-- +test: + udiv w3, w0, w1 + msub w0, w3, w1, w0 + udiv w1, w0, w2 + msub w0, w1, w2, w0 + ret diff --git a/tests/aarch64/ra_010.irt b/tests/aarch64/ra_010.irt new file mode 100644 index 0000000..b6bf822 --- /dev/null +++ b/tests/aarch64/ra_010.irt @@ -0,0 +1,21 @@ +--TEST-- +010: Register Allocation (ADD + MUL) +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + l_1 = START(l_4); + uint32_t x_1 = PARAM(l_1, "x", 1); + uint32_t y_1 = PARAM(l_1, "y", 2); + uint32_t z_1 = PARAM(l_1, "z", 3); + uint32_t x_2 = ADD(x_1, y_1); + uint32_t x_3 = MUL(x_2, z_1); + l_4 = RETURN(l_1, x_3); +} +--EXPECT-- +test: + add w0, w1, w0 + mul w0, w0, w2 + ret diff --git a/tests/aarch64/ra_011.irt b/tests/aarch64/ra_011.irt new file mode 100644 index 0000000..5ca8c6f --- /dev/null +++ b/tests/aarch64/ra_011.irt @@ -0,0 +1,21 @@ +--TEST-- +011: Register Allocation (ADD + DIV) +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + l_1 = START(l_4); + uint32_t x_1 = PARAM(l_1, "x", 1); + uint32_t y_1 = PARAM(l_1, "y", 2); + uint32_t z_1 = PARAM(l_1, "z", 3); + uint32_t x_2 = ADD(x_1, y_1); + uint32_t x_3 = DIV(x_2, z_1); + l_4 = RETURN(l_1, x_3); +} +--EXPECT-- +test: + add w0, w1, w0 + udiv w0, w0, w2 + ret diff --git a/tests/aarch64/ra_012.irt b/tests/aarch64/ra_012.irt new file mode 100644 index 0000000..1df8c22 --- /dev/null +++ b/tests/aarch64/ra_012.irt @@ -0,0 +1,22 @@ +--TEST-- +012: Register Allocation (ADD + MOD) +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + l_1 = START(l_4); + uint32_t x_1 = PARAM(l_1, "x", 1); + uint32_t y_1 = PARAM(l_1, "y", 2); + uint32_t z_1 = PARAM(l_1, "z", 3); + uint32_t x_2 = ADD(x_1, y_1); + uint32_t x_3 = MOD(x_2, z_1); + l_4 = RETURN(l_1, x_3); +} +--EXPECT-- +test: + add w0, w1, w0 + udiv w1, w0, w2 + msub w0, w1, w2, w0 + ret diff --git a/tests/aarch64/ra_013.irt b/tests/aarch64/ra_013.irt new file mode 100644 index 0000000..9b6ae12 --- /dev/null +++ b/tests/aarch64/ra_013.irt @@ -0,0 +1,27 @@ +--TEST-- +013: Register Allocation (MOD + MOD + MOD) +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + l_1 = START(l_4); + uint32_t x_1 = PARAM(l_1, "x", 1); + uint32_t y_1 = PARAM(l_1, "y", 2); + uint32_t z_1 = PARAM(l_1, "z", 3); + uint32_t v_1 = PARAM(l_1, "v", 4); + uint32_t x_2 = MOD(x_1, y_1); + uint32_t x_3 = MOD(x_2, z_1); + uint32_t x_4 = MOD(v_1, x_3); + l_4 = RETURN(l_1, x_4); +} +--EXPECT-- +test: + udiv w4, w0, w1 + msub w0, w4, w1, w0 + udiv w1, w0, w2 + msub w0, w1, w2, w0 + udiv w1, w3, w0 + msub w0, w1, w0, w3 + ret diff --git a/tests/aarch64/ra_014.irt b/tests/aarch64/ra_014.irt new file mode 100644 index 0000000..2fe5d6d --- /dev/null +++ b/tests/aarch64/ra_014.irt @@ -0,0 +1,21 @@ +--TEST-- +014: Register Allocation (SHL + SHL) +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + l_1 = START(l_4); + uint32_t x = PARAM(l_1, "x", 1); + uint32_t y = PARAM(l_1, "y", 2); + uint32_t ret = SHL(x, y); + uint32_t ret2 = SHL(x, ret); + l_4 = RETURN(l_1, ret2); +} +--EXPECT-- +test: + lsl w1, w0, w1 + lsl w0, w0, w1 + ret + diff --git a/tests/aarch64/ra_015.irt b/tests/aarch64/ra_015.irt new file mode 100644 index 0000000..45857b5 --- /dev/null +++ b/tests/aarch64/ra_015.irt @@ -0,0 +1,20 @@ +--TEST-- +015: Register Allocation (SHL + SHL + reuse/vreg hint) +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + l_1 = START(l_4); + uint32_t x = PARAM(l_1, "x", 1); + uint32_t y = PARAM(l_1, "y", 2); + uint32_t ret = SHL(x, y); + uint32_t ret2 = SHL(y, ret); + l_4 = RETURN(l_1, ret2); +} +--EXPECT-- +test: + lsl w0, w0, w1 + lsl w0, w1, w0 + ret diff --git a/tests/aarch64/rol_001.irt b/tests/aarch64/rol_001.irt new file mode 100644 index 0000000..8bd79c0 --- /dev/null +++ b/tests/aarch64/rol_001.irt @@ -0,0 +1,19 @@ +--TEST-- +001: rol function +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + l_1 = START(l_4); + int32_t x = PARAM(l_1, "x", 1); + int32_t y = PARAM(l_1, "y", 2); + int32_t ret = ROL(x, y); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + neg w2, w1 + ror w0, w0, w2 + ret diff --git a/tests/aarch64/rol_002.irt b/tests/aarch64/rol_002.irt new file mode 100644 index 0000000..14dd4a2 --- /dev/null +++ b/tests/aarch64/rol_002.irt @@ -0,0 +1,18 @@ +--TEST-- +002: rol function +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + int32_t c = 17; + l_1 = START(l_4); + int32_t x = PARAM(l_1, "x", 1); + int32_t ret = ROL(x, c); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + ror w0, w0, #0xf + ret diff --git a/tests/aarch64/rol_003.irt b/tests/aarch64/rol_003.irt new file mode 100644 index 0000000..8c27ae5 --- /dev/null +++ b/tests/aarch64/rol_003.irt @@ -0,0 +1,19 @@ +--TEST-- +003: rol function +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + l_1 = START(l_4); + int32_t x = PARAM(l_1, "x", 1); + int32_t y = PARAM(l_1, "y", 2); + int32_t ret = ROL(y, x); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + neg w2, w0 + ror w0, w1, w2 + ret diff --git a/tests/aarch64/rol_004.irt b/tests/aarch64/rol_004.irt new file mode 100644 index 0000000..110429f --- /dev/null +++ b/tests/aarch64/rol_004.irt @@ -0,0 +1,20 @@ +--TEST-- +004: rol function +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + int32_t c = 17; + l_1 = START(l_4); + int32_t x = PARAM(l_1, "x", 1); + int32_t ret = ROL(c, x); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + movz w2, #0x11 + neg w1, w0 + ror w0, w2, w1 + ret diff --git a/tests/aarch64/ror_001.irt b/tests/aarch64/ror_001.irt new file mode 100644 index 0000000..6e6aaa6 --- /dev/null +++ b/tests/aarch64/ror_001.irt @@ -0,0 +1,18 @@ +--TEST-- +001: ror function +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + l_1 = START(l_4); + int32_t x = PARAM(l_1, "x", 1); + int32_t y = PARAM(l_1, "y", 2); + int32_t ret = ROR(x, y); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + ror w0, w0, w1 + ret diff --git a/tests/aarch64/ror_002.irt b/tests/aarch64/ror_002.irt new file mode 100644 index 0000000..5d4701e --- /dev/null +++ b/tests/aarch64/ror_002.irt @@ -0,0 +1,18 @@ +--TEST-- +002: ror function +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + int32_t c = 17; + l_1 = START(l_4); + int32_t x = PARAM(l_1, "x", 1); + int32_t ret = ROR(x, c); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + ror w0, w0, #0x11 + ret diff --git a/tests/aarch64/ror_003.irt b/tests/aarch64/ror_003.irt new file mode 100644 index 0000000..6f9851d --- /dev/null +++ b/tests/aarch64/ror_003.irt @@ -0,0 +1,18 @@ +--TEST-- +003: ror function +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + l_1 = START(l_4); + int32_t x = PARAM(l_1, "x", 1); + int32_t y = PARAM(l_1, "y", 2); + int32_t ret = ROR(y, x); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + ror w0, w1, w0 + ret diff --git a/tests/aarch64/ror_004.irt b/tests/aarch64/ror_004.irt new file mode 100644 index 0000000..5832966 --- /dev/null +++ b/tests/aarch64/ror_004.irt @@ -0,0 +1,19 @@ +--TEST-- +004: ror function +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + int32_t c = 17; + l_1 = START(l_4); + int32_t x = PARAM(l_1, "x", 1); + int32_t ret = ROR(c, x); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + movz w1, #0x11 + ror w0, w1, w0 + ret diff --git a/tests/aarch64/shl_001.irt b/tests/aarch64/shl_001.irt new file mode 100644 index 0000000..7b5ded5 --- /dev/null +++ b/tests/aarch64/shl_001.irt @@ -0,0 +1,18 @@ +--TEST-- +001: shl function +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + l_1 = START(l_4); + int32_t x = PARAM(l_1, "x", 1); + int32_t y = PARAM(l_1, "y", 2); + int32_t ret = SHL(x, y); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + lsl w0, w0, w1 + ret diff --git a/tests/aarch64/shl_002.irt b/tests/aarch64/shl_002.irt new file mode 100644 index 0000000..f4620d5 --- /dev/null +++ b/tests/aarch64/shl_002.irt @@ -0,0 +1,18 @@ +--TEST-- +002: shl function +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + int32_t c = 17; + l_1 = START(l_4); + int32_t x = PARAM(l_1, "x", 1); + int32_t ret = SHL(x, c); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + lsl w0, w0, #0x11 + ret diff --git a/tests/aarch64/shl_003.irt b/tests/aarch64/shl_003.irt new file mode 100644 index 0000000..0b7434a --- /dev/null +++ b/tests/aarch64/shl_003.irt @@ -0,0 +1,18 @@ +--TEST-- +003: shl function +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + l_1 = START(l_4); + int32_t x = PARAM(l_1, "x", 1); + int32_t y = PARAM(l_1, "y", 2); + int32_t ret = SHL(y, x); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + lsl w0, w1, w0 + ret diff --git a/tests/aarch64/shl_004.irt b/tests/aarch64/shl_004.irt new file mode 100644 index 0000000..97fe215 --- /dev/null +++ b/tests/aarch64/shl_004.irt @@ -0,0 +1,19 @@ +--TEST-- +004: shl function +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + int32_t c = 17; + l_1 = START(l_4); + int32_t x = PARAM(l_1, "x", 1); + int32_t ret = SHL(c, x); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + movz w1, #0x11 + lsl w0, w1, w0 + ret diff --git a/tests/aarch64/sub_001.irt b/tests/aarch64/sub_001.irt new file mode 100644 index 0000000..2a92926 --- /dev/null +++ b/tests/aarch64/sub_001.irt @@ -0,0 +1,18 @@ +--TEST-- +001: sub function +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + l_1 = START(l_4); + int32_t x = PARAM(l_1, "x", 1); + int32_t y = PARAM(l_1, "y", 2); + int32_t ret = SUB(x, y); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + sub w0, w0, w1 + ret diff --git a/tests/aarch64/sub_002.irt b/tests/aarch64/sub_002.irt new file mode 100644 index 0000000..361b24b --- /dev/null +++ b/tests/aarch64/sub_002.irt @@ -0,0 +1,18 @@ +--TEST-- +002: sub function +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + int32_t c = 17; + l_1 = START(l_4); + int32_t x = PARAM(l_1, "x", 1); + int32_t ret = SUB(x, c); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + sub w0, w0, #0x11 + ret diff --git a/tests/aarch64/sub_003.irt b/tests/aarch64/sub_003.irt new file mode 100644 index 0000000..f7d1952 --- /dev/null +++ b/tests/aarch64/sub_003.irt @@ -0,0 +1,18 @@ +--TEST-- +003: sub function +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + l_1 = START(l_4); + int32_t x = PARAM(l_1, "x", 1); + int32_t y = PARAM(l_1, "y", 2); + int32_t ret = SUB(y, x); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + sub w0, w1, w0 + ret diff --git a/tests/aarch64/sub_004.irt b/tests/aarch64/sub_004.irt new file mode 100644 index 0000000..da15c9a --- /dev/null +++ b/tests/aarch64/sub_004.irt @@ -0,0 +1,19 @@ +--TEST-- +004: sub function +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + int32_t c = 17; + l_1 = START(l_4); + int32_t x = PARAM(l_1, "x", 1); + int32_t ret = SUB(c, x); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + movz w1, #0x11 + sub w0, w1, w0 + ret diff --git a/tests/aarch64/sub_005.irt b/tests/aarch64/sub_005.irt new file mode 100644 index 0000000..9f75719 --- /dev/null +++ b/tests/aarch64/sub_005.irt @@ -0,0 +1,18 @@ +--TEST-- +005: sub function +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + l_1 = START(l_4); + double x = PARAM(l_1, "x", 1); + double y = PARAM(l_1, "y", 2); + double ret = SUB(x, y); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + fsub d0, d0, d1 + ret diff --git a/tests/aarch64/sub_006.irt b/tests/aarch64/sub_006.irt new file mode 100644 index 0000000..75e689c --- /dev/null +++ b/tests/aarch64/sub_006.irt @@ -0,0 +1,18 @@ +--TEST-- +006: sub function +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + l_1 = START(l_4); + double x = PARAM(l_1, "x", 1); + double y = PARAM(l_1, "y", 2); + double ret = SUB(y, x); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + fsub d0, d1, d0 + ret diff --git a/tests/aarch64/sub_007.irt b/tests/aarch64/sub_007.irt new file mode 100644 index 0000000..a1633fc --- /dev/null +++ b/tests/aarch64/sub_007.irt @@ -0,0 +1,18 @@ +--TEST-- +007: sub function +--TARGET-- +aarch64 +--ARGS-- +-S -mavx +--CODE-- +{ + l_1 = START(l_4); + double x = PARAM(l_1, "x", 1); + double y = PARAM(l_1, "y", 2); + double ret = SUB(x, y); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + fsub d0, d0, d1 + ret diff --git a/tests/aarch64/sub_008.irt b/tests/aarch64/sub_008.irt new file mode 100644 index 0000000..be21f1f --- /dev/null +++ b/tests/aarch64/sub_008.irt @@ -0,0 +1,18 @@ +--TEST-- +008: sub function +--TARGET-- +aarch64 +--ARGS-- +-S -mavx +--CODE-- +{ + l_1 = START(l_4); + double x = PARAM(l_1, "x", 1); + double y = PARAM(l_1, "y", 2); + double ret = SUB(y, x); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + fsub d0, d1, d0 + ret diff --git a/tests/aarch64/sub_009.irt b/tests/aarch64/sub_009.irt new file mode 100644 index 0000000..ab3042a --- /dev/null +++ b/tests/aarch64/sub_009.irt @@ -0,0 +1,19 @@ +--TEST-- +009: sub function +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + uint64_t c = 0x100000000; + l_1 = START(l_4); + uint64_t x = PARAM(l_1, "x", 1); + uint64_t ret = SUB(c, x); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + movz x1, #0x1, lsl #32 + sub x0, x1, x0 + ret diff --git a/tests/aarch64/sub_010.irt b/tests/aarch64/sub_010.irt new file mode 100644 index 0000000..759171d --- /dev/null +++ b/tests/aarch64/sub_010.irt @@ -0,0 +1,18 @@ +--TEST-- +010: sub function +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + uint16_t c = 1; + l_1 = START(l_4); + uint16_t x = PARAM(l_1, "x", 1); + uint16_t ret = SUB(x, c); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + sub w0, w0, #1 + ret diff --git a/tests/aarch64/sub_011.irt b/tests/aarch64/sub_011.irt new file mode 100644 index 0000000..7238417 --- /dev/null +++ b/tests/aarch64/sub_011.irt @@ -0,0 +1,23 @@ +--TEST-- +011: sub function +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + double c = 0.5; + l_1 = START(l_4); + double x = PARAM(l_1, "x", 1); + double ret = SUB(c, x); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + ldr d1, .L1 + fsub d0, d1, d0 + ret +.rodata + .db 0x1f, 0x20, 0x03, 0xd5 +.L1: + .db 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x3f diff --git a/tests/aarch64/sub_012.irt b/tests/aarch64/sub_012.irt new file mode 100644 index 0000000..31ebbd7 --- /dev/null +++ b/tests/aarch64/sub_012.irt @@ -0,0 +1,23 @@ +--TEST-- +012: sub function +--TARGET-- +aarch64 +--ARGS-- +-S -mavx +--CODE-- +{ + double c = 0.5; + l_1 = START(l_4); + double x = PARAM(l_1, "x", 1); + double ret = SUB(c, x); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + ldr d1, .L1 + fsub d0, d1, d0 + ret +.rodata + .db 0x1f, 0x20, 0x03, 0xd5 +.L1: + .db 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x3f diff --git a/tests/aarch64/uge_001.irt b/tests/aarch64/uge_001.irt new file mode 100644 index 0000000..7f9f9aa --- /dev/null +++ b/tests/aarch64/uge_001.irt @@ -0,0 +1,19 @@ +--TEST-- +001: uge function +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + l_1 = START(l_4); + uint32_t x = PARAM(l_1, "x", 1); + uint32_t y = PARAM(l_1, "y", 2); + bool ret = UGE(x, y); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + cmp w1, w0 + cset w0, ls + ret diff --git a/tests/aarch64/uge_002.irt b/tests/aarch64/uge_002.irt new file mode 100644 index 0000000..969b4ae --- /dev/null +++ b/tests/aarch64/uge_002.irt @@ -0,0 +1,19 @@ +--TEST-- +002: uge function +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + uint32_t c = 17; + l_1 = START(l_4); + uint32_t x = PARAM(l_1, "x", 1); + bool ret = UGE(x, c); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + cmp w0, #0x11 + cset w0, hs + ret diff --git a/tests/aarch64/uge_003.irt b/tests/aarch64/uge_003.irt new file mode 100644 index 0000000..2027cc7 --- /dev/null +++ b/tests/aarch64/uge_003.irt @@ -0,0 +1,18 @@ +--TEST-- +003: uge function +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + uint32_t c = 0; + l_1 = START(l_4); + uint32_t x = PARAM(l_1, "x", 1); + bool ret = UGE(x, c); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + movz w0, #0x1 + ret diff --git a/tests/aarch64/ugt_001.irt b/tests/aarch64/ugt_001.irt new file mode 100644 index 0000000..1811847 --- /dev/null +++ b/tests/aarch64/ugt_001.irt @@ -0,0 +1,19 @@ +--TEST-- +001: ugt function +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + l_1 = START(l_4); + uint32_t x = PARAM(l_1, "x", 1); + uint32_t y = PARAM(l_1, "y", 2); + bool ret = UGT(x, y); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + cmp w1, w0 + cset w0, lo + ret diff --git a/tests/aarch64/ugt_002.irt b/tests/aarch64/ugt_002.irt new file mode 100644 index 0000000..7ed2552 --- /dev/null +++ b/tests/aarch64/ugt_002.irt @@ -0,0 +1,19 @@ +--TEST-- +002: ugt function +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + uint32_t c = 17; + l_1 = START(l_4); + uint32_t x = PARAM(l_1, "x", 1); + bool ret = UGT(x, c); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + cmp w0, #0x11 + cset w0, hi + ret diff --git a/tests/aarch64/ugt_003.irt b/tests/aarch64/ugt_003.irt new file mode 100644 index 0000000..dee7975 --- /dev/null +++ b/tests/aarch64/ugt_003.irt @@ -0,0 +1,19 @@ +--TEST-- +003: ugt function +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + uint32_t c = 0; + l_1 = START(l_4); + uint32_t x = PARAM(l_1, "x", 1); + bool ret = UGT(x, c); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + cmp w0, #0 + cset w0, ne + ret diff --git a/tests/aarch64/ule_001.irt b/tests/aarch64/ule_001.irt new file mode 100644 index 0000000..7ad7565 --- /dev/null +++ b/tests/aarch64/ule_001.irt @@ -0,0 +1,19 @@ +--TEST-- +001: ule function +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + l_1 = START(l_4); + uint32_t x = PARAM(l_1, "x", 1); + uint32_t y = PARAM(l_1, "y", 2); + bool ret = ULE(x, y); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + cmp w1, w0 + cset w0, hs + ret diff --git a/tests/aarch64/ule_002.irt b/tests/aarch64/ule_002.irt new file mode 100644 index 0000000..5a80247 --- /dev/null +++ b/tests/aarch64/ule_002.irt @@ -0,0 +1,19 @@ +--TEST-- +002: ule function +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + uint32_t c = 17; + l_1 = START(l_4); + uint32_t x = PARAM(l_1, "x", 2); + bool ret = ULE(x, c); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + cmp w0, #0x11 + cset w0, ls + ret diff --git a/tests/aarch64/ule_003.irt b/tests/aarch64/ule_003.irt new file mode 100644 index 0000000..9d3e51f --- /dev/null +++ b/tests/aarch64/ule_003.irt @@ -0,0 +1,19 @@ +--TEST-- +003: ule function +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + uint32_t c = 0; + l_1 = START(l_4); + uint32_t x = PARAM(l_1, "x", 2); + bool ret = ULE(x, c); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + cmp w0, #0 + cset w0, eq + ret diff --git a/tests/aarch64/ult_001.irt b/tests/aarch64/ult_001.irt new file mode 100644 index 0000000..8fb4f1f --- /dev/null +++ b/tests/aarch64/ult_001.irt @@ -0,0 +1,19 @@ +--TEST-- +001: ult function +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + l_1 = START(l_4); + uint32_t x = PARAM(l_1, "x", 1); + uint32_t y = PARAM(l_1, "y", 2); + bool ret = ULT(x, y); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + cmp w1, w0 + cset w0, hi + ret diff --git a/tests/aarch64/ult_002.irt b/tests/aarch64/ult_002.irt new file mode 100644 index 0000000..a8a60c8 --- /dev/null +++ b/tests/aarch64/ult_002.irt @@ -0,0 +1,19 @@ +--TEST-- +002: ult function +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + uint32_t c = 17; + l_1 = START(l_4); + uint32_t x = PARAM(l_1, "x", 1); + bool ret = ULT(x, c); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + cmp w0, #0x11 + cset w0, lo + ret diff --git a/tests/aarch64/ult_003.irt b/tests/aarch64/ult_003.irt new file mode 100644 index 0000000..9983060 --- /dev/null +++ b/tests/aarch64/ult_003.irt @@ -0,0 +1,18 @@ +--TEST-- +003: ult function +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + uint32_t c = 0; + l_1 = START(l_4); + uint32_t x = PARAM(l_1, "x", 1); + bool ret = ULT(x, c); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + mov w0, wzr + ret diff --git a/tests/debug.aarch64/args_001.irt b/tests/debug.aarch64/args_001.irt new file mode 100644 index 0000000..f2229de --- /dev/null +++ b/tests/debug.aarch64/args_001.irt @@ -0,0 +1,57 @@ +--TEST-- +001: Argument Passing +--TARGET-- +aarch64 +--ARGS-- +-S --run +--CODE-- +{ + int8_t c_1 = 1; + int16_t c_2 = 2; + int32_t c_3 = 3; + int64_t c_4 = 4; + int64_t c_5 = 0x100000000; + uint8_t c_6 = 6; + uint16_t c_7 = 7; + uint32_t c_8 = 8; + int64_t c_9 = 9; + int64_t c_10 = 0x100000000; + uintptr_t f = func(printf); + uintptr_t fmt = "%d %d %d %lld 0x%llx %d %d %d %lld 0x%llx\n"; + l_1 = START(l_3); + int32_t d_2, l_2 = CALL/11(l_1, f, fmt, c_1, c_2, c_3, c_4, c_5, c_6, c_7, c_8, c_9, c_10); + l_3 = RETURN(l_2, d_2); +} +--EXPECT-- +test: + stp x29, x30, [sp, #-0x10]! + mov x29, sp + sub sp, sp, #0x20 + movz w8, #0x8 + str x8, [sp] + movz x8, #0x9 + str x8, [sp, #8] + movz x8, #0x1, lsl #32 + str x8, [sp, #0x10] + adr x0, .L1 + movz x1, #0x1 + movz w2, #0x2 + movz w3, #0x3 + movz x4, #0x4 + movz x5, #0x1, lsl #32 + movz x6, #0x6 + movz w7, #0x7 + bl _IO_printf + add sp, sp, #0x20 + ldp x29, x30, [sp], #0x10 + ret +.rodata + .db 0x1f, 0x20, 0x03, 0xd5 +.L1: + .db 0x25, 0x64, 0x20, 0x25, 0x64, 0x20, 0x25, 0x64, 0x20, 0x25, 0x6c, 0x6c, 0x64, 0x20, 0x30, 0x78 + .db 0x25, 0x6c, 0x6c, 0x78, 0x20, 0x25, 0x64, 0x20, 0x25, 0x64, 0x20, 0x25, 0x64, 0x20, 0x25, 0x6c + .db 0x6c, 0x64, 0x20, 0x30, 0x78, 0x25, 0x6c, 0x6c, 0x78, 0x0a, 0x00, 0x00 + +1 2 3 4 0x100000000 6 7 8 9 0x100000000 + +exit code = 40 diff --git a/tests/debug.aarch64/args_002.irt b/tests/debug.aarch64/args_002.irt new file mode 100644 index 0000000..12d979d --- /dev/null +++ b/tests/debug.aarch64/args_002.irt @@ -0,0 +1,72 @@ +--TEST-- +002: Argument Passing +--TARGET-- +aarch64 +--ARGS-- +-S --run +--CODE-- +{ + double c_1 = 0.1; + double c_2 = 0.2; + double c_3 = 0.3; + double c_4 = 0.4; + double c_5 = 0.5; + double c_6 = 0.6; + double c_7 = 0.7; + double c_8 = 0.8; + double c_9 = 0.9; + double c_10 = 0.0; + uintptr_t f = func(printf); + uintptr_t fmt = "%g %g %g %g %g %g %g %g %g %g\n"; + l_1 = START(l_3); + int32_t d_2, l_2 = CALL/11(l_1, f, fmt, c_1, c_2, c_3, c_4, c_5, c_6, c_7, c_8, c_9, c_10); + l_3 = RETURN(l_2, d_2); +} +--EXPECT-- +test: + stp x29, x30, [sp, #-0x10]! + mov x29, sp + sub sp, sp, #0x10 + ldr d31, .L9 + str d31, [sp] + fmov d31, xzr + str d31, [sp, #8] + adr x0, .L10 + ldr d0, .L1 + ldr d1, .L2 + ldr d2, .L3 + ldr d3, .L4 + ldr d4, .L5 + ldr d5, .L6 + ldr d6, .L7 + ldr d7, .L8 + bl _IO_printf + add sp, sp, #0x10 + ldp x29, x30, [sp], #0x10 + ret +.rodata +.L1: + .db 0x9a, 0x99, 0x99, 0x99, 0x99, 0x99, 0xb9, 0x3f +.L2: + .db 0x9a, 0x99, 0x99, 0x99, 0x99, 0x99, 0xc9, 0x3f +.L3: + .db 0x33, 0x33, 0x33, 0x33, 0x33, 0x33, 0xd3, 0x3f +.L4: + .db 0x9a, 0x99, 0x99, 0x99, 0x99, 0x99, 0xd9, 0x3f +.L5: + .db 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x3f +.L6: + .db 0x33, 0x33, 0x33, 0x33, 0x33, 0x33, 0xe3, 0x3f +.L7: + .db 0x66, 0x66, 0x66, 0x66, 0x66, 0x66, 0xe6, 0x3f +.L8: + .db 0x9a, 0x99, 0x99, 0x99, 0x99, 0x99, 0xe9, 0x3f +.L9: + .db 0xcd, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xec, 0x3f +.L10: + .db 0x25, 0x67, 0x20, 0x25, 0x67, 0x20, 0x25, 0x67, 0x20, 0x25, 0x67, 0x20, 0x25, 0x67, 0x20, 0x25 + .db 0x67, 0x20, 0x25, 0x67, 0x20, 0x25, 0x67, 0x20, 0x25, 0x67, 0x20, 0x25, 0x67, 0x0a, 0x00, 0x00 + +0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 0 + +exit code = 38 diff --git a/tests/debug.aarch64/call-O0.irt b/tests/debug.aarch64/call-O0.irt new file mode 100644 index 0000000..4665e05 --- /dev/null +++ b/tests/debug.aarch64/call-O0.irt @@ -0,0 +1,37 @@ +--TEST-- +Simple CALL -O0 +--TARGET-- +aarch64 +--ARGS-- +-S -O0 --run +--CODE-- +{ + uintptr_t c_1 = 0; + bool c_2 = 0; + bool c_3 = 1; + int32_t c_4 = 42; + uintptr_t c_5 = func(printf); + uintptr_t c_6 = "hello %d!\n"; + l_1 = START(l_4); + int32_t d_2, l_2 = CALL/2(l_1, c_5, c_6, c_4); + l_4 = RETURN(l_2, d_2); +} +--EXPECT-- +test: + stp x29, x30, [sp, #-0x20]! + mov x29, sp + adr x0, .L1 + movz w1, #0x2a + bl _IO_printf + str w0, [x29, #0x10] + ldr w0, [x29, #0x10] + ldp x29, x30, [sp], #0x20 + ret +.rodata + .db 0x1f, 0x20, 0x03, 0xd5 +.L1: + .db 0x68, 0x65, 0x6c, 0x6c, 0x6f, 0x20, 0x25, 0x64, 0x21, 0x0a, 0x00, 0x00 + +hello 42! + +exit code = 10 diff --git a/tests/debug.aarch64/call.irt b/tests/debug.aarch64/call.irt new file mode 100644 index 0000000..489eac3 --- /dev/null +++ b/tests/debug.aarch64/call.irt @@ -0,0 +1,35 @@ +--TEST-- +Simple CALL +--TARGET-- +aarch64 +--ARGS-- +-S --run +--CODE-- +{ + uintptr_t c_1 = 0; + bool c_2 = 0; + bool c_3 = 1; + int32_t c_4 = 42; + uintptr_t c_5 = func(printf); + uintptr_t c_6 = "hello %d!\n"; + l_1 = START(l_4); + int32_t d_2, l_2 = CALL/2(l_1, c_5, c_6, c_4); + l_4 = RETURN(l_2, d_2); +} +--EXPECT-- +test: + stp x29, x30, [sp, #-0x10]! + mov x29, sp + adr x0, .L1 + movz w1, #0x2a + bl _IO_printf + ldp x29, x30, [sp], #0x10 + ret +.rodata + .db 0x1f, 0x20, 0x03, 0xd5 +.L1: + .db 0x68, 0x65, 0x6c, 0x6c, 0x6f, 0x20, 0x25, 0x64, 0x21, 0x0a, 0x00, 0x00 + +hello 42! + +exit code = 10 diff --git a/tests/debug.aarch64/call2.irt b/tests/debug.aarch64/call2.irt new file mode 100644 index 0000000..12500ed --- /dev/null +++ b/tests/debug.aarch64/call2.irt @@ -0,0 +1,42 @@ +--TEST-- +CALL with parallel argument passing +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + uintptr_t c_1 = 0; + bool c_2 = 0; + bool c_3 = 1; + int32_t c_4 = 42; + uintptr_t c_5 = func(printf); + uintptr_t c_6 = "hello %d!\n"; + l_1 = START(l_4); + int32_t p_1 = PARAM(l_1, "p1", 1); + int32_t p_2 = PARAM(l_1, "p2", 1); + int32_t p_3 = PARAM(l_1, "p3", 1); + int32_t p_4 = PARAM(l_1, "p4", 1); + int32_t d_2, l_2 = CALL/4(l_1, c_5, c_6, p_3, p_4, p_2); + int32_t d_3 = ADD(d_2, p_1); + l_4 = RETURN(l_2, d_3); +} +--EXPECT-- +test: + stp x29, x30, [sp, #-0x20]! + mov x29, sp + str x19, [x29, #0x18] + mov w19, w0 + mov w4, w1 + mov w1, w2 + mov w2, w3 + mov w3, w4 + adr x0, .L1 + bl _IO_printf + add w0, w0, w19 + ldr x19, [x29, #0x18] + ldp x29, x30, [sp], #0x20 + ret +.rodata +.L1: + .db 0x68, 0x65, 0x6c, 0x6c, 0x6f, 0x20, 0x25, 0x64, 0x21, 0x0a, 0x00, 0x00 diff --git a/tests/debug.aarch64/call3.irt b/tests/debug.aarch64/call3.irt new file mode 100644 index 0000000..6923104 --- /dev/null +++ b/tests/debug.aarch64/call3.irt @@ -0,0 +1,41 @@ +--TEST-- +CALL with parallel argument passing +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + uintptr_t c_6 = "hello %d!\n"; + l_1 = START(l_4); + int32_t p_1 = PARAM(l_1, "p1", 1); + int32_t p_2 = PARAM(l_1, "p2", 2); + int32_t p_3 = PARAM(l_1, "p3", 3); + int32_t p_4 = PARAM(l_1, "p4", 4); + uintptr_t fp = PARAM(l_1, "fp", 5); + uintptr_t f, l_11 = LOAD(l_1, fp); + int32_t d_2, l_2 = CALL/4(l_11, f, c_6, p_3, p_4, p_2); + int32_t d_3 = ADD(d_2, p_1); + l_4 = RETURN(l_2, d_3); +} +--EXPECT-- +test: + stp x29, x30, [sp, #-0x20]! + mov x29, sp + str x19, [x29, #0x18] + mov w19, w0 + ldr x4, [x4] + mov w5, w1 + mov w1, w2 + mov w2, w3 + mov w3, w5 + adr x0, .L1 + blr x4 + add w0, w0, w19 + ldr x19, [x29, #0x18] + ldp x29, x30, [sp], #0x20 + ret +.rodata + .db 0x1f, 0x20, 0x03, 0xd5 +.L1: + .db 0x68, 0x65, 0x6c, 0x6c, 0x6f, 0x20, 0x25, 0x64, 0x21, 0x0a, 0x00, 0x00 diff --git a/tests/debug.aarch64/call_002.irt b/tests/debug.aarch64/call_002.irt new file mode 100644 index 0000000..86be34c --- /dev/null +++ b/tests/debug.aarch64/call_002.irt @@ -0,0 +1,28 @@ +--TEST-- +Indirect CALL +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + uintptr_t c_6 = "hello %d!\n"; + l_1 = START(l_4); + uintptr_t f = PARAM(l_1, "f", 1); + int32_t p = PARAM(l_1, "p", 2); + int32_t d_2, l_2 = CALL/2(l_1, f, c_6, p); + l_4 = RETURN(l_2, d_2); +} +--EXPECT-- +test: + stp x29, x30, [sp, #-0x10]! + mov x29, sp + mov x2, x0 + adr x0, .L1 + blr x2 + ldp x29, x30, [sp], #0x10 + ret +.rodata + .db 0x1f, 0x20, 0x03, 0xd5 +.L1: + .db 0x68, 0x65, 0x6c, 0x6c, 0x6f, 0x20, 0x25, 0x64, 0x21, 0x0a, 0x00, 0x00 diff --git a/tests/debug.aarch64/call_alloca.irt b/tests/debug.aarch64/call_alloca.irt new file mode 100644 index 0000000..16a7d3e --- /dev/null +++ b/tests/debug.aarch64/call_alloca.irt @@ -0,0 +1,68 @@ +--TEST-- +Simple CALL with ALLOCA +--TARGET-- +aarch64 +--ARGS-- +-S --run +--CODE-- +{ + uintptr_t c_1 = 0; + bool c_2 = 0; + bool c_3 = 1; + int32_t c_4 = 42; + char h = 'h'; + char i = 'i'; + char sp = ' '; + char pc = '%'; + char d = 'd'; + char nl = '\n'; + char zero = 0; + uint32_t len = 7; + uintptr_t one = 1; + uintptr_t c_5 = func(printf); + l_1 = START(l_4); + uintptr_t a_0, s_0 = ALLOCA(l_1, len); + s_1 = STORE(s_0, a_0, h); + uintptr_t a_1 = ADD(a_0, one); + s_2 = STORE(s_1, a_1, i); + uintptr_t a_2 = ADD(a_1, one); + s_3 = STORE(s_2, a_2, sp); + uintptr_t a_3 = ADD(a_2, one); + s_4 = STORE(s_3, a_3, pc); + uintptr_t a_4 = ADD(a_3, one); + s_5 = STORE(s_4, a_4, d); + uintptr_t a_5 = ADD(a_4, one); + s_6 = STORE(s_5, a_5, nl); + uintptr_t a_6 = ADD(a_5, one); + s_7 = STORE(s_6, a_6, zero); + int32_t d_2, l_2 = CALL/2(s_7, c_5, a_0, c_4); + l_4 = RETURN(l_2, d_2); +} +--EXPECT-- +test: + stp x29, x30, [sp, #-0x10]! + mov x29, sp + sub sp, sp, #0x10 + mov x0, sp + movz w1, #0x68 + strb w1, [x0] + movz w1, #0x69 + strb w1, [x0, #1] + movz w1, #0x20 + strb w1, [x0, #2] + movz w1, #0x25 + strb w1, [x0, #3] + movz w1, #0x64 + strb w1, [x0, #4] + movz w1, #0xa + strb w1, [x0, #5] + strb wzr, [x0, #6] + movz w1, #0x2a + bl _IO_printf + mov sp, x29 + ldp x29, x30, [sp], #0x10 + ret + +hi 42 + +exit code = 6 diff --git a/tests/debug.aarch64/call_vaddr.irt b/tests/debug.aarch64/call_vaddr.irt new file mode 100644 index 0000000..7e7ac38 --- /dev/null +++ b/tests/debug.aarch64/call_vaddr.irt @@ -0,0 +1,66 @@ +--TEST-- +Simple CALL with VADDR +--TARGET-- +aarch64 +--ARGS-- +-S --run +--CODE-- +{ + uintptr_t c_1 = 0; + bool c_2 = 0; + bool c_3 = 1; + int32_t c_4 = 42; + char h = 'h'; + char i = 'i'; + char sp = ' '; + char pc = '%'; + char d = 'd'; + char nl = '\n'; + char zero = 0; + uintptr_t one = 1; + uintptr_t c_5 = func(printf); + l_1 = START(l_4); + uint64_t var = VAR(l_1, "str"); + uintptr_t a_0 = VADDR(var); + s_1 = STORE(l_1, a_0, h); + uintptr_t a_1 = ADD(a_0, one); + s_2 = STORE(s_1, a_1, i); + uintptr_t a_2 = ADD(a_1, one); + s_3 = STORE(s_2, a_2, sp); + uintptr_t a_3 = ADD(a_2, one); + s_4 = STORE(s_3, a_3, pc); + uintptr_t a_4 = ADD(a_3, one); + s_5 = STORE(s_4, a_4, d); + uintptr_t a_5 = ADD(a_4, one); + s_6 = STORE(s_5, a_5, nl); + uintptr_t a_6 = ADD(a_5, one); + s_7 = STORE(s_6, a_6, zero); + int32_t d_2, l_2 = CALL/2(s_7, c_5, a_0, c_4); + l_4 = RETURN(l_2, d_2); +} +--EXPECT-- +test: + stp x29, x30, [sp, #-0x20]! + mov x29, sp + add x0, x29, #0x10 + movz w1, #0x68 + strb w1, [x0] + movz w1, #0x69 + strb w1, [x0, #1] + movz w1, #0x20 + strb w1, [x0, #2] + movz w1, #0x25 + strb w1, [x0, #3] + movz w1, #0x64 + strb w1, [x0, #4] + movz w1, #0xa + strb w1, [x0, #5] + strb wzr, [x0, #6] + movz w1, #0x2a + bl _IO_printf + ldp x29, x30, [sp], #0x20 + ret + +hi 42 + +exit code = 6 diff --git a/tests/debug.aarch64/combo_001.irt b/tests/debug.aarch64/combo_001.irt new file mode 100644 index 0000000..2e4fede --- /dev/null +++ b/tests/debug.aarch64/combo_001.irt @@ -0,0 +1,43 @@ +--TEST-- +Combo 001 +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +# Figure 3.9 from "Combining Analyses, Combining Optimization" by C.Click +#func test(bool): uint32_t +{ + uintptr_t c_1 = 0; + bool c_2 = 0; + bool c_3 = 1; + int32_t i_1 = 1; + int32_t i_2 = 2; + ll_1 = START(ll_16); + bool cond = PARAM(ll_1, "cond", 0); + int32_t x_0 = COPY(i_1); + ll_2 = END(ll_1); + ll_3 = LOOP_BEGIN(ll_2, ll_12); + int32_t x_1 = PHI(ll_3, x_0, x_3); + bool b = NE(x_1, i_1); + ll_4 = IF(ll_3, b); + ll_5 = IF_TRUE(ll_4); + int32_t x_2 = COPY(i_2); + ll_6 = END(ll_5); + ll_7 = IF_FALSE(ll_4); + ll_72 = END(ll_7); + ll_8 = MERGE(ll_6, ll_72); + int32_t x_3 = PHI(ll_8, x_2, x_1); + ll_10 = IF(ll_8, cond); + ll_11 = IF_TRUE(ll_10); + ll_12 = LOOP_END(ll_11, ll_3); + ll_13 = IF_FALSE(ll_10); + ll_16 = RETURN(ll_13, x_3); +} +--EXPECT-- +test: +.L1: + cmp w0, #0 + b.ne .L1 + movz w0, #0x1 + ret diff --git a/tests/debug.aarch64/combo_002.irt b/tests/debug.aarch64/combo_002.irt new file mode 100644 index 0000000..a4f75c9 --- /dev/null +++ b/tests/debug.aarch64/combo_002.irt @@ -0,0 +1,55 @@ +--TEST-- +Combo 002 +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +#func test(bool, bool): int32_t +{ + uintptr_t c_1 = 0; + bool c_2 = 0; + bool c_3 = 1; + int32_t c_4 = 1; + int32_t c_5 = 2; + l_1 = START(l_34); + bool d_2 = PARAM(l_1, "cond", 0); + int32_t d_3 = PARAM(l_1, "z", 1); + bool d_4 = COPY(c_4); + bool d_5 = COPY(d_3); + l_6 = END(l_1); + l_7 = LOOP_BEGIN(l_6, l_31); + int32_t d_8 = PHI(l_7, d_4, d_19); + int32_t d_9 = PHI(l_7, d_5, d_28); + bool d_10 = NE(d_9, d_3); + l_11 = IF(l_7, d_10); + l_12 = IF_TRUE(l_11); + int32_t d_13 = COPY(c_5); + l_14 = END(l_12); + l_15 = IF_FALSE(l_11); + l_16 = END(l_15); + l_17 = MERGE(l_14, l_16); + int32_t d_18 = PHI(l_17, d_13, d_8); + int32_t d_19 = SUB(c_5, d_18); + bool d_20 = NE(d_19, c_4); + l_21 = IF(l_17, d_20); + l_22 = IF_TRUE(l_21); + int32_t d_23 = COPY(c_5); + l_24 = END(l_22); + l_25 = IF_FALSE(l_21); + l_26 = END(l_25); + l_27 = MERGE(l_24, l_26); + int32_t d_28 = PHI(l_27, d_23, d_9); + l_29 = IF(l_27, d_2); + l_30 = IF_TRUE(l_29); + l_31 = LOOP_END(l_30, l_7); + l_32 = IF_FALSE(l_29); + l_34 = RETURN(l_32, d_19); +} +--EXPECT-- +test: +.L1: + cmp w0, #0 + b.ne .L1 + movz w0, #0x1 + ret diff --git a/tests/debug.aarch64/combo_003.irt b/tests/debug.aarch64/combo_003.irt new file mode 100644 index 0000000..3273dc2 --- /dev/null +++ b/tests/debug.aarch64/combo_003.irt @@ -0,0 +1,55 @@ +--TEST-- +Combo 003 +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + uintptr_t c_1 = 0; + bool c_2 = 0; + bool c_3 = 1; + int32_t c_4 = 1; + int32_t c_5 = 2; + l_1 = START(l_34); + bool d_2 = PARAM(l_1, "cond", 0); + int32_t d_3 = PARAM(l_1, "z", 1); + bool d_4 = COPY(c_4); + int32_t d_5 = COPY(d_3); + l_6 = END(l_1); + l_7 = LOOP_BEGIN(l_6, l_31); + int32_t d_8 = PHI(l_7, d_4, d_19); + int32_t d_9 = PHI(l_7, d_5, d_28); + bool d_10 = NE(d_9, d_3); + l_11 = IF(l_7, d_10); + l_12 = IF_TRUE(l_11); + int32_t d_13 = COPY(c_5); + l_14 = END(l_12); + l_15 = IF_FALSE(l_11); + l_16 = END(l_15); + l_17 = MERGE(l_14, l_16); + int32_t d_18 = PHI(l_17, d_13, d_8); + int32_t d_19 = SUB(c_5, d_18); + bool d_20 = NE(d_19, c_4); + l_21 = IF(l_17, d_20); + l_22 = IF_TRUE(l_21); + int32_t d_23 = COPY(c_5); + l_24 = END(l_22); + l_25 = IF_FALSE(l_21); + l_26 = END(l_25); + l_27 = MERGE(l_24, l_26); + int32_t d_28 = PHI(l_27, d_23, d_9); + l_29 = IF(l_27, d_2); + l_30 = IF_TRUE(l_29); + l_31 = LOOP_END(l_30, l_7); + l_32 = IF_FALSE(l_29); + int32_t xx = MUL(d_19, d_28); + l_34 = RETURN(l_32, xx); +} +--EXPECT-- +test: +.L1: + cmp w0, #0 + b.ne .L1 + mov w0, w1 + ret diff --git a/tests/debug.aarch64/combo_004.irt b/tests/debug.aarch64/combo_004.irt new file mode 100644 index 0000000..249c81a --- /dev/null +++ b/tests/debug.aarch64/combo_004.irt @@ -0,0 +1,46 @@ +--TEST-- +Combo 004 +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +# Figure 3.9 from "Combining Analyses, Combining Optimization" by C.Click +{ + uintptr_t c_1 = 0; + bool c_2 = 0; + bool c_3 = 1; + int32_t i_1 = 1; + int32_t i_2 = 2; + ll_1 = START(ll_16); + bool cond = PARAM(ll_1, "cond", 0); + int32_t ret = PARAM(ll_1, "ret", 1); + int32_t x_0 = COPY(i_1); + ll_2 = END(ll_1); + ll_3 = LOOP_BEGIN(ll_2, ll_12); + int32_t x_1 = PHI(ll_3, x_0, x_3); + bool b = NE(x_1, i_1); + ll_4 = IF(ll_3, b); + ll_5 = IF_TRUE(ll_4); + int32_t x_2 = COPY(i_2); + ll_6 = END(ll_5); + ll_7 = IF_FALSE(ll_4); + ll_72 = END(ll_7); + ll_8 = MERGE(ll_6, ll_72); + int32_t x_3 = PHI(ll_8, x_2, x_1); + ll_10 = IF(ll_8, cond); + ll_11 = IF_TRUE(ll_10); + ll_12 = LOOP_END(ll_11, ll_3); + ll_13 = IF_FALSE(ll_10); + int32_t xx = MUL(x_3, i_2); + int32_t yy = MUL(xx, ret); + ll_16 = RETURN(ll_13, yy); +} +--EXPECT-- +test: + add w1, w1, w1 +.L1: + cmp w0, #0 + b.ne .L1 + mov w0, w1 + ret diff --git a/tests/debug.aarch64/dce_001.irt b/tests/debug.aarch64/dce_001.irt new file mode 100644 index 0000000..572d7c6 --- /dev/null +++ b/tests/debug.aarch64/dce_001.irt @@ -0,0 +1,41 @@ +--TEST-- +DCE 001 +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + uintptr_t c_1 = 0; + bool c_2 = 0; + bool c_3 = 1; + int32_t c_4 = 10; + int32_t c_5 = 2; + int32_t c_6 = 1; + int32_t c_7 = 0; + l_1 = START(l_16); + int32_t d_2 = PARAM(l_1, "x", 0); + l_3 = END(l_1); + l_4 = LOOP_BEGIN(l_3, l_12); + int32_t d_5 = PHI(l_4, c_7, d_7); + int32_t d_6 = ADD(d_2, c_6); + int32_t d_7 = ADD(d_6, d_5); + int32_t d_8 = MUL(d_7, c_5); + int32_t xxx = DIV(d_8, c_4); + bool d_9 = LT(d_7, c_4); + l_10 = IF(l_4, d_9); + l_11 = IF_TRUE(l_10); + l_12 = LOOP_END(l_11, l_4); + l_13 = IF_FALSE(l_10); + l_16 = RETURN(l_13, d_8); +} +--EXPECT-- +test: + add w0, w0, #1 + mov w1, wzr +.L1: + add w1, w0, w1 + cmp w1, #0xa + b.lt .L1 + add w0, w1, w1 + ret diff --git a/tests/debug.aarch64/dessa_001.irt b/tests/debug.aarch64/dessa_001.irt new file mode 100644 index 0000000..407f4ed --- /dev/null +++ b/tests/debug.aarch64/dessa_001.irt @@ -0,0 +1,32 @@ +--TEST-- +DESSA 001 +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +# Figure 1 from "Translating Out of Static Single Assignment Form" by Sreedhar +{ + uintptr_t c_1 = 0; + bool c_2 = 0; + bool c_3 = 1; + l_1 = START(l_13); + int32_t d_2 = PARAM(l_1, "a", 0); + int32_t d_3 = PARAM(l_1, "b", 1); + bool d_4 = PARAM(l_1, "cond", 2); + l_6 = IF(l_1, d_4); + l_7 = IF_TRUE(l_6); + l_8 = END(l_7); + l_9 = IF_FALSE(l_6); + l_10 = END(l_9); + l_11 = MERGE(l_8, l_10); + int32_t d_12 = PHI(l_11, d_3, d_2); + l_13 = RETURN(l_11, d_12); +} +--EXPECT-- +test: + cmp w2, #0 + b.eq .L1 + mov w0, w1 +.L1: + ret diff --git a/tests/debug.aarch64/dessa_002.irt b/tests/debug.aarch64/dessa_002.irt new file mode 100644 index 0000000..1ef29e8 --- /dev/null +++ b/tests/debug.aarch64/dessa_002.irt @@ -0,0 +1,34 @@ +--TEST-- +DESSA 002 +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + uintptr_t c_1 = 0; + bool c_2 = 0; + bool c_3 = 1; + int32_t c_4 = 1; + l_1 = START(l_13); + int32_t d_2 = PARAM(l_1, "x", 0); + l_3 = END(l_1); + l_4 = LOOP_BEGIN(l_3, l_9); + int32_t d_5 = PHI(l_4, d_2, d_6); + int32_t d_6 = ADD(d_5, c_4); + l_7 = IF(l_4, d_6); + l_8 = IF_TRUE(l_7); + l_9 = LOOP_END(l_8, l_4); + l_10 = IF_FALSE(l_7); + l_13 = RETURN(l_10, d_5); +} +--EXPECT-- +test: +.L1: + add w1, w0, #1 + cmp w1, #0 + b.eq .L2 + mov w0, w1 + b .L1 +.L2: + ret diff --git a/tests/debug.aarch64/dessa_003.irt b/tests/debug.aarch64/dessa_003.irt new file mode 100644 index 0000000..a07e646 --- /dev/null +++ b/tests/debug.aarch64/dessa_003.irt @@ -0,0 +1,45 @@ +--TEST-- +DESSA 003 +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +# Figure 8 (swap problem) from "Translating Out of Static Single Assignment Form" by Sreedhar +{ + uintptr_t c_1 = 0; + bool c_2 = 0; + bool c_3 = 1; + int32_t c_4 = 1; + int32_t c_12 = 12; + l_1 = START(l_13); + int32_t x0 = PARAM(l_1, "x", 0); + int32_t y1 = PARAM(l_1, "y", 1); + int32_t cond = PARAM(l_1, "z", 2); + int32_t x1 = DIV(x0, c_12); + l_3 = END(l_1); + l_4 = LOOP_BEGIN(l_3, l_9); + int32_t x2 = PHI(l_4, x1, x3); + int32_t y2 = PHI(l_4, y1, y3); + int32_t z = COPY(x2); + int32_t x3 = COPY(y2); + int32_t y3 = COPY(z); + l_7 = IF(l_4, cond); + l_8 = IF_TRUE(l_7); + l_9 = LOOP_END(l_8, l_4); + l_10 = IF_FALSE(l_7); + l_13 = RETURN(l_10, z); +} +--EXPECT-- +test: + movz w3, #0xc + sdiv w0, w0, w3 +.L1: + cmp w2, #0 + b.eq .L2 + mov w3, w0 + mov w0, w1 + mov w1, w3 + b .L1 +.L2: + ret diff --git a/tests/debug.aarch64/fig-O0.irt b/tests/debug.aarch64/fig-O0.irt new file mode 100644 index 0000000..5917870 --- /dev/null +++ b/tests/debug.aarch64/fig-O0.irt @@ -0,0 +1,198 @@ +--TEST-- +Fig -O0 +--TARGET-- +aarch64 +--ARGS-- +-S -O0 +--CODE-- +{ + uintptr_t c_1 = 0; + bool c_2 = 0; + bool c_3 = 1; + int32_t i_1 = 1; + int32_t i_4 = 4; + ll_1 = START(ll_16); # <- + int32_t a_0 = PARAM(ll_1, "a", 0); + int32_t b_0 = PARAM(ll_1, "b", 1); + int32_t c_0 = PARAM(ll_1, "c", 2); + int32_t d_0 = PARAM(ll_1, "d", 3); + int32_t l_0 = PARAM(ll_1, "l", 4); + int32_t m_0 = PARAM(ll_1, "m", 5); + int32_t s_0 = PARAM(ll_1, "s", 6); + int32_t t_0 = PARAM(ll_1, "t", 7); + int32_t cond1 = PARAM(ll_1, "cond1", 8); + int32_t cond2 = PARAM(ll_1, "cond2", 9); + ll_2 = END(ll_1); + ll_3 = LOOP_BEGIN(ll_2, ll_12); # <- + int32_t a_1 = PHI(ll_3, a_0, a_3); + int32_t d_1 = PHI(ll_3, d_0, d_3); + int32_t m_1 = PHI(ll_3, m_0, m_3); + int32_t s_1 = PHI(ll_3, s_0, s_3); + int32_t t_1 = PHI(ll_3, t_0, t_3); + ll_4 = IF(ll_3, cond1); + ll_5 = IF_TRUE(ll_4); + int32_t l_1 = MUL(c_0, b_0); + int32_t m_2 = ADD(l_1, i_4); + int32_t a_2 = COPY(c_0); + ll_6 = END(ll_5); + ll_7 = IF_FALSE(ll_4); + int32_t d_2 = COPY(c_0); + int32_t l_2 = MUL(d_2, b_0); + int32_t s_2 = MUL(a_1, b_0); + int32_t t_2 = ADD(s_2, i_1); + ll_8 = END(ll_7); + ll_9 = MERGE(ll_6, ll_8); + int32_t a_3 = PHI(ll_9, a_2, a_1); + int32_t d_3 = PHI(ll_9, d_1, d_2); + int32_t l_3 = PHI(ll_9, l_1, l_2); + int32_t m_3 = PHI(ll_9, m_2, m_1); + int32_t s_3 = PHI(ll_9, s_1, s_2); + int32_t t_3 = PHI(ll_9, t_1, t_2); + int32_t x_0 = MUL(a_3, b_0); + int32_t y_0 = ADD(x_0, i_1); + ll_10 = IF(ll_9, cond2); + ll_11 = IF_TRUE(ll_10); + ll_12 = LOOP_END(ll_11, ll_3); + ll_13 = IF_FALSE(ll_10); + int32_t ret1 = ADD(a_3, b_0); + int32_t ret2 = ADD(ret1, c_0); + int32_t ret3 = ADD(ret2, d_3); + int32_t ret4 = ADD(ret3, l_3); + int32_t ret5 = ADD(ret4, m_3); + int32_t ret6 = ADD(ret5, s_3); + int32_t ret7 = ADD(ret6, t_3); + int32_t ret8 = ADD(ret7, y_0); + ll_16 = RETURN(ll_13, ret8); +} +--EXPECT-- +test: + sub sp, sp, #0x90 + str w0, [sp] + str w1, [sp, #4] + str w2, [sp, #8] + str w3, [sp, #0xc] + str w5, [sp, #0x10] + str w6, [sp, #0x14] + str w7, [sp, #0x18] + ldr w0, [sp] + str w0, [sp, #0x1c] + ldr w0, [sp, #0xc] + str w0, [sp, #0x20] + ldr w0, [sp, #0x10] + str w0, [sp, #0x24] + ldr w0, [sp, #0x14] + str w0, [sp, #0x28] + ldr w0, [sp, #0x18] + str w0, [sp, #0x2c] +.L1: + ldr w0, [sp, #0x98] + cmp w0, #0 + b.eq .L2 + ldr w1, [sp, #8] + ldr w2, [sp, #4] + mul w0, w1, w2 + str w0, [sp, #0x30] + ldr w1, [sp, #0x30] + add w0, w1, #4 + str w0, [sp, #0x34] + ldr w1, [sp, #8] + mov w0, w1 + str w0, [sp, #0x38] + ldr w0, [sp, #0x38] + str w0, [sp, #0x4c] + ldr w0, [sp, #0x20] + str w0, [sp, #0x50] + ldr w0, [sp, #0x30] + str w0, [sp, #0x54] + ldr w0, [sp, #0x34] + str w0, [sp, #0x58] + ldr w0, [sp, #0x28] + str w0, [sp, #0x5c] + ldr w0, [sp, #0x2c] + str w0, [sp, #0x60] + b .L3 +.L2: + ldr w1, [sp, #8] + mov w0, w1 + str w0, [sp, #0x3c] + ldr w1, [sp, #0x3c] + ldr w2, [sp, #4] + mul w0, w1, w2 + str w0, [sp, #0x40] + ldr w1, [sp, #0x1c] + ldr w2, [sp, #4] + mul w0, w1, w2 + str w0, [sp, #0x44] + ldr w1, [sp, #0x44] + add w0, w1, #1 + str w0, [sp, #0x48] + ldr w0, [sp, #0x1c] + str w0, [sp, #0x4c] + ldr w0, [sp, #0x3c] + str w0, [sp, #0x50] + ldr w0, [sp, #0x40] + str w0, [sp, #0x54] + ldr w0, [sp, #0x24] + str w0, [sp, #0x58] + ldr w0, [sp, #0x44] + str w0, [sp, #0x5c] + ldr w0, [sp, #0x48] + str w0, [sp, #0x60] +.L3: + ldr w1, [sp, #0x4c] + ldr w2, [sp, #4] + mul w0, w1, w2 + str w0, [sp, #0x64] + ldr w1, [sp, #0x64] + add w0, w1, #1 + str w0, [sp, #0x68] + ldr w0, [sp, #0xa0] + cmp w0, #0 + b.eq .L4 + ldr w0, [sp, #0x4c] + str w0, [sp, #0x1c] + ldr w0, [sp, #0x50] + str w0, [sp, #0x20] + ldr w0, [sp, #0x58] + str w0, [sp, #0x24] + ldr w0, [sp, #0x5c] + str w0, [sp, #0x28] + ldr w0, [sp, #0x60] + str w0, [sp, #0x2c] + b .L1 +.L4: + ldr w1, [sp, #0x4c] + ldr w2, [sp, #4] + add w0, w1, w2 + str w0, [sp, #0x6c] + ldr w1, [sp, #0x6c] + ldr w2, [sp, #8] + add w0, w1, w2 + str w0, [sp, #0x70] + ldr w1, [sp, #0x70] + ldr w2, [sp, #0x50] + add w0, w1, w2 + str w0, [sp, #0x74] + ldr w1, [sp, #0x74] + ldr w2, [sp, #0x54] + add w0, w1, w2 + str w0, [sp, #0x78] + ldr w1, [sp, #0x78] + ldr w2, [sp, #0x58] + add w0, w1, w2 + str w0, [sp, #0x7c] + ldr w1, [sp, #0x7c] + ldr w2, [sp, #0x5c] + add w0, w1, w2 + str w0, [sp, #0x80] + ldr w1, [sp, #0x80] + ldr w2, [sp, #0x60] + add w0, w1, w2 + str w0, [sp, #0x84] + ldr w1, [sp, #0x84] + ldr w2, [sp, #0x68] + add w0, w1, w2 + str w0, [sp, #0x88] + ldr w0, [sp, #0x88] + add sp, sp, #0x90 + ret diff --git a/tests/debug.aarch64/fig.irt b/tests/debug.aarch64/fig.irt new file mode 100644 index 0000000..b59bb68 --- /dev/null +++ b/tests/debug.aarch64/fig.irt @@ -0,0 +1,96 @@ +--TEST-- +Fig +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + uintptr_t c_1 = 0; + bool c_2 = 0; + bool c_3 = 1; + int32_t i_1 = 1; + int32_t i_4 = 4; + ll_1 = START(ll_16); # <- + int32_t a_0 = PARAM(ll_1, "a", 0); + int32_t b_0 = PARAM(ll_1, "b", 1); + int32_t c_0 = PARAM(ll_1, "c", 2); + int32_t d_0 = PARAM(ll_1, "d", 3); + int32_t l_0 = PARAM(ll_1, "l", 4); + int32_t m_0 = PARAM(ll_1, "m", 5); + int32_t s_0 = PARAM(ll_1, "s", 6); + int32_t t_0 = PARAM(ll_1, "t", 7); + int32_t cond1 = PARAM(ll_1, "cond1", 8); + int32_t cond2 = PARAM(ll_1, "cond2", 9); + ll_2 = END(ll_1); + ll_3 = LOOP_BEGIN(ll_2, ll_12); # <- + int32_t a_1 = PHI(ll_3, a_0, a_3); + int32_t d_1 = PHI(ll_3, d_0, d_3); + int32_t m_1 = PHI(ll_3, m_0, m_3); + int32_t s_1 = PHI(ll_3, s_0, s_3); + int32_t t_1 = PHI(ll_3, t_0, t_3); + ll_4 = IF(ll_3, cond1); + ll_5 = IF_TRUE(ll_4); + int32_t l_1 = MUL(c_0, b_0); + int32_t m_2 = ADD(l_1, i_4); + int32_t a_2 = COPY(c_0); + ll_6 = END(ll_5); + ll_7 = IF_FALSE(ll_4); + int32_t d_2 = COPY(c_0); + int32_t l_2 = MUL(d_2, b_0); + int32_t s_2 = MUL(a_1, b_0); + int32_t t_2 = ADD(s_2, i_1); + ll_8 = END(ll_7); + ll_9 = MERGE(ll_6, ll_8); + int32_t a_3 = PHI(ll_9, a_2, a_1); + int32_t d_3 = PHI(ll_9, d_1, d_2); + int32_t l_3 = PHI(ll_9, l_1, l_2); + int32_t m_3 = PHI(ll_9, m_2, m_1); + int32_t s_3 = PHI(ll_9, s_1, s_2); + int32_t t_3 = PHI(ll_9, t_1, t_2); + int32_t x_0 = MUL(a_3, b_0); + int32_t y_0 = ADD(x_0, i_1); + ll_10 = IF(ll_9, cond2); + ll_11 = IF_TRUE(ll_10); + ll_12 = LOOP_END(ll_11, ll_3); + ll_13 = IF_FALSE(ll_10); + int32_t ret1 = ADD(a_3, b_0); + int32_t ret2 = ADD(ret1, c_0); + int32_t ret3 = ADD(ret2, d_3); + int32_t ret4 = ADD(ret3, l_3); + int32_t ret5 = ADD(ret4, m_3); + int32_t ret6 = ADD(ret5, s_3); + int32_t ret7 = ADD(ret6, t_3); + int32_t ret8 = ADD(ret7, y_0); + ll_16 = RETURN(ll_13, ret8); +} +--EXPECT-- +test: + ldr w4, [sp, #8] + ldr w8, [sp, #0x10] + mul w9, w2, w1 + add w10, w9, #4 +.L1: + cmp w4, #0 + b.eq .L3 + mov w0, w2 + mov w5, w10 +.L2: + cmp w8, #0 + b.ne .L1 + mul w4, w0, w1 + add w4, w4, #1 + add w0, w0, w1 + add w0, w0, w2 + add w0, w0, w3 + add w0, w0, w9 + add w0, w0, w5 + add w0, w0, w6 + add w0, w0, w7 + add w0, w0, w4 + ret +.L3: + mul w6, w0, w1 + add w7, w6, #1 + mov w3, w2 + b .L2 diff --git a/tests/debug.aarch64/ijmp_001.irt b/tests/debug.aarch64/ijmp_001.irt new file mode 100644 index 0000000..df7eec6 --- /dev/null +++ b/tests/debug.aarch64/ijmp_001.irt @@ -0,0 +1,15 @@ +--TEST-- +001: IJMP - computed goto +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + l_1 = START(l_2); + uintptr_t p = PARAM(l_1, "p", 1); + l_2 = IJMP(l_1, p); +} +--EXPECT-- +test: + br x0 diff --git a/tests/debug.aarch64/loop_001.irt b/tests/debug.aarch64/loop_001.irt new file mode 100644 index 0000000..4c245db --- /dev/null +++ b/tests/debug.aarch64/loop_001.irt @@ -0,0 +1,40 @@ +--TEST-- +LOOP 001 +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + uintptr_t c_1 = 0; + bool c_2 = 0; + bool c_3 = 1; + int32_t c_4 = 10; + int32_t c_5 = 2; + int32_t c_6 = 1; + int32_t c_7 = 0; + l_1 = START(l_16); + int32_t d_2 = PARAM(l_1, "x", 0); + l_3 = END(l_1); + l_4 = LOOP_BEGIN(l_3, l_12); + int32_t d_5 = PHI(l_4, c_7, d_7); + int32_t d_6 = ADD(d_2, c_6); + int32_t d_7 = ADD(d_6, d_5); + int32_t d_8 = MUL(d_7, c_5); + bool d_9 = LT(d_7, c_4); + l_10 = IF(l_4, d_9); + l_11 = IF_TRUE(l_10); + l_12 = LOOP_END(l_11, l_4); + l_13 = IF_FALSE(l_10); + l_16 = RETURN(l_13, d_8); +} +--EXPECT-- +test: + add w0, w0, #1 + mov w1, wzr +.L1: + add w1, w0, w1 + cmp w1, #0xa + b.lt .L1 + add w0, w1, w1 + ret diff --git a/tests/debug.aarch64/loop_002.irt b/tests/debug.aarch64/loop_002.irt new file mode 100644 index 0000000..0f2be88 --- /dev/null +++ b/tests/debug.aarch64/loop_002.irt @@ -0,0 +1,68 @@ +--TEST-- +LOOP 002 +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + uintptr_t c_1 = 0; + bool c_2 = 0; + bool c_3 = 1; + int32_t c_4 = 0; + int32_t c_5 = 1; + int32_t c_6 = 10; + l_1 = START(l_35); + l_2 = END(l_1); + l_3 = LOOP_BEGIN(l_2, l_30); + int32_t d_4 = PHI(l_3, c_4, d_29); + int32_t d_5 = PHI(l_3, c_4, d_12); + bool d_6 = LT(d_4, c_6); + l_7 = IF(l_3, d_6); + l_8 = IF_TRUE(l_7); + l_9 = END(l_8); + l_10 = LOOP_BEGIN(l_9, l_26); + int32_t d_11 = PHI(l_10, c_4, d_25); + int32_t d_12 = PHI(l_10, d_5, d_24); + bool d_13 = LT(d_11, c_6); + l_14 = IF(l_10, d_13); + l_15 = IF_TRUE(l_14); + bool d_16 = NE(d_11, d_4); + l_17 = IF(l_15, d_16); + l_18 = IF_TRUE(l_17); + int32_t d_19 = ADD(d_12, c_5); + l_20 = END(l_18); + l_21 = IF_FALSE(l_17); + l_22 = END(l_21); + l_23 = MERGE(l_20, l_22); + int32_t d_24 = PHI(l_23, d_19, d_12); + int32_t d_25 = ADD(d_11, c_5); + l_26 = LOOP_END(l_23, l_10); + l_27 = IF_FALSE(l_14); + int32_t d_29 = ADD(d_4, c_5); + l_30 = LOOP_END(l_27, l_3); + l_31 = IF_FALSE(l_7); + l_35 = RETURN(l_31, d_5); +} +--EXPECT-- +test: + mov w1, wzr + mov w0, wzr +.L1: + cmp w1, #0xa + b.ge .L5 + mov w2, wzr +.L2: + cmp w2, #0xa + b.ge .L4 + cmp w2, w1 + b.eq .L3 + add w0, w0, #1 +.L3: + add w2, w2, #1 + b .L2 +.L4: + add w1, w1, #1 + b .L1 +.L5: + ret diff --git a/tests/debug.aarch64/memop_001.irt b/tests/debug.aarch64/memop_001.irt new file mode 100644 index 0000000..7ca7113 --- /dev/null +++ b/tests/debug.aarch64/memop_001.irt @@ -0,0 +1,27 @@ +--TEST-- +001: Memory update (binary op with const) +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + int32_t c = 0x80; + l_1 = START(l_5); + int32_t y = PARAM(l_1, "y", 1); + int32_t v = VAR(l_1, "_spill_"); + l_2 = VSTORE(l_1, v, y); + int32_t z, l_3 = VLOAD(l_2, v); + int32_t ret = AND(z, c); + l_4 = VSTORE(l_3, v, ret); + l_5 = RETURN(l_4); +} +--EXPECT-- +test: + sub sp, sp, #8 + str w0, [sp] + ldr w0, [sp] + and w0, w0, #0x80 + str w0, [sp] + add sp, sp, #8 + ret diff --git a/tests/debug.aarch64/memop_002.irt b/tests/debug.aarch64/memop_002.irt new file mode 100644 index 0000000..87c0868 --- /dev/null +++ b/tests/debug.aarch64/memop_002.irt @@ -0,0 +1,27 @@ +--TEST-- +002: Memory update (binary op with reg) +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + int32_t c = 0x80; + l_1 = START(l_5); + int32_t y = PARAM(l_1, "y", 1); + int32_t v = VAR(l_1, "_spill_"); + l_2 = VSTORE(l_1, v, y); + int32_t z, l_3 = VLOAD(l_2, v); + int32_t ret = AND(z, y); + l_4 = VSTORE(l_3, v, ret); + l_5 = RETURN(l_4); +} +--EXPECT-- +test: + sub sp, sp, #8 + str w0, [sp] + ldr w1, [sp] + and w0, w1, w0 + str w0, [sp] + add sp, sp, #8 + ret diff --git a/tests/debug.aarch64/memop_003.irt b/tests/debug.aarch64/memop_003.irt new file mode 100644 index 0000000..a8407e3 --- /dev/null +++ b/tests/debug.aarch64/memop_003.irt @@ -0,0 +1,29 @@ +--TEST-- +003: Memory update (binary op with reg + swap) +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + int32_t c = 0x80; + l_1 = START(l_5); + int32_t y = PARAM(l_1, "y", 1); + int32_t v = VAR(l_1, "_spill_"); + l_2 = VSTORE(l_1, v, y); + int32_t z, l_3 = VLOAD(l_2, v); + int32_t y2 = ADD(y, y); + int32_t ret = AND(y2, z); + l_4 = VSTORE(l_3, v, ret); + l_5 = RETURN(l_4); +} +--EXPECT-- +test: + sub sp, sp, #8 + str w0, [sp] + ldr w1, [sp] + add w0, w0, w0 + and w0, w0, w1 + str w0, [sp] + add sp, sp, #8 + ret diff --git a/tests/debug.aarch64/memop_004.irt b/tests/debug.aarch64/memop_004.irt new file mode 100644 index 0000000..b1da460 --- /dev/null +++ b/tests/debug.aarch64/memop_004.irt @@ -0,0 +1,27 @@ +--TEST-- +004: Memory update (inc/dec) +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + int8_t c = 1; + l_1 = START(l_5); + int8_t y = PARAM(l_1, "y", 1); + int8_t v = VAR(l_1, "_spill_"); + l_2 = VSTORE(l_1, v, y); + int8_t z, l_3 = VLOAD(l_2, v); + int8_t ret = ADD(z, c); + l_4 = VSTORE(l_3, v, ret); + l_5 = RETURN(l_4); +} +--EXPECT-- +test: + sub sp, sp, #8 + strb w0, [sp] + ldrsb w0, [sp] + add w0, w0, #1 + strb w0, [sp] + add sp, sp, #8 + ret diff --git a/tests/debug.aarch64/memop_005.irt b/tests/debug.aarch64/memop_005.irt new file mode 100644 index 0000000..30c7806 --- /dev/null +++ b/tests/debug.aarch64/memop_005.irt @@ -0,0 +1,27 @@ +--TEST-- +005: Memory update (mul pwr2) +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + int32_t c = 16; + l_1 = START(l_5); + int32_t y = PARAM(l_1, "y", 1); + int32_t v = VAR(l_1, "_spill_"); + l_2 = VSTORE(l_1, v, y); + int32_t z, l_3 = VLOAD(l_2, v); + int32_t ret = MUL(z, c); + l_4 = VSTORE(l_3, v, ret); + l_5 = RETURN(l_4); +} +--EXPECT-- +test: + sub sp, sp, #8 + str w0, [sp] + ldr w0, [sp] + lsl w0, w0, #4 + str w0, [sp] + add sp, sp, #8 + ret diff --git a/tests/debug.aarch64/memop_006.irt b/tests/debug.aarch64/memop_006.irt new file mode 100644 index 0000000..1e46f8d --- /dev/null +++ b/tests/debug.aarch64/memop_006.irt @@ -0,0 +1,26 @@ +--TEST-- +006: Memory update (shift) +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + l_1 = START(l_5); + int32_t y = PARAM(l_1, "y", 1); + int32_t v = VAR(l_1, "_spill_"); + l_2 = VSTORE(l_1, v, y); + int32_t z, l_3 = VLOAD(l_2, v); + int32_t ret = SHL(z, y); + l_4 = VSTORE(l_3, v, ret); + l_5 = RETURN(l_4); +} +--EXPECT-- +test: + sub sp, sp, #8 + str w0, [sp] + ldr w1, [sp] + lsl w0, w1, w0 + str w0, [sp] + add sp, sp, #8 + ret diff --git a/tests/debug.aarch64/memop_007.irt b/tests/debug.aarch64/memop_007.irt new file mode 100644 index 0000000..0efc3bc --- /dev/null +++ b/tests/debug.aarch64/memop_007.irt @@ -0,0 +1,27 @@ +--TEST-- +007: Memory update (shift const) +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + int32_t c = 3; + l_1 = START(l_5); + int32_t y = PARAM(l_1, "y", 1); + int32_t v = VAR(l_1, "_spill_"); + l_2 = VSTORE(l_1, v, y); + int32_t z, l_3 = VLOAD(l_2, v); + int32_t ret = SHL(z, c); + l_4 = VSTORE(l_3, v, ret); + l_5 = RETURN(l_4); +} +--EXPECT-- +test: + sub sp, sp, #8 + str w0, [sp] + ldr w0, [sp] + lsl w0, w0, #3 + str w0, [sp] + add sp, sp, #8 + ret diff --git a/tests/debug.aarch64/memop_008.irt b/tests/debug.aarch64/memop_008.irt new file mode 100644 index 0000000..427355f --- /dev/null +++ b/tests/debug.aarch64/memop_008.irt @@ -0,0 +1,22 @@ +--TEST-- +008: Memory update (LOAD/STORE) +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + int32_t c = 0x80; + l_1 = START(l_4); + uintptr_t p = PARAM(l_1, "p", 1); + int32_t z, l_2 = LOAD(l_1, p); + int32_t ret = AND(z, c); + l_3 = STORE(l_2, p, ret); + l_4 = RETURN(l_3); +} +--EXPECT-- +test: + ldr w1, [x0] + and w1, w1, #0x80 + str w1, [x0] + ret diff --git a/tests/debug.aarch64/params_001.irt b/tests/debug.aarch64/params_001.irt new file mode 100644 index 0000000..00e4627 --- /dev/null +++ b/tests/debug.aarch64/params_001.irt @@ -0,0 +1,44 @@ +--TEST-- +001: Parameter Loading +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + l_1 = START(l_2); + int32_t p_1 = PARAM(l_1, "p_1", 1); + int32_t p_2 = PARAM(l_1, "p_2", 1); + int32_t p_3 = PARAM(l_1, "p_3", 1); + int32_t p_4 = PARAM(l_1, "p_4", 1); + int32_t p_5 = PARAM(l_1, "p_5", 1); + int32_t p_6 = PARAM(l_1, "p_6", 1); + int32_t p_7 = PARAM(l_1, "p_7", 1); + int32_t p_8 = PARAM(l_1, "p_8", 1); + int32_t p_9 = PARAM(l_1, "p_9", 1); + int32_t p_10 = PARAM(l_1, "p_10", 1); + int32_t r1 = ADD(p_1, p_2); + int32_t r2 = ADD(r1, p_3); + int32_t r3 = ADD(r2, p_4); + int32_t r4 = ADD(r3, p_5); + int32_t r5 = ADD(r4, p_6); + int32_t r6 = ADD(r5, p_7); + int32_t r7 = ADD(r6, p_8); + int32_t r8 = ADD(r7, p_9); + int32_t ret = SUB(r8, p_10); + l_2 = RETURN(l_1, ret); +} +--EXPECT-- +test: + ldr w8, [sp, #8] + ldr w9, [sp, #0x10] + add w0, w1, w0 + add w0, w0, w2 + add w0, w0, w3 + add w0, w0, w4 + add w0, w0, w5 + add w0, w0, w6 + add w0, w0, w7 + add w0, w0, w8 + sub w0, w0, w9 + ret diff --git a/tests/debug.aarch64/params_002.irt b/tests/debug.aarch64/params_002.irt new file mode 100644 index 0000000..f673279 --- /dev/null +++ b/tests/debug.aarch64/params_002.irt @@ -0,0 +1,44 @@ +--TEST-- +002: Parameter Loading +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + l_1 = START(l_2); + double p_1 = PARAM(l_1, "p_1", 1); + double p_2 = PARAM(l_1, "p_2", 1); + double p_3 = PARAM(l_1, "p_3", 1); + double p_4 = PARAM(l_1, "p_4", 1); + double p_5 = PARAM(l_1, "p_5", 1); + double p_6 = PARAM(l_1, "p_6", 1); + double p_7 = PARAM(l_1, "p_7", 1); + double p_8 = PARAM(l_1, "p_8", 1); + double p_9 = PARAM(l_1, "p_9", 1); + double p_10 = PARAM(l_1, "p_10", 1); + double r1 = ADD(p_1, p_2); + double r2 = ADD(r1, p_3); + double r3 = ADD(r2, p_4); + double r4 = ADD(r3, p_5); + double r5 = ADD(r4, p_6); + double r6 = ADD(r5, p_7); + double r7 = ADD(r6, p_8); + double r8 = ADD(r7, p_9); + double ret = SUB(r8, p_10); + l_2 = RETURN(l_1, ret); +} +--EXPECT-- +test: + ldr d16, [sp, #8] + ldr d17, [sp, #0x10] + fadd d0, d1, d0 + fadd d0, d0, d2 + fadd d0, d0, d3 + fadd d0, d0, d4 + fadd d0, d0, d5 + fadd d0, d0, d6 + fadd d0, d0, d7 + fadd d0, d0, d16 + fsub d0, d0, d17 + ret diff --git a/tests/debug.aarch64/params_003.irt b/tests/debug.aarch64/params_003.irt new file mode 100644 index 0000000..038eba7 --- /dev/null +++ b/tests/debug.aarch64/params_003.irt @@ -0,0 +1,52 @@ +--TEST-- +003: Parameter Loading and argument passing +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + uintptr_t f = func(printf); + uintptr_t fmt = "%d %d %d %d %d %d %d %d %d %d\n"; + l_1 = START(l_3); + int32_t p_1 = PARAM(l_1, "p_1", 1); + int32_t p_2 = PARAM(l_1, "p_2", 2); + int32_t p_3 = PARAM(l_1, "p_3", 3); + int32_t p_4 = PARAM(l_1, "p_4", 4); + int32_t p_5 = PARAM(l_1, "p_5", 5); + int32_t p_6 = PARAM(l_1, "p_6", 6); + int32_t p_7 = PARAM(l_1, "p_7", 7); + int32_t p_8 = PARAM(l_1, "p_8", 8); + int32_t p_9 = PARAM(l_1, "p_9", 9); + int32_t p_10 = PARAM(l_1, "p_10", 10); + int32_t ret, l_2 = CALL/11(l_1, f, fmt, p_1, p_2, p_3, p_4, p_5, p_6, p_7, p_8, p_9, p_10); + l_3 = RETURN(l_2, ret); +} +--EXPECT-- +test: + stp x29, x30, [sp, #-0x10]! + mov x29, sp + mov w8, w7 + sub sp, sp, #0x20 + str w8, [sp] + ldr w9, [x29, #0x20] + str w9, [sp, #8] + ldr w9, [x29, #0x28] + str w9, [sp, #0x10] + mov w7, w6 + mov w6, w5 + mov w5, w4 + mov w4, w3 + mov w3, w2 + mov w2, w1 + mov w1, w0 + adr x0, .L1 + bl _IO_printf + add sp, sp, #0x20 + ldp x29, x30, [sp], #0x10 + ret +.rodata + .db 0x1f, 0x20, 0x03, 0xd5 +.L1: + .db 0x25, 0x64, 0x20, 0x25, 0x64, 0x20, 0x25, 0x64, 0x20, 0x25, 0x64, 0x20, 0x25, 0x64, 0x20, 0x25 + .db 0x64, 0x20, 0x25, 0x64, 0x20, 0x25, 0x64, 0x20, 0x25, 0x64, 0x20, 0x25, 0x64, 0x0a, 0x00, 0x00 diff --git a/tests/debug.aarch64/regset-fib.irt b/tests/debug.aarch64/regset-fib.irt new file mode 100644 index 0000000..7ef0bee --- /dev/null +++ b/tests/debug.aarch64/regset-fib.irt @@ -0,0 +1,135 @@ +--TEST-- +Fib +--TARGET-- +aarch64 +--ARGS-- +--debug-regset 0x3ffffffff --save --dump-live-ranges -S --run +--CODE-- +{ + int32_t zero = 0; + double c_0 = 0; + double c_1 = 1; + double c_10000 = 10000; + uintptr_t f = func(printf); + uintptr_t format = "%g\n"; + l_1 = START(l_6); + double lo_1 = COPY(c_0); + double hi_1 = COPY(c_1); + l_2 = END(l_1); + l_3 = LOOP_BEGIN(l_2, l_9); + double lo_2 = PHI(l_3, lo_1, lo_3); + double hi_2 = PHI(l_3, hi_1, hi_3); + bool b = LT(hi_2, c_10000); + l_4 = IF(l_3, b); + l_7 = IF_TRUE(l_4); + double hi_3 = ADD(hi_2, lo_2); + double lo_3 = SUB(hi_3, lo_2); + l_8 = CALL/2(l_7, f, format, lo_3); +# ll = CALL/2(l_7, f, format, lo_3); +# l_8 = CALL/2(ll, f, format, lo_3); + l_9 = LOOP_END(l_8, l_3); + l_5 = IF_FALSE(l_4); + l_6 = RETURN(l_5, zero); +} +--EXPECT-- +{ + uintptr_t c_1 = 0; + bool c_2 = 0; + bool c_3 = 1; + int32_t c_4 = 0; + double c_5 = 0; + double c_6 = 1; + double c_7 = 10000; + uintptr_t c_8 = func(printf); + uintptr_t c_9 = "%g\n"; + l_1 = START(l_15); + l_2 = END(l_1); + l_3 = LOOP_BEGIN(l_2, l_13); + double d_4 = PHI(l_3, c_5, d_10); + double d_5 = PHI(l_3, c_6, d_9); + bool d_6 = LT(d_5, c_7); + l_7 = IF(l_3, d_6); + l_8 = IF_TRUE(l_7); + double d_9 = ADD(d_5, d_4); + double d_10 = SUB(d_9, d_4); + l_11 = CALL/2(l_8, c_8, c_9, d_10); + l_13 = LOOP_END(l_11, l_3); + l_14 = IF_FALSE(l_7); + l_15 = RETURN(l_14, c_4); +} +{ # LIVE-RANGES (vregs_count=2) +TMP + [%d0]: [2.2-2.3) + [%d0]: [6.0-6.2) + [%x1]: [11.0-11.1) +R1 (d_4, d_10) [SPILL=0x0] + [%d0]: [3.0-6.0), DEF(4.2) + : [6.0-8.0) + [%d0]: [8.0-10.1), [10.2-11.0), USE(9.1/2)!, USE(10.1/2)!, DEF(10.2)!, USE(11.0/4, hint=%d0) + : [11.0-14.0), PHI_USE(13.2, phi=d_4/3) +R2 (d_5, d_9) [SPILL=0x8] + [%d1]: [3.0-9.1), [9.2-10.1), DEF(5.2), USE(6.1/1)!, USE(9.1/1)!, DEF(9.2)!, USE(10.1/1)! + : [10.1-14.0), PHI_USE(13.2, phi=d_5/3) +[%x0] : [11.0-11.1), [15.0-15.1) +[%d0] : [11.0-11.1) +[%SCRATCH] : [11.1-11.2) +} +test: + stp x29, x30, [sp, #-0x20]! + mov x29, sp + fmov d0, xzr + str d0, [x29, #0x10] + ldr d1, .L3 + str d1, [x29, #0x18] +.L1: + ldr d0, .L4 + ldr d1, [x29, #0x18] + fcmp d0, d1 + b.ls .L2 + ldr d1, [x29, #0x18] + ldr d0, [x29, #0x10] + fadd d1, d1, d0 + str d1, [x29, #0x18] + ldr d1, [x29, #0x18] + ldr d0, [x29, #0x10] + fsub d0, d1, d0 + str d0, [x29, #0x10] + ldr d0, [x29, #0x10] + adr x0, .L5 + bl _IO_printf + b .L1 +.L2: + mov w0, wzr + ldp x29, x30, [sp], #0x20 + ret +.rodata + .db 0x1f, 0x20, 0x03, 0xd5 +.L3: + .db 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x3f +.L4: + .db 0x00, 0x00, 0x00, 0x00, 0x00, 0x88, 0xc3, 0x40 +.L5: + .db 0x25, 0x67, 0x0a, 0x00 + +1 +1 +2 +3 +5 +8 +13 +21 +34 +55 +89 +144 +233 +377 +610 +987 +1597 +2584 +4181 +6765 + +exit code = 0 diff --git a/tests/debug.aarch64/regset-fib2.irt b/tests/debug.aarch64/regset-fib2.irt new file mode 100644 index 0000000..60cf42c --- /dev/null +++ b/tests/debug.aarch64/regset-fib2.irt @@ -0,0 +1,158 @@ +--TEST-- +Fib2 +--TARGET-- +aarch64 +--ARGS-- +--debug-regset 0x3ffffffff --save --dump-live-ranges -S --run +--CODE-- +{ + int32_t zero = 0; + double c_0 = 0; + double c_1 = 1; + double c_10000 = 10000; + uintptr_t f = func(printf); + uintptr_t format = "%g\n"; + l_1 = START(l_6); + double lo_1 = COPY(c_0); + double hi_1 = COPY(c_1); + l_2 = END(l_1); + l_3 = LOOP_BEGIN(l_2, l_9); + double lo_2 = PHI(l_3, lo_1, lo_3); + double hi_2 = PHI(l_3, hi_1, hi_3); + bool b = LT(hi_2, c_10000); + l_4 = IF(l_3, b); + l_7 = IF_TRUE(l_4); + double hi_3 = ADD(hi_2, lo_2); + double lo_3 = SUB(hi_3, lo_2); + ll = CALL/2(l_7, f, format, lo_3); + l_8 = CALL/2(ll, f, format, lo_3); + l_9 = LOOP_END(l_8, l_3); + l_5 = IF_FALSE(l_4); + l_6 = RETURN(l_5, zero); +} +--EXPECT-- +{ + uintptr_t c_1 = 0; + bool c_2 = 0; + bool c_3 = 1; + int32_t c_4 = 0; + double c_5 = 0; + double c_6 = 1; + double c_7 = 10000; + uintptr_t c_8 = func(printf); + uintptr_t c_9 = "%g\n"; + l_1 = START(l_17); + l_2 = END(l_1); + l_3 = LOOP_BEGIN(l_2, l_15); + double d_4 = PHI(l_3, c_5, d_10); + double d_5 = PHI(l_3, c_6, d_9); + bool d_6 = LT(d_5, c_7); + l_7 = IF(l_3, d_6); + l_8 = IF_TRUE(l_7); + double d_9 = ADD(d_5, d_4); + double d_10 = SUB(d_9, d_4); + l_11 = CALL/2(l_8, c_8, c_9, d_10); + l_13 = CALL/2(l_11, c_8, c_9, d_10); + l_15 = LOOP_END(l_13, l_3); + l_16 = IF_FALSE(l_7); + l_17 = RETURN(l_16, c_4); +} +{ # LIVE-RANGES (vregs_count=2) +TMP + [%d0]: [2.2-2.3) + [%d0]: [6.0-6.2) + [%x1]: [11.0-11.1) + [%x1]: [13.0-13.1) +R1 (d_4, d_10) [SPILL=0x0] + [%d0]: [3.0-6.0), DEF(4.2) + : [6.0-8.0) + [%d0]: [8.0-10.1), [10.2-11.0), USE(9.1/2)!, USE(10.1/2)!, DEF(10.2)!, USE(11.0/4, hint=%d0) + : [11.0-16.0), USE(13.0/4, hint=%d0), PHI_USE(15.2, phi=d_4/3) +R2 (d_5, d_9) [SPILL=0x8] + [%d1]: [3.0-9.1), [9.2-10.1), DEF(5.2), USE(6.1/1)!, USE(9.1/1)!, DEF(9.2)!, USE(10.1/1)! + : [10.1-16.0), PHI_USE(15.2, phi=d_5/3) +[%x0] : [11.0-11.1), [13.0-13.1), [17.0-17.1) +[%d0] : [11.0-11.1), [13.0-13.1) +[%SCRATCH] : [11.1-11.2), [13.1-13.2) +} +test: + stp x29, x30, [sp, #-0x20]! + mov x29, sp + fmov d0, xzr + str d0, [x29, #0x10] + ldr d1, .L3 + str d1, [x29, #0x18] +.L1: + ldr d0, .L4 + ldr d1, [x29, #0x18] + fcmp d0, d1 + b.ls .L2 + ldr d1, [x29, #0x18] + ldr d0, [x29, #0x10] + fadd d1, d1, d0 + str d1, [x29, #0x18] + ldr d1, [x29, #0x18] + ldr d0, [x29, #0x10] + fsub d0, d1, d0 + str d0, [x29, #0x10] + ldr d0, [x29, #0x10] + adr x0, .L5 + bl _IO_printf + adr x0, .L5 + ldr d0, [x29, #0x10] + bl _IO_printf + b .L1 +.L2: + mov w0, wzr + ldp x29, x30, [sp], #0x20 + ret +.rodata +.L3: + .db 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x3f +.L4: + .db 0x00, 0x00, 0x00, 0x00, 0x00, 0x88, 0xc3, 0x40 +.L5: + .db 0x25, 0x67, 0x0a, 0x00 + +1 +1 +1 +1 +2 +2 +3 +3 +5 +5 +8 +8 +13 +13 +21 +21 +34 +34 +55 +55 +89 +89 +144 +144 +233 +233 +377 +377 +610 +610 +987 +987 +1597 +1597 +2584 +2584 +4181 +4181 +6765 +6765 + +exit code = 0 diff --git a/tests/debug.aarch64/regset-fibi.irt b/tests/debug.aarch64/regset-fibi.irt new file mode 100644 index 0000000..d436ce7 --- /dev/null +++ b/tests/debug.aarch64/regset-fibi.irt @@ -0,0 +1,113 @@ +--TEST-- +FibI +--TARGET-- +aarch64 +--ARGS-- +--save --dump-live-ranges -S --run +--CODE-- +{ + int32_t c_0 = 0; + int32_t c_1 = 1; + int32_t c_10000 = 10000; + uintptr_t f = func(printf); + uintptr_t format = "%d\n"; + l_1 = START(l_6); + int32_t lo_1 = COPY(c_0); + int32_t hi_1 = COPY(c_1); + l_2 = END(l_1); + l_3 = LOOP_BEGIN(l_2, l_9); + int32_t lo_2 = PHI(l_3, lo_1, lo_3); + int32_t hi_2 = PHI(l_3, hi_1, hi_3); + bool b = LT(hi_2, c_10000); + l_4 = IF(l_3, b); + l_7 = IF_TRUE(l_4); + int32_t hi_3 = ADD(hi_2, lo_2); + int32_t lo_3 = SUB(hi_3, lo_2); + l_8 = CALL/2(l_7, f, format, lo_3); + l_9 = LOOP_END(l_8, l_3); + l_5 = IF_FALSE(l_4); + l_6 = RETURN(l_5, c_0); +} +--EXPECT-- +{ + uintptr_t c_1 = 0; + bool c_2 = 0; + bool c_3 = 1; + int32_t c_4 = 0; + int32_t c_5 = 1; + int32_t c_6 = 10000; + uintptr_t c_7 = func(printf); + uintptr_t c_8 = "%d\n"; + l_1 = START(l_15); + l_2 = END(l_1); + l_3 = LOOP_BEGIN(l_2, l_13); + int32_t d_4 = PHI(l_3, c_4, d_10); + int32_t d_5 = PHI(l_3, c_5, d_9); + bool d_6 = LT(d_5, c_6); + l_7 = IF(l_3, d_6); + l_8 = IF_TRUE(l_7); + int32_t d_9 = ADD(d_5, d_4); + int32_t d_10 = SUB(d_9, d_4); + l_11 = CALL/2(l_8, c_7, c_8, d_10); + l_13 = LOOP_END(l_11, l_3); + l_14 = IF_FALSE(l_7); + l_15 = RETURN(l_14, c_4); +} +{ # LIVE-RANGES (vregs_count=2) +TMP + [%w0]: [2.2-2.3) + [%w0]: [6.0-6.2) + [%x2]: [11.0-11.1) +R1 (d_4, d_10) [%w20]: [3.0-10.1), [10.2-14.0), DEF(4.2), USE(9.1/2)!, USE(10.1/2)!, DEF(10.2)!, USE(11.0/4, hint=%w1), PHI_USE(13.2, phi=d_4/3) +R2 (d_5, d_9) [%w18]: [3.0-9.1), [9.2-14.0), DEF(5.2), USE(6.1/1)!, USE(9.1/1)!, DEF(9.2)!, USE(10.1/1)!, PHI_USE(13.2, phi=d_5/3) +[%x0] : [11.0-11.1), [15.0-15.1) +[%x1] : [11.0-11.1) +[%SCRATCH] : [11.1-11.2) +} +test: + stp x29, x30, [sp, #-0x20]! + mov x29, sp + stp x19, x20, [x29, #0x10] + mov w20, wzr + movz w19, #0x1 +.L1: + movz w0, #0x2710 + cmp w19, w0 + b.ge .L2 + add w19, w19, w20 + sub w20, w19, w20 + mov w1, w20 + adr x0, .L3 + bl _IO_printf + b .L1 +.L2: + mov w0, wzr + ldp x19, x20, [x29, #0x10] + ldp x29, x30, [sp], #0x20 + ret +.rodata +.L3: + .db 0x25, 0x64, 0x0a, 0x00 + +1 +1 +2 +3 +5 +8 +13 +21 +34 +55 +89 +144 +233 +377 +610 +987 +1597 +2584 +4181 +6765 + +exit code = 0 diff --git a/tests/debug.aarch64/regset-test.irt b/tests/debug.aarch64/regset-test.irt new file mode 100644 index 0000000..1bc683d --- /dev/null +++ b/tests/debug.aarch64/regset-test.irt @@ -0,0 +1,205 @@ +--TEST-- +Test +--TARGET-- +aarch64 +--ARGS-- +--debug-regset 0x3ffffffff --save --dump-live-ranges -S +--CODE-- +{ + uintptr_t c_1 = 0; + bool c_2 = 0; + bool c_3 = 1; + double c_4 = 0.5; + double c_5 = 0; + int32_t c_6 = 0; + int32_t c_7 = 1; + double c_8 = 16; + int32_t c_9 = 1000; + l_1 = START(l_35); + double d_2 = PARAM(l_1, "x", 0); + double d_3 = PARAM(l_1, "y", 1); + double d_4 = VAR(l_1, "cr"); + double d_5 = SUB(d_3, c_4); + double d_6 = VAR(l_1, "ci"); + double d_7 = VAR(l_1, "zi"); + double d_8 = VAR(l_1, "zr"); + int32_t d_9 = VAR(l_1, "i"); + l_10 = END(l_1); + l_11 = LOOP_BEGIN(l_10, l_37); + double d_12 = PHI(l_11, c_5, d_25); + double d_13 = PHI(l_11, c_5, d_23); + int32_t d_14 = PHI(l_11, c_6, d_15); + int32_t d_15 = ADD(d_14, c_7); + double d_16 = VAR(l_11, "temp"); + double d_17 = MUL(d_13, d_12); + double d_18 = VAR(l_11, "zr2"); + double d_19 = MUL(d_13, d_13); + double d_20 = VAR(l_11, "zi2"); + double d_21 = MUL(d_12, d_12); + double d_22 = SUB(d_19, d_21); + double d_23 = ADD(d_22, d_5); + double d_24 = ADD(d_17, d_17); + double d_25 = ADD(d_24, d_2); + double d_26 = ADD(d_21, d_19); + bool d_27 = GT(d_26, c_8); + l_28 = IF(l_11, d_27); + l_29 = IF_TRUE(l_28); + l_30 = RETURN(l_29, d_15); + l_31 = IF_FALSE(l_28); + bool d_32 = GT(d_15, c_9); + l_33 = IF(l_31, d_32); + l_34 = IF_TRUE(l_33); + l_35 = RETURN(l_34, c_6, l_30); + l_36 = IF_FALSE(l_33); + l_37 = LOOP_END(l_36, l_11); +} +--EXPECT-- +{ + uintptr_t c_1 = 0; + bool c_2 = 0; + bool c_3 = 1; + double c_4 = 0.5; + double c_5 = 0; + int32_t c_6 = 0; + int32_t c_7 = 1; + double c_8 = 16; + int32_t c_9 = 1000; + l_1 = START(l_30); + double d_2 = PARAM(l_1, "x", 0); + double d_3 = PARAM(l_1, "y", 1); + double d_4 = VAR(l_1, "cr"); + double d_5 = SUB(d_3, c_4); + double d_6 = VAR(l_1, "ci"); + double d_7 = VAR(l_1, "zi"); + double d_8 = VAR(l_1, "zr"); + int32_t d_9 = VAR(l_1, "i"); + l_10 = END(l_1); + l_11 = LOOP_BEGIN(l_10, l_37); + double d_12 = PHI(l_11, c_5, d_36); + double d_13 = PHI(l_11, c_5, d_34); + int32_t d_14 = PHI(l_11, c_6, d_15); + int32_t d_15 = ADD(d_14, c_7); + double d_16 = VAR(l_11, "temp"); + double d_17 = VAR(l_11, "zr2"); + double d_18 = MUL(d_13, d_13); + double d_19 = VAR(l_11, "zi2"); + double d_20 = MUL(d_12, d_12); + double d_21 = ADD(d_20, d_18); + bool d_22 = GT(d_21, c_8); + l_23 = IF(l_11, d_22); + l_24 = IF_TRUE(l_23); + l_25 = RETURN(l_24, d_15); + l_26 = IF_FALSE(l_23); + bool d_27 = GT(d_15, c_9); + l_28 = IF(l_26, d_27); + l_29 = IF_TRUE(l_28); + l_30 = RETURN(l_29, c_6, l_25); + l_31 = IF_FALSE(l_28); + double d_32 = MUL(d_13, d_12); + double d_33 = SUB(d_18, d_20); + double d_34 = ADD(d_33, d_5); + double d_35 = ADD(d_32, d_32); + double d_36 = ADD(d_35, d_2); + l_37 = LOOP_END(l_31, l_11); +} +{ # LIVE-RANGES (vregs_count=12) +TMP + [%d0]: [5.0-5.2) + [%d1]: [10.2-10.3) + [%w0]: [10.2-10.3) + [%d1]: [22.0-22.2) +R1 (d_2) [SPILL=0x0] + [%d0]: [2.3-5.0), DEF(2.3, hint=%d0) + : [5.0-24.0), [26.0-29.0), [31.0-36.0) + [%d1]: [36.0-38.0), USE(36.1/2)! +R2 (d_3) [%d1]: [3.3-5.1), DEF(3.3, hint=%d1), USE(5.1/1)! +R3 (d_5) [SPILL=0x8] + [%d0]: [5.2-10.2), DEF(5.2)! + : [10.2-24.0), [26.0-29.0), [31.0-34.0) + [%d1]: [34.0-34.1), USE(34.1/2)! + : [34.1-38.0) +R4 (d_12, d_36) [SPILL=0x10] + [%d0]: [11.0-20.2), DEF(12.2), USE(20.1/1)!, USE(20.1/2)! + : [20.2-24.0), [26.0-29.0), [31.0-32.0) + [%d0]: [32.0-32.1), [36.2-38.0), USE(32.1/2)!, DEF(36.2)!, PHI_USE(37.2, phi=d_12/3) +R5 (d_13, d_34) [SPILL=0x18] + [%d1]: [11.0-18.2), DEF(13.2), USE(18.1/1)!, USE(18.1/2)! + : [18.2-24.0), [26.0-29.0), [31.0-32.0) + [%d1]: [32.0-32.1), [34.2-36.0), USE(32.1/1)!, DEF(34.2)! + : [36.0-37.1) + : [37.1-38.0), PHI_USE(37.2, phi=d_13/3) +R6 (d_14, d_15) [%w0]: [11.0-15.1), [15.2-25.0), [26.0-29.0), [31.0-38.0), DEF(14.2), USE(15.1/1)!, DEF(15.2)!, USE(25.0/2, hint=%w0), USE(27.1/1)!, PHI_USE(37.2, phi=d_14/3) +R7 (d_18) [SPILL=0x20] + [%d1]: [18.2-22.0), DEF(18.2)!, USE(21.1/2)! + : [22.0-24.0), [26.0-29.0), [31.0-33.0) + [%d0]: [33.0-33.1), USE(33.1/1)! +R8 (d_20) [SPILL=0x28] + [%d0]: [20.2-21.2), DEF(20.2)!, USE(21.1/1)! + : [21.2-24.0), [26.0-29.0), [31.0-33.0) + [%d1]: [33.0-33.1), USE(33.1/2)! +R9 (d_21) [%d0]: [21.2-22.1), DEF(21.2)!, USE(22.1/1)! +R10 (d_32) [SPILL=0x30] + [%d0]: [32.2-33.0), DEF(32.2)! + : [33.0-35.0) + [%d0]: [35.0-35.1), USE(35.1/1)!, USE(35.1/2)! +R11 (d_33) [%d0]: [33.2-34.1), DEF(33.2)!, USE(34.1/1)! +R12 (d_35) [%d0]: [35.2-36.1), DEF(35.2)!, USE(36.1/1)! +[%x0] : [25.0-25.1), [30.0-30.1) +[%d0] : [1.0-2.3) +[%d1] : [1.0-3.3) +} +test: + sub sp, sp, #0x38 + str d0, [sp] + ldr d0, .L4 + fsub d0, d1, d0 + str d0, [sp, #8] + fmov d0, xzr + str d0, [sp, #0x10] + fmov d1, xzr + str d1, [sp, #0x18] + mov w0, wzr +.L1: + add w0, w0, #1 + ldr d1, [sp, #0x18] + fmul d1, d1, d1 + str d1, [sp, #0x20] + ldr d0, [sp, #0x10] + fmul d0, d0, d0 + str d0, [sp, #0x28] + ldr d0, [sp, #0x28] + ldr d1, [sp, #0x20] + fadd d0, d0, d1 + ldr d1, .L5 + fcmp d0, d1 + b.gt .L2 + cmp w0, #0x3e8 + b.gt .L3 + ldr d1, [sp, #0x18] + ldr d0, [sp, #0x10] + fmul d0, d1, d0 + str d0, [sp, #0x30] + ldr d0, [sp, #0x20] + ldr d1, [sp, #0x28] + fsub d0, d0, d1 + ldr d1, [sp, #8] + fadd d1, d0, d1 + str d1, [sp, #0x18] + ldr d0, [sp, #0x30] + fadd d0, d0, d0 + ldr d1, [sp] + fadd d0, d0, d1 + str d0, [sp, #0x10] + b .L1 +.L2: + add sp, sp, #0x38 + ret +.L3: + mov w0, wzr + add sp, sp, #0x38 + ret +.rodata +.L4: + .db 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x3f +.L5: + .db 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x40 diff --git a/tests/debug.aarch64/sccp_001.irt b/tests/debug.aarch64/sccp_001.irt new file mode 100644 index 0000000..3649e10 --- /dev/null +++ b/tests/debug.aarch64/sccp_001.irt @@ -0,0 +1,19 @@ +--TEST-- +SCCP 001 +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + int64_t i_1 = 10; + int64_t i_4 = 4; + l_1 = START(l_2); + int64_t z1 = BSWAP(i_1); + l_2 = RETURN(l_1, z1); +} +--EXPECT-- +test: + movz x0, #0xa + rev x0, x0 + ret diff --git a/tests/debug.aarch64/sccp_002.irt b/tests/debug.aarch64/sccp_002.irt new file mode 100644 index 0000000..5a5483f --- /dev/null +++ b/tests/debug.aarch64/sccp_002.irt @@ -0,0 +1,81 @@ +--TEST-- +SCCP 002 +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + uintptr_t c_1 = 0; + bool c_2 = 0; + bool c_3 = 1; + int32_t c_4 = 1; + int32_t c_5 = 2; + int32_t c_6 = 3; + int32_t c_7 = 4; + l_1 = START(l_38); + int32_t d_2 = PARAM(l_1, "z", 0); + bool d_3 = PARAM(l_1, "cond", 1); + l_4 = SWITCH(l_1, d_2); + l_5 = CASE_VAL(l_4, c_4); + l_6 = END(l_5); + l_7 = CASE_VAL(l_4, c_5); + l_8 = END(l_7); + l_9 = CASE_VAL(l_4, c_6); + l_10 = END(l_9); + l_11 = CASE_DEFAULT(l_4); + l_12 = END(l_11); + l_13 = LOOP_BEGIN(l_12, l_25); + int32_t d_14 = PHI(l_13, c_4, d_22); + bool d_15 = NE(d_14, c_4); + l_16 = IF(l_13, d_15); + l_17 = IF_TRUE(l_16); + l_18 = END(l_17); + l_19 = IF_FALSE(l_16); + l_20 = END(l_19); + l_21 = MERGE(l_18, l_20); + int32_t d_22 = PHI(l_21, c_5, d_14); + l_23 = IF(l_21, d_3); + l_24 = IF_TRUE(l_23); + l_25 = LOOP_END(l_24, l_13); + l_26 = IF_FALSE(l_23); + bool d_28 = EQ(d_22, c_4); + l_29 = IF(l_26, d_28); + l_30 = IF_TRUE(l_29); + l_31 = RETURN(l_30, d_22); + l_32 = IF_FALSE(l_29); + l_33 = END(l_32); + l_34 = MERGE/4(l_6, l_8, l_10, l_33); + int32_t d_36 = PHI/4(l_34, c_4, c_5, c_6, c_7); + l_38 = RETURN(l_34, d_36, l_31); +} +--EXPECT-- +test: + cmp w0, #3 + b.gt .L5 + subs w3, w0, #1 + b.lt .L5 + adr x2, .L6 + ldr x2, [x2, x3, lsl #3] + br x2 +.L1: + movz w0, #0x1 +.L2: + ret +.L3: + movz w0, #0x2 + b .L2 +.L4: + movz w0, #0x3 + b .L2 +.L5: + cmp w1, #0 + b.ne .L5 + movz w0, #0x1 + ret +.rodata +.align 8 +.L6: + .qword .L1 + .qword .L3 + .qword .L4 diff --git a/tests/debug.aarch64/switch_001.irt b/tests/debug.aarch64/switch_001.irt new file mode 100644 index 0000000..dd00635 --- /dev/null +++ b/tests/debug.aarch64/switch_001.irt @@ -0,0 +1,62 @@ +--TEST-- +SWITCH 001 +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + uintptr_t c_1 = 0; + bool c_2 = 0; + bool c_3 = 1; + int32_t c_4 = 1; + int32_t c_5 = 2; + int32_t c_6 = 3; + int32_t c_7 = 4; + l_1 = START(l_16); + int32_t d_2 = PARAM(l_1, "z", 0); + l_4 = SWITCH(l_1, d_2); + l_5 = CASE_VAL(l_4, c_4); + int32_t x_1 = COPY(c_4); + l_6 = END(l_5); + l_7 = CASE_VAL(l_4, c_5); + int32_t x_2 = COPY(c_5); + l_8 = END(l_7); + l_9 = CASE_VAL(l_4, c_6); + int32_t x_3 = COPY(c_6); + l_10 = END(l_9); + l_11 = CASE_DEFAULT(l_4); + int32_t x_4 = COPY(c_7); + l_12 = END(l_11); + l_13 = MERGE/4(l_6, l_8, l_10, l_12); + int32_t ret = PHI/4(l_13, x_1, x_2, x_3, x_4); + l_16 = RETURN(l_13, ret); +} +--EXPECT-- +test: + cmp w0, #3 + b.gt .L5 + subs w2, w0, #1 + b.lt .L5 + adr x1, .L6 + ldr x1, [x1, x2, lsl #3] + br x1 +.L1: + movz w0, #0x1 +.L2: + ret +.L3: + movz w0, #0x2 + b .L2 +.L4: + movz w0, #0x3 + b .L2 +.L5: + movz w0, #0x4 + b .L2 +.rodata +.align 8 +.L6: + .qword .L1 + .qword .L3 + .qword .L4 diff --git a/tests/debug.aarch64/switch_002.irt b/tests/debug.aarch64/switch_002.irt new file mode 100644 index 0000000..a5c0160 --- /dev/null +++ b/tests/debug.aarch64/switch_002.irt @@ -0,0 +1,38 @@ +--TEST-- +SWITCH 002 +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + uintptr_t c_1 = 0; + bool c_2 = 0; + bool c_3 = 1; + int32_t c_4 = 1; + int32_t c_5 = 2; + int32_t c_6 = 3; + int32_t c_7 = 4; + l_1 = START(l_16); + int32_t d_2 = COPY(c_7); + l_4 = SWITCH(l_1, d_2); + l_5 = CASE_VAL(l_4, c_4); + int32_t x_1 = COPY(c_4); + l_6 = END(l_5); + l_7 = CASE_VAL(l_4, c_5); + int32_t x_2 = COPY(c_5); + l_8 = END(l_7); + l_9 = CASE_VAL(l_4, c_6); + int32_t x_3 = COPY(c_6); + l_10 = END(l_9); + l_11 = CASE_DEFAULT(l_4); + int32_t x_4 = COPY(c_7); + l_12 = END(l_11); + l_13 = MERGE/4(l_6, l_8, l_10, l_12); + int32_t ret = PHI/4(l_13, x_1, x_2, x_3, x_4); + l_16 = RETURN(l_13, ret); +} +--EXPECT-- +test: + movz w0, #0x4 + ret diff --git a/tests/debug.aarch64/switch_003.irt b/tests/debug.aarch64/switch_003.irt new file mode 100644 index 0000000..6c67cc9 --- /dev/null +++ b/tests/debug.aarch64/switch_003.irt @@ -0,0 +1,64 @@ +--TEST-- +SWITCH 003 +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + uintptr_t c_1 = 0; + bool c_2 = 0; + bool c_3 = 1; + int64_t c_4 = 8589934592; + int64_t c_5 = 8589934593; + int64_t c_6 = 8589935594; + int64_t c_7 = 8589934595; + l_1 = START(l_16); + int64_t d_2 = PARAM(l_1, "z", 0); + l_4 = SWITCH(l_1, d_2); + l_5 = CASE_VAL(l_4, c_4); + int64_t x_1 = COPY(c_4); + l_6 = END(l_5); + l_7 = CASE_VAL(l_4, c_5); + int64_t x_2 = COPY(c_5); + l_8 = END(l_7); + l_9 = CASE_VAL(l_4, c_6); + int64_t x_3 = COPY(c_6); + l_10 = END(l_9); + l_11 = CASE_DEFAULT(l_4); + int64_t x_4 = COPY(c_7); + l_12 = END(l_11); + l_13 = MERGE/4(l_6, l_8, l_10, l_12); + int64_t ret = PHI/4(l_13, x_1, x_2, x_3, x_4); + l_16 = RETURN(l_13, ret); +} +--EXPECT-- +test: + movz x1, #0x2, lsl #32 + cmp x0, x1 + b.eq .L1 + movz x1, #0x1 + movk x1, #0x2, lsl #32 + cmp x0, x1 + b.eq .L3 + movz x1, #0x3ea + movk x1, #0x2, lsl #32 + cmp x0, x1 + b.eq .L4 + b .L5 +.L1: + movz x0, #0x2, lsl #32 +.L2: + ret +.L3: + movz x0, #0x1 + movk x0, #0x2, lsl #32 + b .L2 +.L4: + movz x0, #0x3ea + movk x0, #0x2, lsl #32 + b .L2 +.L5: + movz x0, #0x3 + movk x0, #0x2, lsl #32 + b .L2 diff --git a/tests/debug.aarch64/tailcall_001.irt b/tests/debug.aarch64/tailcall_001.irt new file mode 100644 index 0000000..3e72b6a --- /dev/null +++ b/tests/debug.aarch64/tailcall_001.irt @@ -0,0 +1,31 @@ +--TEST-- +Simple CALL +--TARGET-- +aarch64 +--ARGS-- +-S --run +--CODE-- +{ + uintptr_t c_1 = 0; + bool c_2 = 0; + bool c_3 = 1; + int32_t c_4 = 42; + uintptr_t c_5 = func(printf); + uintptr_t c_6 = "hello %d!\n"; + l_1 = START(l_4); + char d_2, l_2 = TAILCALL/2(l_1, c_5, c_6, c_4); + l_4 = UNREACHABLE(l_2, d_2); +} +--EXPECT-- +test: + adr x0, .L1 + movz w1, #0x2a + b _IO_printf +.rodata + .db 0x1f, 0x20, 0x03, 0xd5 +.L1: + .db 0x68, 0x65, 0x6c, 0x6c, 0x6f, 0x20, 0x25, 0x64, 0x21, 0x0a, 0x00, 0x00 + +hello 42! + +exit code = 10 diff --git a/tests/debug.aarch64/tailcall_002.irt b/tests/debug.aarch64/tailcall_002.irt new file mode 100644 index 0000000..a263904 --- /dev/null +++ b/tests/debug.aarch64/tailcall_002.irt @@ -0,0 +1,24 @@ +--TEST-- +Indirect Tail CALL +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + uintptr_t c_6 = "hello %d!\n"; + l_1 = START(l_4); + uintptr_t f = PARAM(l_1, "f", 1); + int32_t p = PARAM(l_1, "p", 2); + int32_t d_2, l_2 = TAILCALL/2(l_1, f, c_6, p); + l_4 = UNREACHABLE(l_2, d_2); +} +--EXPECT-- +test: + mov x2, x0 + adr x0, .L1 + br x2 +.rodata + .db 0x1f, 0x20, 0x03, 0xd5 +.L1: + .db 0x68, 0x65, 0x6c, 0x6c, 0x6f, 0x20, 0x25, 0x64, 0x21, 0x0a, 0x00, 0x00 diff --git a/tests/debug.aarch64/test-O0.irt b/tests/debug.aarch64/test-O0.irt new file mode 100644 index 0000000..14a6812 --- /dev/null +++ b/tests/debug.aarch64/test-O0.irt @@ -0,0 +1,131 @@ +--TEST-- +Mandelbrot Test (-O0) +--TARGET-- +aarch64 +--ARGS-- +-S -O0 +--CODE-- +{ + uintptr_t c_1 = 0; + bool c_2 = 0; + bool c_3 = 1; + double c_4 = 0.5; + double c_5 = 0; + int32_t c_6 = 0; + int32_t c_7 = 1; + double c_8 = 16; + int32_t c_9 = 1000; + l_1 = START(l_35); + double d_2 = PARAM(l_1, "x", 0); + double d_3 = PARAM(l_1, "y", 1); + double d_4 = VAR(l_1, "cr"); + double d_5 = SUB(d_3, c_4); + double d_6 = VAR(l_1, "ci"); + double d_7 = VAR(l_1, "zi"); + double d_8 = VAR(l_1, "zr"); + int32_t d_9 = VAR(l_1, "i"); + l_10 = END(l_1); + l_11 = LOOP_BEGIN(l_10, l_37); + double d_12 = PHI(l_11, c_5, d_25); + double d_13 = PHI(l_11, c_5, d_23); + int32_t d_14 = PHI(l_11, c_6, d_15); + int32_t d_15 = ADD(d_14, c_7); + double d_16 = VAR(l_11, "temp"); + double d_17 = MUL(d_13, d_12); + double d_18 = VAR(l_11, "zr2"); + double d_19 = MUL(d_13, d_13); + double d_20 = VAR(l_11, "zi2"); + double d_21 = MUL(d_12, d_12); + double d_22 = SUB(d_19, d_21); + double d_23 = ADD(d_22, d_5); + double d_24 = ADD(d_17, d_17); + double d_25 = ADD(d_24, d_2); + double d_26 = ADD(d_21, d_19); + bool d_27 = GT(d_26, c_8); + l_28 = IF(l_11, d_27); + l_29 = IF_TRUE(l_28); + l_30 = RETURN(l_29, d_15); + l_31 = IF_FALSE(l_28); + bool d_32 = GT(d_15, c_9); + l_33 = IF(l_31, d_32); + l_34 = IF_TRUE(l_33); + l_35 = RETURN(l_34, c_6, l_30); + l_36 = IF_FALSE(l_33); + l_37 = LOOP_END(l_36, l_11); +} +--EXPECT-- +test: + sub sp, sp, #0x70 + str d0, [sp] + str d1, [sp, #8] + ldr d1, [sp, #8] + ldr d2, .L4 + fsub d0, d1, d2 + str d0, [sp, #0x10] + fmov d0, xzr + str d0, [sp, #0x18] + fmov d0, xzr + str d0, [sp, #0x20] + mov w0, wzr + str w0, [sp, #0x28] +.L1: + ldr w1, [sp, #0x28] + add w0, w1, #1 + str w0, [sp, #0x2c] + ldr d1, [sp, #0x20] + ldr d2, [sp, #0x18] + fmul d0, d1, d2 + str d0, [sp, #0x30] + ldr d1, [sp, #0x20] + fmul d0, d1, d1 + str d0, [sp, #0x38] + ldr d1, [sp, #0x18] + fmul d0, d1, d1 + str d0, [sp, #0x40] + ldr d1, [sp, #0x38] + ldr d2, [sp, #0x40] + fsub d0, d1, d2 + str d0, [sp, #0x48] + ldr d1, [sp, #0x48] + ldr d2, [sp, #0x10] + fadd d0, d1, d2 + str d0, [sp, #0x50] + ldr d1, [sp, #0x30] + fadd d0, d1, d1 + str d0, [sp, #0x58] + ldr d1, [sp, #0x58] + ldr d2, [sp] + fadd d0, d1, d2 + str d0, [sp, #0x60] + ldr d1, [sp, #0x40] + ldr d2, [sp, #0x38] + fadd d0, d1, d2 + str d0, [sp, #0x68] + ldr d0, [sp, #0x68] + ldr d1, .L5 + fcmp d0, d1 + b.ls .L2 + ldr w0, [sp, #0x2c] + add sp, sp, #0x70 + ret +.L2: + ldr w0, [sp, #0x2c] + cmp w0, #0x3e8 + b.le .L3 + mov w0, wzr + add sp, sp, #0x70 + ret +.L3: + ldr d0, [sp, #0x60] + str d0, [sp, #0x18] + ldr d0, [sp, #0x50] + str d0, [sp, #0x20] + ldr w0, [sp, #0x2c] + str w0, [sp, #0x28] + b .L1 +.rodata + .db 0x1f, 0x20, 0x03, 0xd5 +.L4: + .db 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x3f +.L5: + .db 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x40 diff --git a/tests/debug.aarch64/test.irt b/tests/debug.aarch64/test.irt new file mode 100644 index 0000000..7fac22f --- /dev/null +++ b/tests/debug.aarch64/test.irt @@ -0,0 +1,89 @@ +--TEST-- +Mandelbrot Test +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + uintptr_t c_1 = 0; + bool c_2 = 0; + bool c_3 = 1; + double c_4 = 0.5; + double c_5 = 0; + int32_t c_6 = 0; + int32_t c_7 = 1; + double c_8 = 16; + int32_t c_9 = 1000; + l_1 = START(l_35); + double d_2 = PARAM(l_1, "x", 0); + double d_3 = PARAM(l_1, "y", 1); + double d_4 = VAR(l_1, "cr"); + double d_5 = SUB(d_3, c_4); + double d_6 = VAR(l_1, "ci"); + double d_7 = VAR(l_1, "zi"); + double d_8 = VAR(l_1, "zr"); + int32_t d_9 = VAR(l_1, "i"); + l_10 = END(l_1); + l_11 = LOOP_BEGIN(l_10, l_37); + double d_12 = PHI(l_11, c_5, d_25); + double d_13 = PHI(l_11, c_5, d_23); + int32_t d_14 = PHI(l_11, c_6, d_15); + int32_t d_15 = ADD(d_14, c_7); + double d_16 = VAR(l_11, "temp"); + double d_17 = MUL(d_13, d_12); + double d_18 = VAR(l_11, "zr2"); + double d_19 = MUL(d_13, d_13); + double d_20 = VAR(l_11, "zi2"); + double d_21 = MUL(d_12, d_12); + double d_22 = SUB(d_19, d_21); + double d_23 = ADD(d_22, d_5); + double d_24 = ADD(d_17, d_17); + double d_25 = ADD(d_24, d_2); + double d_26 = ADD(d_21, d_19); + bool d_27 = GT(d_26, c_8); + l_28 = IF(l_11, d_27); + l_29 = IF_TRUE(l_28); + l_30 = RETURN(l_29, d_15); + l_31 = IF_FALSE(l_28); + bool d_32 = GT(d_15, c_9); + l_33 = IF(l_31, d_32); + l_34 = IF_TRUE(l_33); + l_35 = RETURN(l_34, c_6, l_30); + l_36 = IF_FALSE(l_33); + l_37 = LOOP_END(l_36, l_11); +} +--EXPECT-- +test: + ldr d2, .L4 + fsub d1, d1, d2 + fmov d3, xzr + fmov d2, xzr + mov w0, wzr +.L1: + add w0, w0, #1 + fmul d4, d2, d2 + fmul d5, d3, d3 + fadd d6, d5, d4 + ldr d7, .L5 + fcmp d6, d7 + b.gt .L2 + cmp w0, #0x3e8 + b.gt .L3 + fmul d3, d2, d3 + fsub d2, d4, d5 + fadd d2, d2, d1 + fadd d3, d3, d3 + fadd d3, d3, d0 + b .L1 +.L2: + ret +.L3: + mov w0, wzr + ret +.rodata + .db 0x1f, 0x20, 0x03, 0xd5 +.L4: + .db 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x3f +.L5: + .db 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x40 diff --git a/tests/debug.aarch64/test_mem.irt b/tests/debug.aarch64/test_mem.irt new file mode 100644 index 0000000..e97e405 --- /dev/null +++ b/tests/debug.aarch64/test_mem.irt @@ -0,0 +1,141 @@ +--TEST-- +Mandelbrot Test (mem) +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + uintptr_t c_1 = 0; + bool c_2 = 0; + bool c_3 = 1; + double c_4 = 0.5; + double c_5 = 0; + int32_t c_6 = 0; + int32_t c_7 = 1; + uint32_t c_size = 4; + double c_8 = 16; + int32_t c_9 = 1000; + l_1 = START(l_35); + double d_2 = PARAM(l_1, "x", 0); + double d_3 = PARAM(l_1, "y", 1); + double cr = VAR(l_1, "cr"); + double d_5 = SUB(d_3, c_4); + l_1_1 = VSTORE(l_1, cr, d_5); + double ci = VAR(l_1, "ci"); + l_1_2 = VSTORE(l_1_1, ci, d_2); + double zi = VAR(l_1, "zi"); + l_1_3 = VSTORE(l_1_2, zi, c_5); + double zr = VAR(l_1, "zr"); + l_1_4 = VSTORE(l_1_3, zr, c_5); + uintptr_t i, l_1_5 = ALLOCA(l_1_4, c_size); + l_1_6 = STORE(l_1_5, i, c_6); + l_10 = END(l_1_6); + l_11 = LOOP_BEGIN(l_10, l_37); + + int32_t d_14, l_11_1 = LOAD(l_11, i); + int32_t d_15 = ADD(d_14, c_7); + l_11_2 = STORE(l_11_1, i, d_15); + + double temp = VAR(l_11, "temp"); + double zr_1, l_11_3 = VLOAD(l_11_2, zr); + double zi_1, l_11_4 = VLOAD(l_11_3, zi); + double d_17 = MUL(zr_1, zi_1); + l_11_5 = VSTORE(l_11_4, temp, d_17); + + double zr2 = VAR(l_11, "zr2"); + double d_19 = MUL(zr_1, zr_1); + l_11_6 = VSTORE(l_11_5, zr2, d_19); + + double zi2 = VAR(l_11, "zi2"); + double d_21 = MUL(zi_1, zi_1); + l_11_7 = VSTORE(l_11_6, zi2, d_21); + double zr2_1, l_11_8 = VLOAD(l_11_7, zr2); + double zi2_1, l_11_9 = VLOAD(l_11_8, zi2); + double d_22 = SUB(zr2_1, zi2_1); + double cr2_1, l_11_10 = VLOAD(l_11_9, cr); + double d_23 = ADD(d_22, cr2_1); + l_11_11 = VSTORE(l_11_10, zr, d_23); + double temp_1, l_11_12 = VLOAD(l_11_11, temp); + double d_24 = ADD(temp_1, temp_1); + double ci_1, l_11_13 = VLOAD(l_11_12, ci); + double d_25 = ADD(d_24, ci_1); + l_11_14 = VSTORE(l_11_13, zi, d_25); + double zi2_2, l_11_15 = VLOAD(l_11_14, zi2); + double zr2_2, l_11_16 = VLOAD(l_11_15, zr2); + double d_26 = ADD(zi2_2, zr2_2); + bool d_27 = GT(d_26, c_8); + l_28 = IF(l_11_16, d_27); + l_29 = IF_TRUE(l_28); + int32_t d_15_1, l_29_1 = LOAD(l_29, i); + l_30 = RETURN(l_29_1, d_15_1); + l_31 = IF_FALSE(l_28); + int32_t d_15_2, l_31_1 = LOAD(l_31, i); + bool d_32 = GT(d_15_2, c_9); + l_33 = IF(l_31_1, d_32); + l_34 = IF_TRUE(l_33); + l_35 = RETURN(l_34, c_6, l_30); + l_36 = IF_FALSE(l_33); + l_37 = LOOP_END(l_36, l_11); +} +--EXPECT-- +test: + stp x29, x30, [sp, #-0x48]! + mov x29, sp + ldr d2, .L3 + fsub d1, d1, d2 + str d1, [x29, #0x10] + str d0, [x29, #0x18] + fmov d0, xzr + str d0, [x29, #0x20] + fmov d0, xzr + str d0, [x29, #0x28] + sub sp, sp, #8 + mov x0, sp + str wzr, [x0] +.L1: + ldr w1, [x0] + add w1, w1, #1 + str w1, [x0] + ldr d0, [x29, #0x28] + ldr d1, [x29, #0x20] + fmul d2, d1, d0 + str d2, [x29, #0x30] + fmul d0, d0, d0 + str d0, [x29, #0x38] + fmul d0, d1, d1 + str d0, [x29, #0x40] + ldr d0, [x29, #0x38] + ldr d1, [x29, #0x40] + fsub d0, d0, d1 + ldr d1, [x29, #0x10] + fadd d0, d1, d0 + str d0, [x29, #0x28] + ldr d0, [x29, #0x30] + fadd d0, d0, d0 + ldr d1, [x29, #0x18] + fadd d0, d1, d0 + str d0, [x29, #0x20] + ldr d0, [x29, #0x40] + ldr d1, [x29, #0x38] + fadd d0, d1, d0 + ldr d1, .L4 + fcmp d0, d1 + b.gt .L2 + ldr w1, [x0] + cmp w1, #0x3e8 + b.le .L1 + mov w0, wzr + mov sp, x29 + ldp x29, x30, [sp], #0x48 + ret +.L2: + ldr w0, [x0] + mov sp, x29 + ldp x29, x30, [sp], #0x48 + ret +.rodata +.L3: + .db 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x3f +.L4: + .db 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x40 diff --git a/tests/debug.aarch64/test_var-O0.irt b/tests/debug.aarch64/test_var-O0.irt new file mode 100644 index 0000000..1d67d17 --- /dev/null +++ b/tests/debug.aarch64/test_var-O0.irt @@ -0,0 +1,144 @@ +--TEST-- +Mandelbrot Test (var) +--TARGET-- +aarch64 +--ARGS-- +-S -O0 +--CODE-- +{ + uintptr_t c_1 = 0; + bool c_2 = 0; + bool c_3 = 1; + double c_4 = 0.5; + double c_5 = 0; + int32_t c_6 = 0; + int32_t c_7 = 1; + double c_8 = 16; + int32_t c_9 = 1000; + l_1 = START(l_35); + double d_2 = PARAM(l_1, "x", 0); + double d_3 = PARAM(l_1, "y", 1); + double cr = VAR(l_1, "cr"); + double d_5 = SUB(d_3, c_4); + l_1_1 = VSTORE(l_1, cr, d_5); + double ci = VAR(l_1, "ci"); + l_1_2 = VSTORE(l_1_1, ci, d_2); + double zi = VAR(l_1, "zi"); + l_1_3 = VSTORE(l_1_2, zi, c_5); + double zr = VAR(l_1, "zr"); + l_1_4 = VSTORE(l_1_3, zr, c_5); + int32_t i = VAR(l_1, "i"); + l_1_5 = VSTORE(l_1_4, i, c_6); + l_10 = END(l_1_5); + l_11 = LOOP_BEGIN(l_10, l_37); + int32_t d_14, l_11_1 = VLOAD(l_11, i); + int32_t d_15 = ADD(d_14, c_7); + l_11_2 = VSTORE(l_11_1, i, d_15); + double temp = VAR(l_11, "temp"); + double zr_1, l_11_3 = VLOAD(l_11_2, zr); + double zi_1, l_11_4 = VLOAD(l_11_3, zi); + double d_17 = MUL(zr_1, zi_1); + l_11_5 = VSTORE(l_11_4, temp, d_17); + double zr2 = VAR(l_11, "zr2"); + double d_19 = MUL(zr_1, zr_1); + l_11_6 = VSTORE(l_11_5, zr2, d_19); + double zi2 = VAR(l_11, "zi2"); + double d_21 = MUL(zi_1, zi_1); + l_11_7 = VSTORE(l_11_6, zi2, d_21); + double zr2_1, l_11_8 = VLOAD(l_11_7, zr2); + double zi2_1, l_11_9 = VLOAD(l_11_8, zi2); + double d_22 = SUB(zr2_1, zi2_1); + double cr2_1, l_11_10 = VLOAD(l_11_9, cr); + double d_23 = ADD(d_22, cr2_1); + l_11_11 = VSTORE(l_11_10, zr, d_23); + double temp_1, l_11_12 = VLOAD(l_11_11, temp); + double d_24 = ADD(temp_1, temp_1); + double ci_1, l_11_13 = VLOAD(l_11_12, ci); + double d_25 = ADD(d_24, ci_1); + l_11_14 = VSTORE(l_11_13, zi, d_25); + double zi2_2, l_11_15 = VLOAD(l_11_14, zi2); + double zr2_2, l_11_16 = VLOAD(l_11_15, zr2); + double d_26 = ADD(zi2_2, zr2_2); + bool d_27 = GT(d_26, c_8); + l_28 = IF(l_11_16, d_27); + l_29 = IF_TRUE(l_28); + int32_t d_15_1, l_29_1 = VLOAD(l_29, i); + l_30 = RETURN(l_29_1, d_15_1); + l_31 = IF_FALSE(l_28); + int32_t d_15_2, l_31_1 = VLOAD(l_31, i); + bool d_32 = GT(d_15_2, c_9); + l_33 = IF(l_31_1, d_32); + l_34 = IF_TRUE(l_33); + l_35 = RETURN(l_34, c_6, l_30); + l_36 = IF_FALSE(l_33); + l_37 = LOOP_END(l_36, l_11); +} +--EXPECT-- +test: + sub sp, sp, #0x68 + str d0, [sp] + str d1, [sp, #8] + ldr d1, [sp, #8] + ldr d2, .L3 + fsub d0, d1, d2 + str d0, [sp, #0x10] + ldr d0, [sp] + str d0, [sp, #0x18] + fmov d0, xzr + str d0, [sp, #0x20] + fmov d0, xzr + str d0, [sp, #0x28] + mov w0, wzr + str w0, [sp, #0x30] +.L1: + ldr w1, [sp, #0x30] + add w0, w1, #1 + str w0, [sp, #0x30] + ldr d1, [sp, #0x28] + ldr d2, [sp, #0x20] + fmul d0, d1, d2 + str d0, [sp, #0x38] + ldr d1, [sp, #0x28] + fmul d0, d1, d1 + str d0, [sp, #0x40] + ldr d1, [sp, #0x20] + fmul d0, d1, d1 + str d0, [sp, #0x48] + ldr d1, [sp, #0x40] + ldr d2, [sp, #0x48] + fsub d0, d1, d2 + str d0, [sp, #0x50] + ldr d1, [sp, #0x50] + ldr d2, [sp, #0x10] + fadd d0, d1, d2 + str d0, [sp, #0x28] + ldr d1, [sp, #0x38] + fadd d0, d1, d1 + str d0, [sp, #0x58] + ldr d1, [sp, #0x58] + ldr d2, [sp, #0x18] + fadd d0, d1, d2 + str d0, [sp, #0x20] + ldr d1, [sp, #0x48] + ldr d2, [sp, #0x40] + fadd d0, d1, d2 + str d0, [sp, #0x60] + ldr d0, [sp, #0x60] + ldr d1, .L4 + fcmp d0, d1 + b.ls .L2 + ldr w0, [sp, #0x30] + add sp, sp, #0x68 + ret +.L2: + ldr w0, [sp, #0x30] + cmp w0, #0x3e8 + b.le .L1 + mov w0, wzr + add sp, sp, #0x68 + ret +.rodata +.L3: + .db 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x3f +.L4: + .db 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x40 diff --git a/tests/debug.aarch64/test_var.irt b/tests/debug.aarch64/test_var.irt new file mode 100644 index 0000000..2edc495 --- /dev/null +++ b/tests/debug.aarch64/test_var.irt @@ -0,0 +1,132 @@ +--TEST-- +Mandelbrot Test (var) +--TARGET-- +aarch64 +--ARGS-- +-S +--CODE-- +{ + uintptr_t c_1 = 0; + bool c_2 = 0; + bool c_3 = 1; + double c_4 = 0.5; + double c_5 = 0; + int32_t c_6 = 0; + int32_t c_7 = 1; + double c_8 = 16; + int32_t c_9 = 1000; + l_1 = START(l_35); + double d_2 = PARAM(l_1, "x", 0); + double d_3 = PARAM(l_1, "y", 1); + double cr = VAR(l_1, "cr"); + double d_5 = SUB(d_3, c_4); + l_1_1 = VSTORE(l_1, cr, d_5); + double ci = VAR(l_1, "ci"); + l_1_2 = VSTORE(l_1_1, ci, d_2); + double zi = VAR(l_1, "zi"); + l_1_3 = VSTORE(l_1_2, zi, c_5); + double zr = VAR(l_1, "zr"); + l_1_4 = VSTORE(l_1_3, zr, c_5); + int32_t i = VAR(l_1, "i"); + l_1_5 = VSTORE(l_1_4, i, c_6); + l_10 = END(l_1_5); + l_11 = LOOP_BEGIN(l_10, l_37); + int32_t d_14, l_11_1 = VLOAD(l_11, i); + int32_t d_15 = ADD(d_14, c_7); + l_11_2 = VSTORE(l_11_1, i, d_15); + double temp = VAR(l_11, "temp"); + double zr_1, l_11_3 = VLOAD(l_11_2, zr); + double zi_1, l_11_4 = VLOAD(l_11_3, zi); + double d_17 = MUL(zr_1, zi_1); + l_11_5 = VSTORE(l_11_4, temp, d_17); + double zr2 = VAR(l_11, "zr2"); + double d_19 = MUL(zr_1, zr_1); + l_11_6 = VSTORE(l_11_5, zr2, d_19); + double zi2 = VAR(l_11, "zi2"); + double d_21 = MUL(zi_1, zi_1); + l_11_7 = VSTORE(l_11_6, zi2, d_21); + double zr2_1, l_11_8 = VLOAD(l_11_7, zr2); + double zi2_1, l_11_9 = VLOAD(l_11_8, zi2); + double d_22 = SUB(zr2_1, zi2_1); + double cr2_1, l_11_10 = VLOAD(l_11_9, cr); + double d_23 = ADD(d_22, cr2_1); + l_11_11 = VSTORE(l_11_10, zr, d_23); + double temp_1, l_11_12 = VLOAD(l_11_11, temp); + double d_24 = ADD(temp_1, temp_1); + double ci_1, l_11_13 = VLOAD(l_11_12, ci); + double d_25 = ADD(d_24, ci_1); + l_11_14 = VSTORE(l_11_13, zi, d_25); + double zi2_2, l_11_15 = VLOAD(l_11_14, zi2); + double zr2_2, l_11_16 = VLOAD(l_11_15, zr2); + double d_26 = ADD(zi2_2, zr2_2); + bool d_27 = GT(d_26, c_8); + l_28 = IF(l_11_16, d_27); + l_29 = IF_TRUE(l_28); + int32_t d_15_1, l_29_1 = VLOAD(l_29, i); + l_30 = RETURN(l_29_1, d_15_1); + l_31 = IF_FALSE(l_28); + int32_t d_15_2, l_31_1 = VLOAD(l_31, i); + bool d_32 = GT(d_15_2, c_9); + l_33 = IF(l_31_1, d_32); + l_34 = IF_TRUE(l_33); + l_35 = RETURN(l_34, c_6, l_30); + l_36 = IF_FALSE(l_33); + l_37 = LOOP_END(l_36, l_11); +} +--EXPECT-- +test: + sub sp, sp, #0x40 + ldr d2, .L3 + fsub d1, d1, d2 + str d1, [sp] + str d0, [sp, #8] + fmov d0, xzr + str d0, [sp, #0x10] + fmov d0, xzr + str d0, [sp, #0x18] + mov w0, wzr + str w0, [sp, #0x20] +.L1: + ldr w0, [sp, #0x20] + add w0, w0, #1 + str w0, [sp, #0x20] + ldr d0, [sp, #0x18] + ldr d1, [sp, #0x10] + fmul d2, d1, d0 + str d2, [sp, #0x28] + fmul d0, d0, d0 + str d0, [sp, #0x30] + fmul d0, d1, d1 + str d0, [sp, #0x38] + ldr d0, [sp, #0x30] + ldr d1, [sp, #0x38] + fsub d0, d0, d1 + ldr d1, [sp] + fadd d0, d1, d0 + str d0, [sp, #0x18] + ldr d0, [sp, #0x28] + fadd d0, d0, d0 + ldr d1, [sp, #8] + fadd d0, d1, d0 + str d0, [sp, #0x10] + ldr d0, [sp, #0x38] + ldr d1, [sp, #0x30] + fadd d0, d1, d0 + ldr d1, .L4 + fcmp d0, d1 + b.gt .L2 + ldr w0, [sp, #0x20] + cmp w0, #0x3e8 + b.le .L1 + mov w0, wzr + add sp, sp, #0x40 + ret +.L2: + ldr w0, [sp, #0x20] + add sp, sp, #0x40 + ret +.rodata +.L3: + .db 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x3f +.L4: + .db 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x40 diff --git a/tests/debug.x86/args_001.irt b/tests/debug.x86/args_001.irt new file mode 100644 index 0000000..3191581 --- /dev/null +++ b/tests/debug.x86/args_001.irt @@ -0,0 +1,51 @@ +--TEST-- +001: Argument Passing +--TARGET-- +x86 +--ARGS-- +-S --run +--CODE-- +{ + int8_t c_1 = 1; + int16_t c_2 = 2; + int32_t c_3 = 3; + int32_t c_4 = 4; + int32_t c_5 = 5; + uint8_t c_6 = 6; + uint16_t c_7 = 7; + uint32_t c_8 = 8; + int32_t c_9 = 9; + int32_t c_10 = 10; + uintptr_t f = func(printf); + uintptr_t fmt = "%d %d %d %d %d %d %d %d %d %d\n"; + l_1 = START(l_3); + int32_t d_2, l_2 = CALL/11(l_1, f, fmt, c_1, c_2, c_3, c_4, c_5, c_6, c_7, c_8, c_9, c_10); + l_3 = RETURN(l_2, d_2); +} +--EXPECT-- +test: + subl $0x2c, %esp + leal .L1, %eax + movl %eax, (%esp) + movl $1, 4(%esp) + movl $2, 8(%esp) + movl $3, 0xc(%esp) + movl $4, 0x10(%esp) + movl $5, 0x14(%esp) + movl $6, 0x18(%esp) + movl $7, 0x1c(%esp) + movl $8, 0x20(%esp) + movl $9, 0x24(%esp) + movl $0xa, 0x28(%esp) + calll printf + addl $0x2c, %esp + retl +.rodata + .db 0x90, 0x90, 0x90 +.L1: + .db 0x25, 0x64, 0x20, 0x25, 0x64, 0x20, 0x25, 0x64, 0x20, 0x25, 0x64, 0x20, 0x25, 0x64, 0x20, 0x25 + .db 0x64, 0x20, 0x25, 0x64, 0x20, 0x25, 0x64, 0x20, 0x25, 0x64, 0x20, 0x25, 0x64, 0x0a, 0x00 + +1 2 3 4 5 6 7 8 9 10 + +exit code = 21 diff --git a/tests/debug.x86/args_002.irt b/tests/debug.x86/args_002.irt new file mode 100644 index 0000000..4fff869 --- /dev/null +++ b/tests/debug.x86/args_002.irt @@ -0,0 +1,79 @@ +--TEST-- +002: Argument Passing +--TARGET-- +x86 +--ARGS-- +-S --run +--CODE-- +{ + double c_1 = 0.1; + double c_2 = 0.2; + double c_3 = 0.3; + double c_4 = 0.4; + double c_5 = 0.5; + double c_6 = 0.6; + double c_7 = 0.7; + double c_8 = 0.8; + double c_9 = 0.9; + double c_10 = 0.0; + uintptr_t f = func(printf); + uintptr_t fmt = "%g %g %g %g %g %g %g %g %g %g\n"; + l_1 = START(l_3); + int32_t d_2, l_2 = CALL/11(l_1, f, fmt, c_1, c_2, c_3, c_4, c_5, c_6, c_7, c_8, c_9, c_10); + l_3 = RETURN(l_2, d_2); +} +--EXPECT-- +test: + subl $0x5c, %esp + leal .L10, %eax + movl %eax, (%esp) + movsd .L1, %xmm7 + movsd %xmm7, 4(%esp) + movsd .L2, %xmm7 + movsd %xmm7, 0xc(%esp) + movsd .L3, %xmm7 + movsd %xmm7, 0x14(%esp) + movsd .L4, %xmm7 + movsd %xmm7, 0x1c(%esp) + movsd .L5, %xmm7 + movsd %xmm7, 0x24(%esp) + movsd .L6, %xmm7 + movsd %xmm7, 0x2c(%esp) + movsd .L7, %xmm7 + movsd %xmm7, 0x34(%esp) + movsd .L8, %xmm7 + movsd %xmm7, 0x3c(%esp) + movsd .L9, %xmm7 + movsd %xmm7, 0x44(%esp) + xorpd %xmm7, %xmm7 + movsd %xmm7, 0x4c(%esp) + calll printf + addl $0x5c, %esp + retl +.rodata + .db 0x90, 0x90, 0x90 +.L1: + .db 0x9a, 0x99, 0x99, 0x99, 0x99, 0x99, 0xb9, 0x3f +.L2: + .db 0x9a, 0x99, 0x99, 0x99, 0x99, 0x99, 0xc9, 0x3f +.L3: + .db 0x33, 0x33, 0x33, 0x33, 0x33, 0x33, 0xd3, 0x3f +.L4: + .db 0x9a, 0x99, 0x99, 0x99, 0x99, 0x99, 0xd9, 0x3f +.L5: + .db 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x3f +.L6: + .db 0x33, 0x33, 0x33, 0x33, 0x33, 0x33, 0xe3, 0x3f +.L7: + .db 0x66, 0x66, 0x66, 0x66, 0x66, 0x66, 0xe6, 0x3f +.L8: + .db 0x9a, 0x99, 0x99, 0x99, 0x99, 0x99, 0xe9, 0x3f +.L9: + .db 0xcd, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xec, 0x3f +.L10: + .db 0x25, 0x67, 0x20, 0x25, 0x67, 0x20, 0x25, 0x67, 0x20, 0x25, 0x67, 0x20, 0x25, 0x67, 0x20, 0x25 + .db 0x67, 0x20, 0x25, 0x67, 0x20, 0x25, 0x67, 0x20, 0x25, 0x67, 0x20, 0x25, 0x67, 0x0a, 0x00 + +0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 0 + +exit code = 38 diff --git a/tests/debug.x86/call-O0.irt b/tests/debug.x86/call-O0.irt new file mode 100644 index 0000000..8677641 --- /dev/null +++ b/tests/debug.x86/call-O0.irt @@ -0,0 +1,39 @@ +--TEST-- +Simple CALL -O0 +--TARGET-- +x86 +--ARGS-- +-S -O0 --run +--CODE-- +{ + uintptr_t c_1 = 0; + bool c_2 = 0; + bool c_3 = 1; + int32_t c_4 = 42; + uintptr_t c_5 = func(printf); + uintptr_t c_6 = "hello %d!\n"; + l_1 = START(l_4); + int32_t d_2, l_2 = CALL/2(l_1, c_5, c_6, c_4); + l_4 = RETURN(l_2, d_2); +} +--EXPECT-- +test: + subl $0xc, %esp + subl $0x10, %esp + leal .L1, %ecx + movl %ecx, (%esp) + movl $0x2a, 4(%esp) + calll printf + addl $0x10, %esp + movl %eax, (%esp) + movl (%esp), %eax + addl $0xc, %esp + retl +.rodata + .db 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90 +.L1: + .db 0x68, 0x65, 0x6c, 0x6c, 0x6f, 0x20, 0x25, 0x64, 0x21, 0x0a, 0x00 + +hello 42! + +exit code = 10 diff --git a/tests/debug.x86/call.irt b/tests/debug.x86/call.irt new file mode 100644 index 0000000..a5b4536 --- /dev/null +++ b/tests/debug.x86/call.irt @@ -0,0 +1,35 @@ +--TEST-- +Simple CALL +--TARGET-- +x86 +--ARGS-- +-S --run +--CODE-- +{ + uintptr_t c_1 = 0; + bool c_2 = 0; + bool c_3 = 1; + int32_t c_4 = 42; + uintptr_t c_5 = func(printf); + uintptr_t c_6 = "hello %d!\n"; + l_1 = START(l_4); + int32_t d_2, l_2 = CALL/2(l_1, c_5, c_6, c_4); + l_4 = RETURN(l_2, d_2); +} +--EXPECT-- +test: + subl $0xc, %esp + leal .L1, %eax + movl %eax, (%esp) + movl $0x2a, 4(%esp) + calll printf + addl $0xc, %esp + retl +.rodata + .db 0x90, 0x90, 0x90 +.L1: + .db 0x68, 0x65, 0x6c, 0x6c, 0x6f, 0x20, 0x25, 0x64, 0x21, 0x0a, 0x00 + +hello 42! + +exit code = 10 diff --git a/tests/debug.x86/call2.irt b/tests/debug.x86/call2.irt new file mode 100644 index 0000000..1e4f409 --- /dev/null +++ b/tests/debug.x86/call2.irt @@ -0,0 +1,45 @@ +--TEST-- +CALL with parallel argument passing +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + uintptr_t c_1 = 0; + bool c_2 = 0; + bool c_3 = 1; + int32_t c_4 = 42; + uintptr_t c_5 = func(printf); + uintptr_t c_6 = "hello %d!\n"; + l_1 = START(l_4); + int32_t p_1 = PARAM(l_1, "p1", 1); + int32_t p_2 = PARAM(l_1, "p2", 1); + int32_t p_3 = PARAM(l_1, "p3", 1); + int32_t p_4 = PARAM(l_1, "p4", 1); + int32_t d_2, l_2 = CALL/4(l_1, c_5, c_6, p_3, p_4, p_2); + int32_t d_3 = ADD(d_2, p_1); + l_4 = RETURN(l_2, d_3); +} +--EXPECT-- +test: + subl $0x1c, %esp + movl %ebx, 0x18(%esp) + movl 0x20(%esp), %ebx + leal .L1, %eax + movl %eax, (%esp) + movl 0x28(%esp), %eax + movl %eax, 4(%esp) + movl 0x2c(%esp), %eax + movl %eax, 8(%esp) + movl 0x24(%esp), %eax + movl %eax, 0xc(%esp) + calll printf + leal (%eax, %ebx), %eax + movl 0x18(%esp), %ebx + addl $0x1c, %esp + retl +.rodata + .db 0x90, 0x90, 0x90, 0x90 +.L1: + .db 0x68, 0x65, 0x6c, 0x6c, 0x6f, 0x20, 0x25, 0x64, 0x21, 0x0a, 0x00 diff --git a/tests/debug.x86/call3.irt b/tests/debug.x86/call3.irt new file mode 100644 index 0000000..5876850 --- /dev/null +++ b/tests/debug.x86/call3.irt @@ -0,0 +1,44 @@ +--TEST-- +CALL with parallel argument passing +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + uintptr_t c_6 = "hello %d!\n"; + l_1 = START(l_4); + int32_t p_1 = PARAM(l_1, "p1", 1); + int32_t p_2 = PARAM(l_1, "p2", 2); + int32_t p_3 = PARAM(l_1, "p3", 3); + int32_t p_4 = PARAM(l_1, "p4", 4); + uintptr_t fp = PARAM(l_1, "fp", 5); + uintptr_t f, l_11 = LOAD(l_1, fp); + int32_t d_2, l_2 = CALL/4(l_11, f, c_6, p_3, p_4, p_2); + int32_t d_3 = ADD(d_2, p_1); + l_4 = RETURN(l_2, d_3); +} +--EXPECT-- +test: + subl $0x1c, %esp + movl %ebx, 0x18(%esp) + movl 0x20(%esp), %ebx + movl 0x30(%esp), %eax + movl (%eax), %eax + leal .L1, %ecx + movl %ecx, (%esp) + movl 0x28(%esp), %ecx + movl %ecx, 4(%esp) + movl 0x2c(%esp), %ecx + movl %ecx, 8(%esp) + movl 0x24(%esp), %ecx + movl %ecx, 0xc(%esp) + calll *%eax + leal (%eax, %ebx), %eax + movl 0x18(%esp), %ebx + addl $0x1c, %esp + retl +.rodata + .db 0x90 +.L1: + .db 0x68, 0x65, 0x6c, 0x6c, 0x6f, 0x20, 0x25, 0x64, 0x21, 0x0a, 0x00 diff --git a/tests/debug.x86/call_002.irt b/tests/debug.x86/call_002.irt new file mode 100644 index 0000000..139bdf7 --- /dev/null +++ b/tests/debug.x86/call_002.irt @@ -0,0 +1,29 @@ +--TEST-- +Indirect CALL +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + uintptr_t c_6 = "hello %d!\n"; + l_1 = START(l_4); + uintptr_t f = PARAM(l_1, "f", 1); + int32_t p = PARAM(l_1, "p", 2); + int32_t d_2, l_2 = CALL/2(l_1, f, c_6, p); + l_4 = RETURN(l_2, d_2); +} +--EXPECT-- +test: + subl $0xc, %esp + leal .L1, %eax + movl %eax, (%esp) + movl 0x14(%esp), %eax + movl %eax, 4(%esp) + calll *0x10(%esp) + addl $0xc, %esp + retl +.rodata + .db 0x90, 0x90, 0x90, 0x90 +.L1: + .db 0x68, 0x65, 0x6c, 0x6c, 0x6f, 0x20, 0x25, 0x64, 0x21, 0x0a, 0x00 diff --git a/tests/debug.x86/call_alloca.irt b/tests/debug.x86/call_alloca.irt new file mode 100644 index 0000000..3d1426e --- /dev/null +++ b/tests/debug.x86/call_alloca.irt @@ -0,0 +1,66 @@ +--TEST-- +Simple CALL with ALLOCA +--TARGET-- +x86 +--ARGS-- +-S --run +--CODE-- +{ + uintptr_t c_1 = 0; + bool c_2 = 0; + bool c_3 = 1; + int32_t c_4 = 42; + char h = 'h'; + char i = 'i'; + char sp = ' '; + char pc = '%'; + char d = 'd'; + char nl = '\n'; + char zero = 0; + uint32_t len = 7; + uintptr_t one = 1; + uintptr_t c_5 = func(printf); + l_1 = START(l_4); + uintptr_t a_0, s_0 = ALLOCA(l_1, len); + s_1 = STORE(s_0, a_0, h); + uintptr_t a_1 = ADD(a_0, one); + s_2 = STORE(s_1, a_1, i); + uintptr_t a_2 = ADD(a_1, one); + s_3 = STORE(s_2, a_2, sp); + uintptr_t a_3 = ADD(a_2, one); + s_4 = STORE(s_3, a_3, pc); + uintptr_t a_4 = ADD(a_3, one); + s_5 = STORE(s_4, a_4, d); + uintptr_t a_5 = ADD(a_4, one); + s_6 = STORE(s_5, a_5, nl); + uintptr_t a_6 = ADD(a_5, one); + s_7 = STORE(s_6, a_6, zero); + int32_t d_2, l_2 = CALL/2(s_7, c_5, a_0, c_4); + l_4 = RETURN(l_2, d_2); +} +--EXPECT-- +test: + pushl %ebp + movl %esp, %ebp + subl $8, %esp + subl $0x10, %esp + movl %esp, %eax + movb $0x68, (%eax) + movb $0x69, 1(%eax) + movb $0x20, 2(%eax) + movb $0x25, 3(%eax) + movb $0x64, 4(%eax) + movb $0xa, 5(%eax) + movb $0, 6(%eax) + subl $0x10, %esp + movl %eax, (%esp) + movl $0x2a, 4(%esp) + calll printf + addl $0x10, %esp + movl %ebp, %esp + popl %ebp + retl + +hi 42 + +exit code = 6 diff --git a/tests/debug.x86/call_vaddr.irt b/tests/debug.x86/call_vaddr.irt new file mode 100644 index 0000000..8143b81 --- /dev/null +++ b/tests/debug.x86/call_vaddr.irt @@ -0,0 +1,60 @@ +--TEST-- +Simple CALL with VADDR +--TARGET-- +x86 +--ARGS-- +-S --run +--CODE-- +{ + uintptr_t c_1 = 0; + bool c_2 = 0; + bool c_3 = 1; + int32_t c_4 = 42; + char h = 'h'; + char i = 'i'; + char sp = ' '; + char pc = '%'; + char d = 'd'; + char nl = '\n'; + char zero = 0; + uintptr_t one = 1; + uintptr_t c_5 = func(printf); + l_1 = START(l_4); + uint64_t var = VAR(l_1, "str"); + uintptr_t a_0 = VADDR(var); + s_1 = STORE(l_1, a_0, h); + uintptr_t a_1 = ADD(a_0, one); + s_2 = STORE(s_1, a_1, i); + uintptr_t a_2 = ADD(a_1, one); + s_3 = STORE(s_2, a_2, sp); + uintptr_t a_3 = ADD(a_2, one); + s_4 = STORE(s_3, a_3, pc); + uintptr_t a_4 = ADD(a_3, one); + s_5 = STORE(s_4, a_4, d); + uintptr_t a_5 = ADD(a_4, one); + s_6 = STORE(s_5, a_5, nl); + uintptr_t a_6 = ADD(a_5, one); + s_7 = STORE(s_6, a_6, zero); + int32_t d_2, l_2 = CALL/2(s_7, c_5, a_0, c_4); + l_4 = RETURN(l_2, d_2); +} +--EXPECT-- +test: + subl $0x1c, %esp + leal 8(%esp), %eax + movb $0x68, (%eax) + movb $0x69, 1(%eax) + movb $0x20, 2(%eax) + movb $0x25, 3(%eax) + movb $0x64, 4(%eax) + movb $0xa, 5(%eax) + movb $0, 6(%eax) + movl %eax, (%esp) + movl $0x2a, 4(%esp) + calll printf + addl $0x1c, %esp + retl + +hi 42 + +exit code = 6 diff --git a/tests/debug.x86/combo_001.irt b/tests/debug.x86/combo_001.irt new file mode 100644 index 0000000..8ff5184 --- /dev/null +++ b/tests/debug.x86/combo_001.irt @@ -0,0 +1,44 @@ +--TEST-- +Combo 001 +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +# Figure 3.9 from "Combining Analyses, Combining Optimization" by C.Click +#func test(bool): uint32_t +{ + uintptr_t c_1 = 0; + bool c_2 = 0; + bool c_3 = 1; + int32_t i_1 = 1; + int32_t i_2 = 2; + ll_1 = START(ll_16); + bool cond = PARAM(ll_1, "cond", 0); + int32_t x_0 = COPY(i_1); + ll_2 = END(ll_1); + ll_3 = LOOP_BEGIN(ll_2, ll_12); + int32_t x_1 = PHI(ll_3, x_0, x_3); + bool b = NE(x_1, i_1); + ll_4 = IF(ll_3, b); + ll_5 = IF_TRUE(ll_4); + int32_t x_2 = COPY(i_2); + ll_6 = END(ll_5); + ll_7 = IF_FALSE(ll_4); + ll_72 = END(ll_7); + ll_8 = MERGE(ll_6, ll_72); + int32_t x_3 = PHI(ll_8, x_2, x_1); + ll_10 = IF(ll_8, cond); + ll_11 = IF_TRUE(ll_10); + ll_12 = LOOP_END(ll_11, ll_3); + ll_13 = IF_FALSE(ll_10); + ll_16 = RETURN(ll_13, x_3); +} +--EXPECT-- +test: + movb 4(%esp), %al +.L1: + testb %al, %al + jne .L1 + movl $1, %eax + retl diff --git a/tests/debug.x86/combo_002.irt b/tests/debug.x86/combo_002.irt new file mode 100644 index 0000000..2d1913a --- /dev/null +++ b/tests/debug.x86/combo_002.irt @@ -0,0 +1,56 @@ +--TEST-- +Combo 002 +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +#func test(bool, bool): int32_t +{ + uintptr_t c_1 = 0; + bool c_2 = 0; + bool c_3 = 1; + int32_t c_4 = 1; + int32_t c_5 = 2; + l_1 = START(l_34); + bool d_2 = PARAM(l_1, "cond", 0); + int32_t d_3 = PARAM(l_1, "z", 1); + bool d_4 = COPY(c_4); + bool d_5 = COPY(d_3); + l_6 = END(l_1); + l_7 = LOOP_BEGIN(l_6, l_31); + int32_t d_8 = PHI(l_7, d_4, d_19); + int32_t d_9 = PHI(l_7, d_5, d_28); + bool d_10 = NE(d_9, d_3); + l_11 = IF(l_7, d_10); + l_12 = IF_TRUE(l_11); + int32_t d_13 = COPY(c_5); + l_14 = END(l_12); + l_15 = IF_FALSE(l_11); + l_16 = END(l_15); + l_17 = MERGE(l_14, l_16); + int32_t d_18 = PHI(l_17, d_13, d_8); + int32_t d_19 = SUB(c_5, d_18); + bool d_20 = NE(d_19, c_4); + l_21 = IF(l_17, d_20); + l_22 = IF_TRUE(l_21); + int32_t d_23 = COPY(c_5); + l_24 = END(l_22); + l_25 = IF_FALSE(l_21); + l_26 = END(l_25); + l_27 = MERGE(l_24, l_26); + int32_t d_28 = PHI(l_27, d_23, d_9); + l_29 = IF(l_27, d_2); + l_30 = IF_TRUE(l_29); + l_31 = LOOP_END(l_30, l_7); + l_32 = IF_FALSE(l_29); + l_34 = RETURN(l_32, d_19); +} +--EXPECT-- +test: + movb 4(%esp), %al +.L1: + testb %al, %al + jne .L1 + movl $1, %eax + retl diff --git a/tests/debug.x86/combo_003.irt b/tests/debug.x86/combo_003.irt new file mode 100644 index 0000000..fb727f0 --- /dev/null +++ b/tests/debug.x86/combo_003.irt @@ -0,0 +1,56 @@ +--TEST-- +Combo 003 +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + uintptr_t c_1 = 0; + bool c_2 = 0; + bool c_3 = 1; + int32_t c_4 = 1; + int32_t c_5 = 2; + l_1 = START(l_34); + bool d_2 = PARAM(l_1, "cond", 0); + int32_t d_3 = PARAM(l_1, "z", 1); + bool d_4 = COPY(c_4); + int32_t d_5 = COPY(d_3); + l_6 = END(l_1); + l_7 = LOOP_BEGIN(l_6, l_31); + int32_t d_8 = PHI(l_7, d_4, d_19); + int32_t d_9 = PHI(l_7, d_5, d_28); + bool d_10 = NE(d_9, d_3); + l_11 = IF(l_7, d_10); + l_12 = IF_TRUE(l_11); + int32_t d_13 = COPY(c_5); + l_14 = END(l_12); + l_15 = IF_FALSE(l_11); + l_16 = END(l_15); + l_17 = MERGE(l_14, l_16); + int32_t d_18 = PHI(l_17, d_13, d_8); + int32_t d_19 = SUB(c_5, d_18); + bool d_20 = NE(d_19, c_4); + l_21 = IF(l_17, d_20); + l_22 = IF_TRUE(l_21); + int32_t d_23 = COPY(c_5); + l_24 = END(l_22); + l_25 = IF_FALSE(l_21); + l_26 = END(l_25); + l_27 = MERGE(l_24, l_26); + int32_t d_28 = PHI(l_27, d_23, d_9); + l_29 = IF(l_27, d_2); + l_30 = IF_TRUE(l_29); + l_31 = LOOP_END(l_30, l_7); + l_32 = IF_FALSE(l_29); + int32_t xx = MUL(d_19, d_28); + l_34 = RETURN(l_32, xx); +} +--EXPECT-- +test: + movb 4(%esp), %al +.L1: + testb %al, %al + jne .L1 + movl 8(%esp), %eax + retl diff --git a/tests/debug.x86/combo_004.irt b/tests/debug.x86/combo_004.irt new file mode 100644 index 0000000..68b03e9 --- /dev/null +++ b/tests/debug.x86/combo_004.irt @@ -0,0 +1,48 @@ +--TEST-- +Combo 004 +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +# Figure 3.9 from "Combining Analyses, Combining Optimization" by C.Click +{ + uintptr_t c_1 = 0; + bool c_2 = 0; + bool c_3 = 1; + int32_t i_1 = 1; + int32_t i_2 = 2; + ll_1 = START(ll_16); + bool cond = PARAM(ll_1, "cond", 0); + int32_t ret = PARAM(ll_1, "ret", 1); + int32_t x_0 = COPY(i_1); + ll_2 = END(ll_1); + ll_3 = LOOP_BEGIN(ll_2, ll_12); + int32_t x_1 = PHI(ll_3, x_0, x_3); + bool b = NE(x_1, i_1); + ll_4 = IF(ll_3, b); + ll_5 = IF_TRUE(ll_4); + int32_t x_2 = COPY(i_2); + ll_6 = END(ll_5); + ll_7 = IF_FALSE(ll_4); + ll_72 = END(ll_7); + ll_8 = MERGE(ll_6, ll_72); + int32_t x_3 = PHI(ll_8, x_2, x_1); + ll_10 = IF(ll_8, cond); + ll_11 = IF_TRUE(ll_10); + ll_12 = LOOP_END(ll_11, ll_3); + ll_13 = IF_FALSE(ll_10); + int32_t xx = MUL(x_3, i_2); + int32_t yy = MUL(xx, ret); + ll_16 = RETURN(ll_13, yy); +} +--EXPECT-- +test: + movb 4(%esp), %al + movl 8(%esp), %ecx + leal (%ecx, %ecx), %ecx +.L1: + testb %al, %al + jne .L1 + movl %ecx, %eax + retl diff --git a/tests/debug.x86/dce_001.irt b/tests/debug.x86/dce_001.irt new file mode 100644 index 0000000..1df11e8 --- /dev/null +++ b/tests/debug.x86/dce_001.irt @@ -0,0 +1,42 @@ +--TEST-- +DCE 001 +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + uintptr_t c_1 = 0; + bool c_2 = 0; + bool c_3 = 1; + int32_t c_4 = 10; + int32_t c_5 = 2; + int32_t c_6 = 1; + int32_t c_7 = 0; + l_1 = START(l_16); + int32_t d_2 = PARAM(l_1, "x", 0); + l_3 = END(l_1); + l_4 = LOOP_BEGIN(l_3, l_12); + int32_t d_5 = PHI(l_4, c_7, d_7); + int32_t d_6 = ADD(d_2, c_6); + int32_t d_7 = ADD(d_6, d_5); + int32_t d_8 = MUL(d_7, c_5); + int32_t xxx = DIV(d_8, c_4); + bool d_9 = LT(d_7, c_4); + l_10 = IF(l_4, d_9); + l_11 = IF_TRUE(l_10); + l_12 = LOOP_END(l_11, l_4); + l_13 = IF_FALSE(l_10); + l_16 = RETURN(l_13, d_8); +} +--EXPECT-- +test: + movl 4(%esp), %eax + leal 1(%eax), %eax + xorl %ecx, %ecx +.L1: + leal (%eax, %ecx), %ecx + cmpl $0xa, %ecx + jl .L1 + leal (%ecx, %ecx), %eax + retl diff --git a/tests/debug.x86/dessa_001.irt b/tests/debug.x86/dessa_001.irt new file mode 100644 index 0000000..faea09c --- /dev/null +++ b/tests/debug.x86/dessa_001.irt @@ -0,0 +1,33 @@ +--TEST-- +DESSA 001 +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +# Figure 1 from "Translating Out of Static Single Assignment Form" by Sreedhar +{ + uintptr_t c_1 = 0; + bool c_2 = 0; + bool c_3 = 1; + l_1 = START(l_13); + int32_t d_2 = PARAM(l_1, "a", 0); + int32_t d_3 = PARAM(l_1, "b", 1); + bool d_4 = PARAM(l_1, "cond", 2); + l_6 = IF(l_1, d_4); + l_7 = IF_TRUE(l_6); + l_8 = END(l_7); + l_9 = IF_FALSE(l_6); + l_10 = END(l_9); + l_11 = MERGE(l_8, l_10); + int32_t d_12 = PHI(l_11, d_3, d_2); + l_13 = RETURN(l_11, d_12); +} +--EXPECT-- +test: + movl 4(%esp), %eax + cmpb $0, 0xc(%esp) + je .L1 + movl 8(%esp), %eax +.L1: + retl diff --git a/tests/debug.x86/dessa_002.irt b/tests/debug.x86/dessa_002.irt new file mode 100644 index 0000000..b2a3b9e --- /dev/null +++ b/tests/debug.x86/dessa_002.irt @@ -0,0 +1,35 @@ +--TEST-- +DESSA 002 +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + uintptr_t c_1 = 0; + bool c_2 = 0; + bool c_3 = 1; + int32_t c_4 = 1; + l_1 = START(l_13); + int32_t d_2 = PARAM(l_1, "x", 0); + l_3 = END(l_1); + l_4 = LOOP_BEGIN(l_3, l_9); + int32_t d_5 = PHI(l_4, d_2, d_6); + int32_t d_6 = ADD(d_5, c_4); + l_7 = IF(l_4, d_6); + l_8 = IF_TRUE(l_7); + l_9 = LOOP_END(l_8, l_4); + l_10 = IF_FALSE(l_7); + l_13 = RETURN(l_10, d_5); +} +--EXPECT-- +test: + movl 4(%esp), %eax +.L1: + movl %eax, %ecx + addl $1, %ecx + je .L2 + movl %ecx, %eax + jmp .L1 +.L2: + retl diff --git a/tests/debug.x86/dessa_003.irt b/tests/debug.x86/dessa_003.irt new file mode 100644 index 0000000..b38b23e --- /dev/null +++ b/tests/debug.x86/dessa_003.irt @@ -0,0 +1,55 @@ +--TEST-- +DESSA 003 +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +# Figure 8 (swap problem) from "Translating Out of Static Single Assignment Form" by Sreedhar +{ + uintptr_t c_1 = 0; + bool c_2 = 0; + bool c_3 = 1; + int32_t c_4 = 1; + int32_t c_12 = 12; + l_1 = START(l_13); + int32_t x0 = PARAM(l_1, "x", 0); + int32_t y1 = PARAM(l_1, "y", 1); + int32_t cond = PARAM(l_1, "z", 2); + int32_t x1 = DIV(x0, c_12); + l_3 = END(l_1); + l_4 = LOOP_BEGIN(l_3, l_9); + int32_t x2 = PHI(l_4, x1, x3); + int32_t y2 = PHI(l_4, y1, y3); + int32_t z = COPY(x2); + int32_t x3 = COPY(y2); + int32_t y3 = COPY(z); + l_7 = IF(l_4, cond); + l_8 = IF_TRUE(l_7); + l_9 = LOOP_END(l_8, l_4); + l_10 = IF_FALSE(l_7); + l_13 = RETURN(l_10, z); +} +--EXPECT-- +test: + subl $8, %esp + movl %ebx, 4(%esp) + movl %ebp, (%esp) + movl 0x10(%esp), %ecx + movl 0x14(%esp), %ebx + movl 0xc(%esp), %eax + movl $0xc, %ebp + cltd + idivl %ebp +.L1: + testl %ebx, %ebx + je .L2 + movl %eax, %edx + movl %ecx, %eax + movl %edx, %ecx + jmp .L1 +.L2: + movl 4(%esp), %ebx + movl (%esp), %ebp + addl $8, %esp + retl diff --git a/tests/debug.x86/fig-O0.irt b/tests/debug.x86/fig-O0.irt new file mode 100644 index 0000000..2946b72 --- /dev/null +++ b/tests/debug.x86/fig-O0.irt @@ -0,0 +1,175 @@ +--TEST-- +Fig -O0 +--TARGET-- +x86 +--ARGS-- +-S -O0 +--CODE-- +{ + uintptr_t c_1 = 0; + bool c_2 = 0; + bool c_3 = 1; + int32_t i_1 = 1; + int32_t i_4 = 4; + ll_1 = START(ll_16); # <- + int32_t a_0 = PARAM(ll_1, "a", 0); + int32_t b_0 = PARAM(ll_1, "b", 1); + int32_t c_0 = PARAM(ll_1, "c", 2); + int32_t d_0 = PARAM(ll_1, "d", 3); + int32_t l_0 = PARAM(ll_1, "l", 4); + int32_t m_0 = PARAM(ll_1, "m", 5); + int32_t s_0 = PARAM(ll_1, "s", 6); + int32_t t_0 = PARAM(ll_1, "t", 7); + int32_t cond1 = PARAM(ll_1, "cond1", 8); + int32_t cond2 = PARAM(ll_1, "cond2", 9); + ll_2 = END(ll_1); + ll_3 = LOOP_BEGIN(ll_2, ll_12); # <- + int32_t a_1 = PHI(ll_3, a_0, a_3); + int32_t d_1 = PHI(ll_3, d_0, d_3); + int32_t m_1 = PHI(ll_3, m_0, m_3); + int32_t s_1 = PHI(ll_3, s_0, s_3); + int32_t t_1 = PHI(ll_3, t_0, t_3); + ll_4 = IF(ll_3, cond1); + ll_5 = IF_TRUE(ll_4); + int32_t l_1 = MUL(c_0, b_0); + int32_t m_2 = ADD(l_1, i_4); + int32_t a_2 = COPY(c_0); + ll_6 = END(ll_5); + ll_7 = IF_FALSE(ll_4); + int32_t d_2 = COPY(c_0); + int32_t l_2 = MUL(d_2, b_0); + int32_t s_2 = MUL(a_1, b_0); + int32_t t_2 = ADD(s_2, i_1); + ll_8 = END(ll_7); + ll_9 = MERGE(ll_6, ll_8); + int32_t a_3 = PHI(ll_9, a_2, a_1); + int32_t d_3 = PHI(ll_9, d_1, d_2); + int32_t l_3 = PHI(ll_9, l_1, l_2); + int32_t m_3 = PHI(ll_9, m_2, m_1); + int32_t s_3 = PHI(ll_9, s_1, s_2); + int32_t t_3 = PHI(ll_9, t_1, t_2); + int32_t x_0 = MUL(a_3, b_0); + int32_t y_0 = ADD(x_0, i_1); + ll_10 = IF(ll_9, cond2); + ll_11 = IF_TRUE(ll_10); + ll_12 = LOOP_END(ll_11, ll_3); + ll_13 = IF_FALSE(ll_10); + int32_t ret1 = ADD(a_3, b_0); + int32_t ret2 = ADD(ret1, c_0); + int32_t ret3 = ADD(ret2, d_3); + int32_t ret4 = ADD(ret3, l_3); + int32_t ret5 = ADD(ret4, m_3); + int32_t ret6 = ADD(ret5, s_3); + int32_t ret7 = ADD(ret6, t_3); + int32_t ret8 = ADD(ret7, y_0); + ll_16 = RETURN(ll_13, ret8); +} +--EXPECT-- +test: + subl $0x70, %esp + movl 0x74(%esp), %eax + movl %eax, (%esp) + movl 0x80(%esp), %eax + movl %eax, 4(%esp) + movl 0x88(%esp), %eax + movl %eax, 8(%esp) + movl 0x8c(%esp), %eax + movl %eax, 0xc(%esp) + movl 0x90(%esp), %eax + movl %eax, 0x10(%esp) +.L1: + cmpl $0, 0x94(%esp) + je .L2 + movl 0x7c(%esp), %eax + imull 0x78(%esp), %eax + movl %eax, 0x14(%esp) + movl 0x14(%esp), %eax + addl $4, %eax + movl %eax, 0x18(%esp) + movl 0x7c(%esp), %eax + movl %eax, 0x1c(%esp) + movl 0x1c(%esp), %eax + movl %eax, 0x30(%esp) + movl 4(%esp), %eax + movl %eax, 0x34(%esp) + movl 0x14(%esp), %eax + movl %eax, 0x38(%esp) + movl 0x18(%esp), %eax + movl %eax, 0x3c(%esp) + movl 0xc(%esp), %eax + movl %eax, 0x40(%esp) + movl 0x10(%esp), %eax + movl %eax, 0x44(%esp) + jmp .L3 +.L2: + movl 0x7c(%esp), %eax + movl %eax, 0x20(%esp) + movl 0x20(%esp), %eax + imull 0x78(%esp), %eax + movl %eax, 0x24(%esp) + movl (%esp), %eax + imull 0x78(%esp), %eax + movl %eax, 0x28(%esp) + movl 0x28(%esp), %eax + addl $1, %eax + movl %eax, 0x2c(%esp) + movl (%esp), %eax + movl %eax, 0x30(%esp) + movl 0x20(%esp), %eax + movl %eax, 0x34(%esp) + movl 0x24(%esp), %eax + movl %eax, 0x38(%esp) + movl 8(%esp), %eax + movl %eax, 0x3c(%esp) + movl 0x28(%esp), %eax + movl %eax, 0x40(%esp) + movl 0x2c(%esp), %eax + movl %eax, 0x44(%esp) +.L3: + movl 0x30(%esp), %eax + imull 0x78(%esp), %eax + movl %eax, 0x48(%esp) + movl 0x48(%esp), %eax + addl $1, %eax + movl %eax, 0x4c(%esp) + cmpl $0, 0x98(%esp) + je .L4 + movl 0x30(%esp), %eax + movl %eax, (%esp) + movl 0x34(%esp), %eax + movl %eax, 4(%esp) + movl 0x3c(%esp), %eax + movl %eax, 8(%esp) + movl 0x40(%esp), %eax + movl %eax, 0xc(%esp) + movl 0x44(%esp), %eax + movl %eax, 0x10(%esp) + jmp .L1 +.L4: + movl 0x30(%esp), %eax + addl 0x78(%esp), %eax + movl %eax, 0x50(%esp) + movl 0x50(%esp), %eax + addl 0x7c(%esp), %eax + movl %eax, 0x54(%esp) + movl 0x54(%esp), %eax + addl 0x34(%esp), %eax + movl %eax, 0x58(%esp) + movl 0x58(%esp), %eax + addl 0x38(%esp), %eax + movl %eax, 0x5c(%esp) + movl 0x5c(%esp), %eax + addl 0x3c(%esp), %eax + movl %eax, 0x60(%esp) + movl 0x60(%esp), %eax + addl 0x40(%esp), %eax + movl %eax, 0x64(%esp) + movl 0x64(%esp), %eax + addl 0x44(%esp), %eax + movl %eax, 0x68(%esp) + movl 0x68(%esp), %eax + addl 0x4c(%esp), %eax + movl %eax, 0x6c(%esp) + movl 0x6c(%esp), %eax + addl $0x70, %esp + retl diff --git a/tests/debug.x86/fig.irt b/tests/debug.x86/fig.irt new file mode 100644 index 0000000..8784dfe --- /dev/null +++ b/tests/debug.x86/fig.irt @@ -0,0 +1,114 @@ +--TEST-- +Fig +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + uintptr_t c_1 = 0; + bool c_2 = 0; + bool c_3 = 1; + int32_t i_1 = 1; + int32_t i_4 = 4; + ll_1 = START(ll_16); # <- + int32_t a_0 = PARAM(ll_1, "a", 0); + int32_t b_0 = PARAM(ll_1, "b", 1); + int32_t c_0 = PARAM(ll_1, "c", 2); + int32_t d_0 = PARAM(ll_1, "d", 3); + int32_t l_0 = PARAM(ll_1, "l", 4); + int32_t m_0 = PARAM(ll_1, "m", 5); + int32_t s_0 = PARAM(ll_1, "s", 6); + int32_t t_0 = PARAM(ll_1, "t", 7); + int32_t cond1 = PARAM(ll_1, "cond1", 8); + int32_t cond2 = PARAM(ll_1, "cond2", 9); + ll_2 = END(ll_1); + ll_3 = LOOP_BEGIN(ll_2, ll_12); # <- + int32_t a_1 = PHI(ll_3, a_0, a_3); + int32_t d_1 = PHI(ll_3, d_0, d_3); + int32_t m_1 = PHI(ll_3, m_0, m_3); + int32_t s_1 = PHI(ll_3, s_0, s_3); + int32_t t_1 = PHI(ll_3, t_0, t_3); + ll_4 = IF(ll_3, cond1); + ll_5 = IF_TRUE(ll_4); + int32_t l_1 = MUL(c_0, b_0); + int32_t m_2 = ADD(l_1, i_4); + int32_t a_2 = COPY(c_0); + ll_6 = END(ll_5); + ll_7 = IF_FALSE(ll_4); + int32_t d_2 = COPY(c_0); + int32_t l_2 = MUL(d_2, b_0); + int32_t s_2 = MUL(a_1, b_0); + int32_t t_2 = ADD(s_2, i_1); + ll_8 = END(ll_7); + ll_9 = MERGE(ll_6, ll_8); + int32_t a_3 = PHI(ll_9, a_2, a_1); + int32_t d_3 = PHI(ll_9, d_1, d_2); + int32_t l_3 = PHI(ll_9, l_1, l_2); + int32_t m_3 = PHI(ll_9, m_2, m_1); + int32_t s_3 = PHI(ll_9, s_1, s_2); + int32_t t_3 = PHI(ll_9, t_1, t_2); + int32_t x_0 = MUL(a_3, b_0); + int32_t y_0 = ADD(x_0, i_1); + ll_10 = IF(ll_9, cond2); + ll_11 = IF_TRUE(ll_10); + ll_12 = LOOP_END(ll_11, ll_3); + ll_13 = IF_FALSE(ll_10); + int32_t ret1 = ADD(a_3, b_0); + int32_t ret2 = ADD(ret1, c_0); + int32_t ret3 = ADD(ret2, d_3); + int32_t ret4 = ADD(ret3, l_3); + int32_t ret5 = ADD(ret4, m_3); + int32_t ret6 = ADD(ret5, s_3); + int32_t ret7 = ADD(ret6, t_3); + int32_t ret8 = ADD(ret7, y_0); + ll_16 = RETURN(ll_13, ret8); +} +--EXPECT-- +test: + subl $0x18, %esp + movl %ebx, 0x14(%esp) + movl %ebp, 0x10(%esp) + movl %esi, 0xc(%esp) + movl %edi, 8(%esp) + movl 0x1c(%esp), %eax + movl 0x20(%esp), %ecx + movl 0x24(%esp), %edx + movl 0x28(%esp), %ebx + movl %edx, %ebp + imull %ecx, %ebp + movl %ebp, (%esp) + movl (%esp), %ebp + leal 4(%ebp), %ebp + movl %ebp, 4(%esp) +.L1: + cmpl $0, 0x3c(%esp) + je .L3 + movl %edx, %eax + movl 4(%esp), %ebp +.L2: + cmpl $0, 0x40(%esp) + jne .L1 + movl %eax, %esi + imull %ecx, %esi + leal (%eax, %ecx), %eax + leal (%eax, %edx), %eax + leal (%eax, %ebx), %eax + movl (%esp), %edi + leal (%eax, %edi), %eax + leal (%eax, %ebp), %eax + leal (%eax, %ecx), %eax + leal (%eax, %ecx), %eax + leal 1(%eax, %esi), %eax + movl 0x14(%esp), %ebx + movl 0x10(%esp), %ebp + movl 0xc(%esp), %esi + movl 8(%esp), %edi + addl $0x18, %esp + retl +.L3: + movl %eax, %esi + imull %ecx, %esi + leal 1(%esi), %edi + movl %edx, %ebx + jmp .L2 diff --git a/tests/debug.x86/ijmp_001.irt b/tests/debug.x86/ijmp_001.irt new file mode 100644 index 0000000..fab3e93 --- /dev/null +++ b/tests/debug.x86/ijmp_001.irt @@ -0,0 +1,15 @@ +--TEST-- +001: IJMP - computed goto +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + l_1 = START(l_2); + uintptr_t p = PARAM(l_1, "p", 1); + l_2 = IJMP(l_1, p); +} +--EXPECT-- +test: + jmpl *4(%esp) diff --git a/tests/debug.x86/lea_001.irt b/tests/debug.x86/lea_001.irt new file mode 100644 index 0000000..d7c3318 --- /dev/null +++ b/tests/debug.x86/lea_001.irt @@ -0,0 +1,24 @@ +--TEST-- +LEA 001 +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + int32_t i_1 = 10; + int32_t i_4 = 4; + l_1 = START(l_2); + int32_t x = PARAM(l_1, "x", 0); + int32_t y = PARAM(l_1, "y", 0); + int32_t z1 = ADD(x, i_1); + int32_t z2 = MUL(y, i_4); + int32_t z3 = ADD(z1, z2); + l_2 = RETURN(l_1, z3); +} +--EXPECT-- +test: + movl 4(%esp), %eax + movl 8(%esp), %ecx + leal 0xa(%eax, %ecx, 4), %eax + retl diff --git a/tests/debug.x86/loop_001.irt b/tests/debug.x86/loop_001.irt new file mode 100644 index 0000000..00158ee --- /dev/null +++ b/tests/debug.x86/loop_001.irt @@ -0,0 +1,41 @@ +--TEST-- +LOOP 001 +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + uintptr_t c_1 = 0; + bool c_2 = 0; + bool c_3 = 1; + int32_t c_4 = 10; + int32_t c_5 = 2; + int32_t c_6 = 1; + int32_t c_7 = 0; + l_1 = START(l_16); + int32_t d_2 = PARAM(l_1, "x", 0); + l_3 = END(l_1); + l_4 = LOOP_BEGIN(l_3, l_12); + int32_t d_5 = PHI(l_4, c_7, d_7); + int32_t d_6 = ADD(d_2, c_6); + int32_t d_7 = ADD(d_6, d_5); + int32_t d_8 = MUL(d_7, c_5); + bool d_9 = LT(d_7, c_4); + l_10 = IF(l_4, d_9); + l_11 = IF_TRUE(l_10); + l_12 = LOOP_END(l_11, l_4); + l_13 = IF_FALSE(l_10); + l_16 = RETURN(l_13, d_8); +} +--EXPECT-- +test: + movl 4(%esp), %eax + leal 1(%eax), %eax + xorl %ecx, %ecx +.L1: + leal (%eax, %ecx), %ecx + cmpl $0xa, %ecx + jl .L1 + leal (%ecx, %ecx), %eax + retl diff --git a/tests/debug.x86/loop_002.irt b/tests/debug.x86/loop_002.irt new file mode 100644 index 0000000..496789c --- /dev/null +++ b/tests/debug.x86/loop_002.irt @@ -0,0 +1,68 @@ +--TEST-- +LOOP 002 +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + uintptr_t c_1 = 0; + bool c_2 = 0; + bool c_3 = 1; + int32_t c_4 = 0; + int32_t c_5 = 1; + int32_t c_6 = 10; + l_1 = START(l_35); + l_2 = END(l_1); + l_3 = LOOP_BEGIN(l_2, l_30); + int32_t d_4 = PHI(l_3, c_4, d_29); + int32_t d_5 = PHI(l_3, c_4, d_12); + bool d_6 = LT(d_4, c_6); + l_7 = IF(l_3, d_6); + l_8 = IF_TRUE(l_7); + l_9 = END(l_8); + l_10 = LOOP_BEGIN(l_9, l_26); + int32_t d_11 = PHI(l_10, c_4, d_25); + int32_t d_12 = PHI(l_10, d_5, d_24); + bool d_13 = LT(d_11, c_6); + l_14 = IF(l_10, d_13); + l_15 = IF_TRUE(l_14); + bool d_16 = NE(d_11, d_4); + l_17 = IF(l_15, d_16); + l_18 = IF_TRUE(l_17); + int32_t d_19 = ADD(d_12, c_5); + l_20 = END(l_18); + l_21 = IF_FALSE(l_17); + l_22 = END(l_21); + l_23 = MERGE(l_20, l_22); + int32_t d_24 = PHI(l_23, d_19, d_12); + int32_t d_25 = ADD(d_11, c_5); + l_26 = LOOP_END(l_23, l_10); + l_27 = IF_FALSE(l_14); + int32_t d_29 = ADD(d_4, c_5); + l_30 = LOOP_END(l_27, l_3); + l_31 = IF_FALSE(l_7); + l_35 = RETURN(l_31, d_5); +} +--EXPECT-- +test: + xorl %ecx, %ecx + xorl %eax, %eax +.L1: + cmpl $0xa, %ecx + jge .L5 + xorl %edx, %edx +.L2: + cmpl $0xa, %edx + jge .L4 + cmpl %ecx, %edx + je .L3 + leal 1(%eax), %eax +.L3: + leal 1(%edx), %edx + jmp .L2 +.L4: + leal 1(%ecx), %ecx + jmp .L1 +.L5: + retl diff --git a/tests/debug.x86/memop_001.irt b/tests/debug.x86/memop_001.irt new file mode 100644 index 0000000..85e45e4 --- /dev/null +++ b/tests/debug.x86/memop_001.irt @@ -0,0 +1,26 @@ +--TEST-- +001: Memory update (binary op with const) +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + int32_t c = 0x80; + l_1 = START(l_5); + int32_t y = PARAM(l_1, "y", 1); + int32_t v = VAR(l_1, "_spill_"); + l_2 = VSTORE(l_1, v, y); + int32_t z, l_3 = VLOAD(l_2, v); + int32_t ret = AND(z, c); + l_4 = VSTORE(l_3, v, ret); + l_5 = RETURN(l_4); +} +--EXPECT-- +test: + subl $4, %esp + movl 8(%esp), %eax + movl %eax, (%esp) + andl $0x80, (%esp) + addl $4, %esp + retl diff --git a/tests/debug.x86/memop_002.irt b/tests/debug.x86/memop_002.irt new file mode 100644 index 0000000..c5b1614 --- /dev/null +++ b/tests/debug.x86/memop_002.irt @@ -0,0 +1,26 @@ +--TEST-- +002: Memory update (binary op with reg) +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + int32_t c = 0x80; + l_1 = START(l_5); + int32_t y = PARAM(l_1, "y", 1); + int32_t v = VAR(l_1, "_spill_"); + l_2 = VSTORE(l_1, v, y); + int32_t z, l_3 = VLOAD(l_2, v); + int32_t ret = AND(z, y); + l_4 = VSTORE(l_3, v, ret); + l_5 = RETURN(l_4); +} +--EXPECT-- +test: + subl $4, %esp + movl 8(%esp), %eax + movl %eax, (%esp) + andl %eax, (%esp) + addl $4, %esp + retl diff --git a/tests/debug.x86/memop_003.irt b/tests/debug.x86/memop_003.irt new file mode 100644 index 0000000..025af3e --- /dev/null +++ b/tests/debug.x86/memop_003.irt @@ -0,0 +1,28 @@ +--TEST-- +003: Memory update (binary op with reg + swap) +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + int32_t c = 0x80; + l_1 = START(l_5); + int32_t y = PARAM(l_1, "y", 1); + int32_t v = VAR(l_1, "_spill_"); + l_2 = VSTORE(l_1, v, y); + int32_t z, l_3 = VLOAD(l_2, v); + int32_t y2 = ADD(y, y); + int32_t ret = AND(y2, z); + l_4 = VSTORE(l_3, v, ret); + l_5 = RETURN(l_4); +} +--EXPECT-- +test: + subl $4, %esp + movl 8(%esp), %eax + movl %eax, (%esp) + leal (%eax, %eax), %eax + andl %eax, (%esp) + addl $4, %esp + retl diff --git a/tests/debug.x86/memop_004.irt b/tests/debug.x86/memop_004.irt new file mode 100644 index 0000000..80dd579 --- /dev/null +++ b/tests/debug.x86/memop_004.irt @@ -0,0 +1,26 @@ +--TEST-- +004: Memory update (inc/dec) +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + int8_t c = 1; + l_1 = START(l_5); + int8_t y = PARAM(l_1, "y", 1); + int8_t v = VAR(l_1, "_spill_"); + l_2 = VSTORE(l_1, v, y); + int8_t z, l_3 = VLOAD(l_2, v); + int8_t ret = ADD(z, c); + l_4 = VSTORE(l_3, v, ret); + l_5 = RETURN(l_4); +} +--EXPECT-- +test: + subl $4, %esp + movb 8(%esp), %al + movb %al, (%esp) + incb (%esp) + addl $4, %esp + retl diff --git a/tests/debug.x86/memop_005.irt b/tests/debug.x86/memop_005.irt new file mode 100644 index 0000000..ae4008d --- /dev/null +++ b/tests/debug.x86/memop_005.irt @@ -0,0 +1,26 @@ +--TEST-- +005: Memory update (mul pwr2) +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + int32_t c = 16; + l_1 = START(l_5); + int32_t y = PARAM(l_1, "y", 1); + int32_t v = VAR(l_1, "_spill_"); + l_2 = VSTORE(l_1, v, y); + int32_t z, l_3 = VLOAD(l_2, v); + int32_t ret = MUL(z, c); + l_4 = VSTORE(l_3, v, ret); + l_5 = RETURN(l_4); +} +--EXPECT-- +test: + subl $4, %esp + movl 8(%esp), %eax + movl %eax, (%esp) + shll $4, (%esp) + addl $4, %esp + retl diff --git a/tests/debug.x86/memop_006.irt b/tests/debug.x86/memop_006.irt new file mode 100644 index 0000000..d5b3eb8 --- /dev/null +++ b/tests/debug.x86/memop_006.irt @@ -0,0 +1,25 @@ +--TEST-- +006: Memory update (shift) +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + l_1 = START(l_5); + int32_t y = PARAM(l_1, "y", 1); + int32_t v = VAR(l_1, "_spill_"); + l_2 = VSTORE(l_1, v, y); + int32_t z, l_3 = VLOAD(l_2, v); + int32_t ret = SHL(z, y); + l_4 = VSTORE(l_3, v, ret); + l_5 = RETURN(l_4); +} +--EXPECT-- +test: + subl $4, %esp + movl 8(%esp), %ecx + movl %ecx, (%esp) + shll %cl, (%esp) + addl $4, %esp + retl diff --git a/tests/debug.x86/memop_007.irt b/tests/debug.x86/memop_007.irt new file mode 100644 index 0000000..cf209d0 --- /dev/null +++ b/tests/debug.x86/memop_007.irt @@ -0,0 +1,26 @@ +--TEST-- +007: Memory update (shift const) +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + int32_t c = 3; + l_1 = START(l_5); + int32_t y = PARAM(l_1, "y", 1); + int32_t v = VAR(l_1, "_spill_"); + l_2 = VSTORE(l_1, v, y); + int32_t z, l_3 = VLOAD(l_2, v); + int32_t ret = SHL(z, c); + l_4 = VSTORE(l_3, v, ret); + l_5 = RETURN(l_4); +} +--EXPECT-- +test: + subl $4, %esp + movl 8(%esp), %eax + movl %eax, (%esp) + shll $3, (%esp) + addl $4, %esp + retl diff --git a/tests/debug.x86/memop_008.irt b/tests/debug.x86/memop_008.irt new file mode 100644 index 0000000..1e69b87 --- /dev/null +++ b/tests/debug.x86/memop_008.irt @@ -0,0 +1,21 @@ +--TEST-- +008: Memory update (LOAD/STORE) +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + int32_t c = 0x80; + l_1 = START(l_4); + uintptr_t p = PARAM(l_1, "p", 1); + int32_t z, l_2 = LOAD(l_1, p); + int32_t ret = AND(z, c); + l_3 = STORE(l_2, p, ret); + l_4 = RETURN(l_3); +} +--EXPECT-- +test: + movl 4(%esp), %eax + andl $0x80, (%eax) + retl diff --git a/tests/debug.x86/params_001.irt b/tests/debug.x86/params_001.irt new file mode 100644 index 0000000..32afc8d --- /dev/null +++ b/tests/debug.x86/params_001.irt @@ -0,0 +1,59 @@ +--TEST-- +001: Parameter Loading +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + l_1 = START(l_2); + int32_t p_1 = PARAM(l_1, "p_1", 1); + int32_t p_2 = PARAM(l_1, "p_2", 1); + int32_t p_3 = PARAM(l_1, "p_3", 1); + int32_t p_4 = PARAM(l_1, "p_4", 1); + int32_t p_5 = PARAM(l_1, "p_5", 1); + int32_t p_6 = PARAM(l_1, "p_6", 1); + int32_t p_7 = PARAM(l_1, "p_7", 1); + int32_t p_8 = PARAM(l_1, "p_8", 1); + int32_t p_9 = PARAM(l_1, "p_9", 1); + int32_t p_10 = PARAM(l_1, "p_10", 1); + int32_t r1 = ADD(p_1, p_2); + int32_t r2 = ADD(r1, p_3); + int32_t r3 = ADD(r2, p_4); + int32_t r4 = ADD(r3, p_5); + int32_t r5 = ADD(r4, p_6); + int32_t r6 = ADD(r5, p_7); + int32_t r7 = ADD(r6, p_8); + int32_t r8 = ADD(r7, p_9); + int32_t ret = SUB(r8, p_10); + l_2 = RETURN(l_1, ret); +} +--EXPECT-- +test: + subl $0x10, %esp + movl %ebx, 0xc(%esp) + movl %ebp, 8(%esp) + movl %esi, 4(%esp) + movl %edi, (%esp) + movl 0x14(%esp), %eax + movl 0x18(%esp), %ecx + movl 0x1c(%esp), %edx + movl 0x20(%esp), %ebx + movl 0x24(%esp), %ebp + movl 0x28(%esp), %esi + movl 0x34(%esp), %edi + leal (%ecx, %eax), %eax + leal (%eax, %edx), %eax + leal (%eax, %ebx), %eax + leal (%eax, %ebp), %eax + leal (%eax, %esi), %eax + leal (%eax, %ecx), %eax + leal (%eax, %ecx), %eax + leal (%eax, %edi), %eax + subl 0x38(%esp), %eax + movl 0xc(%esp), %ebx + movl 8(%esp), %ebp + movl 4(%esp), %esi + movl (%esp), %edi + addl $0x10, %esp + retl diff --git a/tests/debug.x86/params_002.irt b/tests/debug.x86/params_002.irt new file mode 100644 index 0000000..c6640a5 --- /dev/null +++ b/tests/debug.x86/params_002.irt @@ -0,0 +1,47 @@ +--TEST-- +002: Parameter Loading +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + l_1 = START(l_2); + double p_1 = PARAM(l_1, "p_1", 1); + double p_2 = PARAM(l_1, "p_2", 1); + double p_3 = PARAM(l_1, "p_3", 1); + double p_4 = PARAM(l_1, "p_4", 1); + double p_5 = PARAM(l_1, "p_5", 1); + double p_6 = PARAM(l_1, "p_6", 1); + double p_7 = PARAM(l_1, "p_7", 1); + double p_8 = PARAM(l_1, "p_8", 1); + double p_9 = PARAM(l_1, "p_9", 1); + double p_10 = PARAM(l_1, "p_10", 1); + double r1 = ADD(p_1, p_2); + double r2 = ADD(r1, p_3); + double r3 = ADD(r2, p_4); + double r4 = ADD(r3, p_5); + double r5 = ADD(r4, p_6); + double r6 = ADD(r5, p_7); + double r7 = ADD(r6, p_8); + double r8 = ADD(r7, p_9); + double ret = SUB(r8, p_10); + l_2 = RETURN(l_1, ret); +} +--EXPECT-- +test: + subl $8, %esp + movsd 0x14(%esp), %xmm0 + addsd 0xc(%esp), %xmm0 + addsd 0x1c(%esp), %xmm0 + addsd 0x24(%esp), %xmm0 + addsd 0x2c(%esp), %xmm0 + addsd 0x34(%esp), %xmm0 + addsd 0x3c(%esp), %xmm0 + addsd 0x44(%esp), %xmm0 + addsd 0x4c(%esp), %xmm0 + subsd 0x54(%esp), %xmm0 + movsd %xmm0, (%esp) + fldl (%esp) + addl $8, %esp + retl diff --git a/tests/debug.x86/params_003.irt b/tests/debug.x86/params_003.irt new file mode 100644 index 0000000..3031615 --- /dev/null +++ b/tests/debug.x86/params_003.irt @@ -0,0 +1,57 @@ +--TEST-- +003: Parameter Loading and argument passing +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + uintptr_t f = func(printf); + uintptr_t fmt = "%d %d %d %d %d %d %d %d %d %d\n"; + l_1 = START(l_3); + int32_t p_1 = PARAM(l_1, "p_1", 1); + int32_t p_2 = PARAM(l_1, "p_2", 2); + int32_t p_3 = PARAM(l_1, "p_3", 3); + int32_t p_4 = PARAM(l_1, "p_4", 4); + int32_t p_5 = PARAM(l_1, "p_5", 5); + int32_t p_6 = PARAM(l_1, "p_6", 6); + int32_t p_7 = PARAM(l_1, "p_7", 7); + int32_t p_8 = PARAM(l_1, "p_8", 8); + int32_t p_9 = PARAM(l_1, "p_9", 9); + int32_t p_10 = PARAM(l_1, "p_10", 10); + int32_t ret, l_2 = CALL/11(l_1, f, fmt, p_1, p_2, p_3, p_4, p_5, p_6, p_7, p_8, p_9, p_10); + l_3 = RETURN(l_2, ret); +} +--EXPECT-- +test: + subl $0x2c, %esp + leal .L1, %eax + movl %eax, (%esp) + movl 0x30(%esp), %eax + movl %eax, 4(%esp) + movl 0x34(%esp), %eax + movl %eax, 8(%esp) + movl 0x38(%esp), %eax + movl %eax, 0xc(%esp) + movl 0x3c(%esp), %eax + movl %eax, 0x10(%esp) + movl 0x40(%esp), %eax + movl %eax, 0x14(%esp) + movl 0x44(%esp), %eax + movl %eax, 0x18(%esp) + movl 0x48(%esp), %eax + movl %eax, 0x1c(%esp) + movl 0x4c(%esp), %eax + movl %eax, 0x20(%esp) + movl 0x50(%esp), %eax + movl %eax, 0x24(%esp) + movl 0x54(%esp), %eax + movl %eax, 0x28(%esp) + calll printf + addl $0x2c, %esp + retl +.rodata + .db 0x90, 0x90, 0x90 +.L1: + .db 0x25, 0x64, 0x20, 0x25, 0x64, 0x20, 0x25, 0x64, 0x20, 0x25, 0x64, 0x20, 0x25, 0x64, 0x20, 0x25 + .db 0x64, 0x20, 0x25, 0x64, 0x20, 0x25, 0x64, 0x20, 0x25, 0x64, 0x20, 0x25, 0x64, 0x0a, 0x00 diff --git a/tests/debug.x86/regset-fib.irt b/tests/debug.x86/regset-fib.irt new file mode 100644 index 0000000..f62b956 --- /dev/null +++ b/tests/debug.x86/regset-fib.irt @@ -0,0 +1,137 @@ +--TEST-- +Fib +--TARGET-- +x86 +--ARGS-- +--debug-regset 0x3ff --save --dump-live-ranges -S --run +--CODE-- +{ + int32_t zero = 0; + double c_0 = 0; + double c_1 = 1; + double c_10000 = 10000; + uintptr_t f = func(printf); + uintptr_t format = "%g\n"; + l_1 = START(l_6); + double lo_1 = COPY(c_0); + double hi_1 = COPY(c_1); + l_2 = END(l_1); + l_3 = LOOP_BEGIN(l_2, l_9); + double lo_2 = PHI(l_3, lo_1, lo_3); + double hi_2 = PHI(l_3, hi_1, hi_3); + bool b = LT(hi_2, c_10000); + l_4 = IF(l_3, b); + l_7 = IF_TRUE(l_4); + double hi_3 = ADD(hi_2, lo_2); + double lo_3 = SUB(hi_3, lo_2); + l_8 = CALL/2(l_7, f, format, lo_3); +# ll = CALL/2(l_7, f, format, lo_3); +# l_8 = CALL/2(ll, f, format, lo_3); + l_9 = LOOP_END(l_8, l_3); + l_5 = IF_FALSE(l_4); + l_6 = RETURN(l_5, zero); +} +--EXPECT-- +{ + uintptr_t c_1 = 0; + bool c_2 = 0; + bool c_3 = 1; + int32_t c_4 = 0; + double c_5 = 0; + double c_6 = 1; + double c_7 = 10000; + uintptr_t c_8 = func(printf); + uintptr_t c_9 = "%g\n"; + l_1 = START(l_15); + l_2 = END(l_1); + l_3 = LOOP_BEGIN(l_2, l_13); + double d_4 = PHI(l_3, c_5, d_10); + double d_5 = PHI(l_3, c_6, d_9); + bool d_6 = GT(c_7, d_5); + l_7 = IF(l_3, d_6); + l_8 = IF_TRUE(l_7); + double d_9 = ADD(d_5, d_4); + double d_10 = SUB(d_9, d_4); + l_11 = CALL/2(l_8, c_8, c_9, d_10); + l_13 = LOOP_END(l_11, l_3); + l_14 = IF_FALSE(l_7); + l_15 = RETURN(l_14, c_4); +} +{ # LIVE-RANGES (vregs_count=3) +TMP + [%xmm0]: [2.2-2.3) + [%xmm1]: [6.0-6.2) + [%eax]: [11.0-11.1) + [%xmm0]: [13.2-13.3) +R1 (d_4) [SPILL=0x0] + [%xmm1]: [3.0-6.0), DEF(4.2) + : [6.0-8.0) + [%xmm1]: [8.0-10.1), USE(9.1/2), USE(10.1/2) +R2 (d_5, d_9) [SPILL=0x8] + [%xmm0]: [3.0-10.0), DEF(5.2), USE(6.1/2), USE(9.0/1)!, DEF(9.0)!, DEF(9.2)!, USE(10.0/1, hint=R3)! + : [10.0-14.0), PHI_USE(13.2, phi=d_5/3) +R3 (d_10) [SPILL=0x10] + [%xmm0]: [10.0-11.1), DEF(10.0, hint=R2)!, DEF(10.2)!, USE(11.1/4) + : [11.1-14.0), PHI_USE(13.2, phi=d_4/3) +[%eax] : [15.0-15.1) +[%SCRATCH] : [11.1-11.2) +} +test: + subl $0x2c, %esp + xorpd %xmm1, %xmm1 + movsd %xmm1, 0xc(%esp) + movsd .L3, %xmm0 + movsd %xmm0, 0x14(%esp) +.L1: + movsd .L4, %xmm1 + ucomisd 0x14(%esp), %xmm1 + jbe .L2 + movsd 0x14(%esp), %xmm0 + addsd 0xc(%esp), %xmm0 + movsd %xmm0, 0x14(%esp) + movsd 0x14(%esp), %xmm0 + subsd 0xc(%esp), %xmm0 + movsd %xmm0, 0x1c(%esp) + leal .L5, %eax + movl %eax, (%esp) + movsd 0x1c(%esp), %xmm0 + movsd %xmm0, 4(%esp) + calll printf + movsd 0x1c(%esp), %xmm1 + movsd %xmm1, 0xc(%esp) + jmp .L1 +.L2: + xorl %eax, %eax + addl $0x2c, %esp + retl +.rodata + .db 0x90, 0x90, 0x90 +.L3: + .db 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x3f +.L4: + .db 0x00, 0x00, 0x00, 0x00, 0x00, 0x88, 0xc3, 0x40 +.L5: + .db 0x25, 0x67, 0x0a, 0x00 + +1 +1 +2 +3 +5 +8 +13 +21 +34 +55 +89 +144 +233 +377 +610 +987 +1597 +2584 +4181 +6765 + +exit code = 0 diff --git a/tests/debug.x86/regset-fib2.irt b/tests/debug.x86/regset-fib2.irt new file mode 100644 index 0000000..5e3128b --- /dev/null +++ b/tests/debug.x86/regset-fib2.irt @@ -0,0 +1,163 @@ +--TEST-- +Fib2 +--TARGET-- +x86 +--ARGS-- +--debug-regset 0x3ff --save --dump-live-ranges -S --run +--CODE-- +{ + int32_t zero = 0; + double c_0 = 0; + double c_1 = 1; + double c_10000 = 10000; + uintptr_t f = func(printf); + uintptr_t format = "%g\n"; + l_1 = START(l_6); + double lo_1 = COPY(c_0); + double hi_1 = COPY(c_1); + l_2 = END(l_1); + l_3 = LOOP_BEGIN(l_2, l_9); + double lo_2 = PHI(l_3, lo_1, lo_3); + double hi_2 = PHI(l_3, hi_1, hi_3); + bool b = LT(hi_2, c_10000); + l_4 = IF(l_3, b); + l_7 = IF_TRUE(l_4); + double hi_3 = ADD(hi_2, lo_2); + double lo_3 = SUB(hi_3, lo_2); + ll = CALL/2(l_7, f, format, lo_3); + l_8 = CALL/2(ll, f, format, lo_3); + l_9 = LOOP_END(l_8, l_3); + l_5 = IF_FALSE(l_4); + l_6 = RETURN(l_5, zero); +} +--EXPECT-- +{ + uintptr_t c_1 = 0; + bool c_2 = 0; + bool c_3 = 1; + int32_t c_4 = 0; + double c_5 = 0; + double c_6 = 1; + double c_7 = 10000; + uintptr_t c_8 = func(printf); + uintptr_t c_9 = "%g\n"; + l_1 = START(l_17); + l_2 = END(l_1); + l_3 = LOOP_BEGIN(l_2, l_15); + double d_4 = PHI(l_3, c_5, d_10); + double d_5 = PHI(l_3, c_6, d_9); + bool d_6 = GT(c_7, d_5); + l_7 = IF(l_3, d_6); + l_8 = IF_TRUE(l_7); + double d_9 = ADD(d_5, d_4); + double d_10 = SUB(d_9, d_4); + l_11 = CALL/2(l_8, c_8, c_9, d_10); + l_13 = CALL/2(l_11, c_8, c_9, d_10); + l_15 = LOOP_END(l_13, l_3); + l_16 = IF_FALSE(l_7); + l_17 = RETURN(l_16, c_4); +} +{ # LIVE-RANGES (vregs_count=3) +TMP + [%xmm0]: [2.2-2.3) + [%xmm1]: [6.0-6.2) + [%eax]: [11.0-11.1) + [%eax]: [13.0-13.1) + [%xmm0]: [15.2-15.3) +R1 (d_4) [SPILL=0x0] + [%xmm1]: [3.0-6.0), DEF(4.2) + : [6.0-8.0) + [%xmm1]: [8.0-10.1), USE(9.1/2), USE(10.1/2) +R2 (d_5, d_9) [SPILL=0x8] + [%xmm0]: [3.0-10.0), DEF(5.2), USE(6.1/2), USE(9.0/1)!, DEF(9.0)!, DEF(9.2)!, USE(10.0/1, hint=R3)! + : [10.0-16.0), PHI_USE(15.2, phi=d_5/3) +R3 (d_10) [SPILL=0x10] + [%xmm0]: [10.0-11.1), DEF(10.0, hint=R2)!, DEF(10.2)!, USE(11.1/4) + : [11.1-16.0), USE(13.1/4), PHI_USE(15.2, phi=d_4/3) +[%eax] : [17.0-17.1) +[%SCRATCH] : [11.1-11.2), [13.1-13.2) +} +test: + subl $0x2c, %esp + xorpd %xmm1, %xmm1 + movsd %xmm1, 0xc(%esp) + movsd .L3, %xmm0 + movsd %xmm0, 0x14(%esp) +.L1: + movsd .L4, %xmm1 + ucomisd 0x14(%esp), %xmm1 + jbe .L2 + movsd 0x14(%esp), %xmm0 + addsd 0xc(%esp), %xmm0 + movsd %xmm0, 0x14(%esp) + movsd 0x14(%esp), %xmm0 + subsd 0xc(%esp), %xmm0 + movsd %xmm0, 0x1c(%esp) + leal .L5, %eax + movl %eax, (%esp) + movsd 0x1c(%esp), %xmm0 + movsd %xmm0, 4(%esp) + calll printf + leal .L5, %eax + movl %eax, (%esp) + movsd 0x1c(%esp), %xmm7 + movsd %xmm7, 4(%esp) + calll printf + movsd 0x1c(%esp), %xmm1 + movsd %xmm1, 0xc(%esp) + jmp .L1 +.L2: + xorl %eax, %eax + addl $0x2c, %esp + retl +.rodata + .db 0x90 +.L3: + .db 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x3f +.L4: + .db 0x00, 0x00, 0x00, 0x00, 0x00, 0x88, 0xc3, 0x40 +.L5: + .db 0x25, 0x67, 0x0a, 0x00 + +1 +1 +1 +1 +2 +2 +3 +3 +5 +5 +8 +8 +13 +13 +21 +21 +34 +34 +55 +55 +89 +89 +144 +144 +233 +233 +377 +377 +610 +610 +987 +987 +1597 +1597 +2584 +2584 +4181 +4181 +6765 +6765 + +exit code = 0 diff --git a/tests/debug.x86/regset-fibi.irt b/tests/debug.x86/regset-fibi.irt new file mode 100644 index 0000000..6b75bcb --- /dev/null +++ b/tests/debug.x86/regset-fibi.irt @@ -0,0 +1,117 @@ +--TEST-- +FibI +--TARGET-- +x86 +--ARGS-- +--save --dump-live-ranges -S --run +--CODE-- +{ + int32_t c_0 = 0; + int32_t c_1 = 1; + int32_t c_10000 = 10000; + uintptr_t f = func(printf); + uintptr_t format = "%d\n"; + l_1 = START(l_6); + int32_t lo_1 = COPY(c_0); + int32_t hi_1 = COPY(c_1); + l_2 = END(l_1); + l_3 = LOOP_BEGIN(l_2, l_9); + int32_t lo_2 = PHI(l_3, lo_1, lo_3); + int32_t hi_2 = PHI(l_3, hi_1, hi_3); + bool b = LT(hi_2, c_10000); + l_4 = IF(l_3, b); + l_7 = IF_TRUE(l_4); + int32_t hi_3 = ADD(hi_2, lo_2); + int32_t lo_3 = SUB(hi_3, lo_2); + l_8 = CALL/2(l_7, f, format, lo_3); + l_9 = LOOP_END(l_8, l_3); + l_5 = IF_FALSE(l_4); + l_6 = RETURN(l_5, c_0); +} +--EXPECT-- +{ + uintptr_t c_1 = 0; + bool c_2 = 0; + bool c_3 = 1; + int32_t c_4 = 0; + int32_t c_5 = 1; + int32_t c_6 = 10000; + uintptr_t c_7 = func(printf); + uintptr_t c_8 = "%d\n"; + l_1 = START(l_15); + l_2 = END(l_1); + l_3 = LOOP_BEGIN(l_2, l_13); + int32_t d_4 = PHI(l_3, c_4, d_10); + int32_t d_5 = PHI(l_3, c_5, d_9); + bool d_6 = LT(d_5, c_6); + l_7 = IF(l_3, d_6); + l_8 = IF_TRUE(l_7); + int32_t d_9 = ADD(d_5, d_4); + int32_t d_10 = SUB(d_9, d_4); + l_11 = CALL/2(l_8, c_7, c_8, d_10); + l_13 = LOOP_END(l_11, l_3); + l_14 = IF_FALSE(l_7); + l_15 = RETURN(l_14, c_4); +} +{ # LIVE-RANGES (vregs_count=3) +TMP + [%eax]: [2.2-2.3) + [%eax]: [11.0-11.1) + [%eax]: [13.2-13.3) +R1 (d_4) [%eax]: [3.0-10.1), DEF(4.2), USE(9.1/2)!, USE(10.1/2) +R2 (d_5, d_9) [%ebx]: [3.0-9.1), [9.2-14.0), DEF(5.2), USE(6.1/1), USE(9.1/1)!, DEF(9.2)!, USE(10.0/1, hint=R3)!, PHI_USE(13.2, phi=d_5/3) +R3 (d_10) [%ebp]: [10.0-14.0), DEF(10.0, hint=R2)!, DEF(10.2)!, USE(11.1/4), PHI_USE(13.2, phi=d_4/3) +[%eax] : [15.0-15.1) +[%SCRATCH] : [11.1-11.2) +} +test: + subl $0x1c, %esp + movl %ebx, 0x18(%esp) + movl %ebp, 0x14(%esp) + xorl %eax, %eax + movl $1, %ebx +.L1: + cmpl $0x2710, %ebx + jge .L2 + leal (%ebx, %eax), %ebx + movl %ebx, %ebp + subl %eax, %ebp + leal .L3, %eax + movl %eax, (%esp) + movl %ebp, 4(%esp) + calll printf + movl %ebp, %eax + jmp .L1 +.L2: + xorl %eax, %eax + movl 0x18(%esp), %ebx + movl 0x14(%esp), %ebp + addl $0x1c, %esp + retl +.rodata + .db 0x90, 0x90, 0x90 +.L3: + .db 0x25, 0x64, 0x0a, 0x00 + +1 +1 +2 +3 +5 +8 +13 +21 +34 +55 +89 +144 +233 +377 +610 +987 +1597 +2584 +4181 +6765 + +exit code = 0 diff --git a/tests/debug.x86/regset-test.irt b/tests/debug.x86/regset-test.irt new file mode 100644 index 0000000..f9fbb73 --- /dev/null +++ b/tests/debug.x86/regset-test.irt @@ -0,0 +1,181 @@ +--TEST-- +Test +--TARGET-- +x86 +--ARGS-- +--debug-regset 0x3ff --save --dump-live-ranges -S +--CODE-- +{ + uintptr_t c_1 = 0; + bool c_2 = 0; + bool c_3 = 1; + double c_4 = 0.5; + double c_5 = 0; + int32_t c_6 = 0; + int32_t c_7 = 1; + double c_8 = 16; + int32_t c_9 = 1000; + l_1 = START(l_35); + double d_2 = PARAM(l_1, "x", 0); + double d_3 = PARAM(l_1, "y", 1); + double d_4 = VAR(l_1, "cr"); + double d_5 = SUB(d_3, c_4); + double d_6 = VAR(l_1, "ci"); + double d_7 = VAR(l_1, "zi"); + double d_8 = VAR(l_1, "zr"); + int32_t d_9 = VAR(l_1, "i"); + l_10 = END(l_1); + l_11 = LOOP_BEGIN(l_10, l_37); + double d_12 = PHI(l_11, c_5, d_25); + double d_13 = PHI(l_11, c_5, d_23); + int32_t d_14 = PHI(l_11, c_6, d_15); + int32_t d_15 = ADD(d_14, c_7); + double d_16 = VAR(l_11, "temp"); + double d_17 = MUL(d_13, d_12); + double d_18 = VAR(l_11, "zr2"); + double d_19 = MUL(d_13, d_13); + double d_20 = VAR(l_11, "zi2"); + double d_21 = MUL(d_12, d_12); + double d_22 = SUB(d_19, d_21); + double d_23 = ADD(d_22, d_5); + double d_24 = ADD(d_17, d_17); + double d_25 = ADD(d_24, d_2); + double d_26 = ADD(d_21, d_19); + bool d_27 = GT(d_26, c_8); + l_28 = IF(l_11, d_27); + l_29 = IF_TRUE(l_28); + l_30 = RETURN(l_29, d_15); + l_31 = IF_FALSE(l_28); + bool d_32 = GT(d_15, c_9); + l_33 = IF(l_31, d_32); + l_34 = IF_TRUE(l_33); + l_35 = RETURN(l_34, c_6, l_30); + l_36 = IF_FALSE(l_33); + l_37 = LOOP_END(l_36, l_11); +} +--EXPECT-- +{ + uintptr_t c_1 = 0; + bool c_2 = 0; + bool c_3 = 1; + double c_4 = 0.5; + double c_5 = 0; + int32_t c_6 = 0; + int32_t c_7 = 1; + double c_8 = 16; + int32_t c_9 = 1000; + l_1 = START(l_30); + double d_2 = PARAM(l_1, "x", 0); + double d_3 = PARAM(l_1, "y", 1); + double d_4 = VAR(l_1, "cr"); + double d_5 = SUB(d_3, c_4); + double d_6 = VAR(l_1, "ci"); + double d_7 = VAR(l_1, "zi"); + double d_8 = VAR(l_1, "zr"); + int32_t d_9 = VAR(l_1, "i"); + l_10 = END(l_1); + l_11 = LOOP_BEGIN(l_10, l_37); + double d_12 = PHI(l_11, c_5, d_36); + double d_13 = PHI(l_11, c_5, d_34); + int32_t d_14 = PHI(l_11, c_6, d_15); + int32_t d_15 = ADD(d_14, c_7); + double d_16 = VAR(l_11, "temp"); + double d_17 = VAR(l_11, "zr2"); + double d_18 = MUL(d_13, d_13); + double d_19 = VAR(l_11, "zi2"); + double d_20 = MUL(d_12, d_12); + double d_21 = ADD(d_20, d_18); + bool d_22 = GT(d_21, c_8); + l_23 = IF(l_11, d_22); + l_24 = IF_TRUE(l_23); + l_25 = RETURN(l_24, d_15); + l_26 = IF_FALSE(l_23); + bool d_27 = GT(d_15, c_9); + l_28 = IF(l_26, d_27); + l_29 = IF_TRUE(l_28); + l_30 = RETURN(l_29, c_6, l_25); + l_31 = IF_FALSE(l_28); + double d_32 = MUL(d_12, d_13); + double d_33 = SUB(d_18, d_20); + double d_34 = ADD(d_33, d_5); + double d_35 = ADD(d_32, d_32); + double d_36 = ADD(d_35, d_2); + l_37 = LOOP_END(l_31, l_11); +} +{ # LIVE-RANGES (vregs_count=12) +TMP + [%xmm0]: [10.2-10.3) + [%eax]: [10.2-10.3) +R1 (d_2) + [%xmm0]: [2.2-10.2), DEF(2.2)! + : [10.2-24.0), [26.0-29.0), [31.0-36.0) + : [36.0-38.0), USE(36.1/2) +R2 (d_3) [%xmm1]: [3.2-5.0), DEF(3.2)!, USE(5.0/1, hint=R3)! +R3 (d_5) [SPILL=0x0] + [%xmm1]: [5.0-10.2), DEF(5.0, hint=R2)!, DEF(5.2)! + : [10.2-24.0), [26.0-29.0), [31.0-34.0) + : [34.0-38.0), USE(34.1/2) +R4 (d_12, d_36) [%xmm1]: [11.0-24.0), [26.0-29.0), [31.0-32.0), [36.0-38.0), DEF(12.2), USE(20.0/1, hint=R8)!, USE(20.0/2), USE(32.0/1)!, DEF(36.0, hint=R12)!, DEF(36.2)!, PHI_USE(37.2, phi=d_12/3) +R5 (d_13, d_34) [SPILL=0x8] + [%xmm0]: [11.0-18.0), DEF(13.2), USE(18.0/1, hint=R7)!, USE(18.0/2) + : [18.0-24.0), [26.0-29.0), [31.0-32.0) + [%xmm0]: [32.0-32.1), [34.0-38.0), USE(32.1/2, hint=R10), DEF(34.0, hint=R11)!, DEF(34.2)!, PHI_USE(37.2, phi=d_13/3) +R6 (d_14, d_15) [%eax]: [11.0-15.1), [15.2-25.0), [26.0-29.0), [31.0-38.0), DEF(14.2), USE(15.1/1)!, DEF(15.2)!, USE(25.0/2, hint=%eax), USE(27.1/1), PHI_USE(37.2, phi=d_14/3) +R7 (d_18) [SPILL=0x10] + [%xmm0]: [18.0-20.0), DEF(18.0, hint=R5)!, DEF(18.2)! + : [20.0-21.0) + : [21.0-24.0), [26.0-29.0), [31.0-32.3), USE(21.1/2) + [%xmm0]: [32.3-33.0), USE(33.0/1, hint=R11)! +R8 (d_20) [SPILL=0x18] + [%xmm0]: [20.0-21.0), DEF(20.0, hint=R4)!, DEF(20.2)!, USE(21.0/1, hint=R9)! + : [21.0-24.0), [26.0-29.0), [31.0-33.0) + : [33.0-33.1), USE(33.1/2) +R9 (d_21) [%xmm0]: [21.0-22.1), DEF(21.0, hint=R8)!, DEF(21.2)!, USE(22.1/1)! +R10 (d_32) [%xmm1]: [32.0-35.0), DEF(32.0, hint=R4)!, DEF(32.2)!, USE(35.0/1, hint=R12)!, USE(35.0/2) +R11 (d_33) [%xmm0]: [33.0-34.0), DEF(33.0, hint=R7)!, DEF(33.2)!, USE(34.0/1, hint=R5)! +R12 (d_35) [%xmm1]: [35.0-36.0), DEF(35.0, hint=R10)!, DEF(35.2)!, USE(36.0/1, hint=R4)! +[%eax] : [25.0-25.1), [30.0-30.1) +} +test: + subl $0x20, %esp + movsd 0x2c(%esp), %xmm1 + subsd .L4, %xmm1 + movsd %xmm1, (%esp) + xorpd %xmm1, %xmm1 + xorpd %xmm0, %xmm0 + movsd %xmm0, 8(%esp) + xorl %eax, %eax +.L1: + leal 1(%eax), %eax + movsd 8(%esp), %xmm0 + mulsd %xmm0, %xmm0 + movsd %xmm0, 0x10(%esp) + movapd %xmm1, %xmm0 + mulsd %xmm1, %xmm0 + movsd %xmm0, 0x18(%esp) + movsd 0x18(%esp), %xmm0 + addsd 0x10(%esp), %xmm0 + ucomisd .L5, %xmm0 + ja .L2 + cmpl $0x3e8, %eax + jg .L3 + mulsd 8(%esp), %xmm1 + movsd 0x10(%esp), %xmm0 + subsd 0x18(%esp), %xmm0 + addsd (%esp), %xmm0 + movsd %xmm0, 8(%esp) + addsd %xmm1, %xmm1 + addsd 0x24(%esp), %xmm1 + jmp .L1 +.L2: + addl $0x20, %esp + retl +.L3: + xorl %eax, %eax + addl $0x20, %esp + retl +.rodata +.L4: + .db 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x3f +.L5: + .db 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x40 diff --git a/tests/debug.x86/sccp_001.irt b/tests/debug.x86/sccp_001.irt new file mode 100644 index 0000000..3cdc2d7 --- /dev/null +++ b/tests/debug.x86/sccp_001.irt @@ -0,0 +1,19 @@ +--TEST-- +SCCP 001 +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + int32_t i_1 = 10; + int32_t i_4 = 4; + l_1 = START(l_2); + int32_t z1 = BSWAP(i_1); + l_2 = RETURN(l_1, z1); +} +--EXPECT-- +test: + movl $0xa, %eax + bswapl %eax + retl diff --git a/tests/debug.x86/sccp_002.irt b/tests/debug.x86/sccp_002.irt new file mode 100644 index 0000000..7ffc17f --- /dev/null +++ b/tests/debug.x86/sccp_002.irt @@ -0,0 +1,82 @@ +--TEST-- +SCCP 002 +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + uintptr_t c_1 = 0; + bool c_2 = 0; + bool c_3 = 1; + int32_t c_4 = 1; + int32_t c_5 = 2; + int32_t c_6 = 3; + int32_t c_7 = 4; + l_1 = START(l_38); + int32_t d_2 = PARAM(l_1, "z", 0); + bool d_3 = PARAM(l_1, "cond", 1); + l_4 = SWITCH(l_1, d_2); + l_5 = CASE_VAL(l_4, c_4); + l_6 = END(l_5); + l_7 = CASE_VAL(l_4, c_5); + l_8 = END(l_7); + l_9 = CASE_VAL(l_4, c_6); + l_10 = END(l_9); + l_11 = CASE_DEFAULT(l_4); + l_12 = END(l_11); + l_13 = LOOP_BEGIN(l_12, l_25); + int32_t d_14 = PHI(l_13, c_4, d_22); + bool d_15 = NE(d_14, c_4); + l_16 = IF(l_13, d_15); + l_17 = IF_TRUE(l_16); + l_18 = END(l_17); + l_19 = IF_FALSE(l_16); + l_20 = END(l_19); + l_21 = MERGE(l_18, l_20); + int32_t d_22 = PHI(l_21, c_5, d_14); + l_23 = IF(l_21, d_3); + l_24 = IF_TRUE(l_23); + l_25 = LOOP_END(l_24, l_13); + l_26 = IF_FALSE(l_23); + bool d_28 = EQ(d_22, c_4); + l_29 = IF(l_26, d_28); + l_30 = IF_TRUE(l_29); + l_31 = RETURN(l_30, d_22); + l_32 = IF_FALSE(l_29); + l_33 = END(l_32); + l_34 = MERGE/4(l_6, l_8, l_10, l_33); + int32_t d_36 = PHI/4(l_34, c_4, c_5, c_6, c_7); + l_38 = RETURN(l_34, d_36, l_31); +} +--EXPECT-- +test: + movl 4(%esp), %eax + movb 8(%esp), %cl + cmpl $3, %eax + jg .L5 + cmpl $1, %eax + jl .L5 + leal -4(, %eax, 4), %eax + jmpl *.L6(%eax) +.L1: + movl $1, %eax +.L2: + retl +.L3: + movl $2, %eax + jmp .L2 +.L4: + movl $3, %eax + jmp .L2 +.L5: + testb %cl, %cl + jne .L5 + movl $1, %eax + retl +.rodata +.align 4 +.L6: + .dword .L1 + .dword .L3 + .dword .L4 diff --git a/tests/debug.x86/swap_001.irt b/tests/debug.x86/swap_001.irt new file mode 100644 index 0000000..1fd2226 --- /dev/null +++ b/tests/debug.x86/swap_001.irt @@ -0,0 +1,28 @@ +--TEST-- +001: Swap operands of commutative instruction +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + l_1 = START(l_5); + double x = PARAM(l_1, "x", 1); + double y = PARAM(l_1, "y", 2); + double v = VAR(l_1, "_spill_"); + l_2 = VSTORE(l_1, v, y); + double z, l_3 = VLOAD(l_2, v); + double ret = ADD(z, x); + l_4 = VSTORE(l_3, v, ret); + l_5 = RETURN(l_4); +} +--EXPECT-- +test: + subl $8, %esp + movsd 0xc(%esp), %xmm0 + movsd 0x14(%esp), %xmm1 + movsd %xmm1, (%esp) + addsd (%esp), %xmm0 + movsd %xmm0, (%esp) + addl $8, %esp + retl diff --git a/tests/debug.x86/swap_002.irt b/tests/debug.x86/swap_002.irt new file mode 100644 index 0000000..99dac36 --- /dev/null +++ b/tests/debug.x86/swap_002.irt @@ -0,0 +1,30 @@ +--TEST-- +002: Swap operands of commutative instruction +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + l_1 = START(l_5); + int32_t x = PARAM(l_1, "x", 1); + int32_t y = PARAM(l_1, "y", 2); + int32_t v = VAR(l_1, "_spill_"); + l_2 = VSTORE(l_1, v, y); + int32_t z, l_3 = VLOAD(l_2, v); + int32_t ret = AND(z, x); + int32_t ret2 = ADD(ret, ret); + l_4 = VSTORE(l_3, v, ret2); + l_5 = RETURN(l_4); +} +--EXPECT-- +test: + subl $4, %esp + movl 8(%esp), %eax + movl 0xc(%esp), %ecx + movl %ecx, (%esp) + andl (%esp), %eax + leal (%eax, %eax), %eax + movl %eax, (%esp) + addl $4, %esp + retl diff --git a/tests/debug.x86/switch_001.irt b/tests/debug.x86/switch_001.irt new file mode 100644 index 0000000..14f5ad1 --- /dev/null +++ b/tests/debug.x86/switch_001.irt @@ -0,0 +1,62 @@ +--TEST-- +SWITCH 001 +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + uintptr_t c_1 = 0; + bool c_2 = 0; + bool c_3 = 1; + int32_t c_4 = 1; + int32_t c_5 = 2; + int32_t c_6 = 3; + int32_t c_7 = 4; + l_1 = START(l_16); + int32_t d_2 = PARAM(l_1, "z", 0); + l_4 = SWITCH(l_1, d_2); + l_5 = CASE_VAL(l_4, c_4); + int32_t x_1 = COPY(c_4); + l_6 = END(l_5); + l_7 = CASE_VAL(l_4, c_5); + int32_t x_2 = COPY(c_5); + l_8 = END(l_7); + l_9 = CASE_VAL(l_4, c_6); + int32_t x_3 = COPY(c_6); + l_10 = END(l_9); + l_11 = CASE_DEFAULT(l_4); + int32_t x_4 = COPY(c_7); + l_12 = END(l_11); + l_13 = MERGE/4(l_6, l_8, l_10, l_12); + int32_t ret = PHI/4(l_13, x_1, x_2, x_3, x_4); + l_16 = RETURN(l_13, ret); +} +--EXPECT-- +test: + movl 4(%esp), %eax + cmpl $3, %eax + jg .L5 + cmpl $1, %eax + jl .L5 + leal -4(, %eax, 4), %eax + jmpl *.L6(%eax) +.L1: + movl $1, %eax +.L2: + retl +.L3: + movl $2, %eax + jmp .L2 +.L4: + movl $3, %eax + jmp .L2 +.L5: + movl $4, %eax + jmp .L2 +.rodata +.align 4 +.L6: + .dword .L1 + .dword .L3 + .dword .L4 diff --git a/tests/debug.x86/switch_002.irt b/tests/debug.x86/switch_002.irt new file mode 100644 index 0000000..48afc00 --- /dev/null +++ b/tests/debug.x86/switch_002.irt @@ -0,0 +1,38 @@ +--TEST-- +SWITCH 002 +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + uintptr_t c_1 = 0; + bool c_2 = 0; + bool c_3 = 1; + int32_t c_4 = 1; + int32_t c_5 = 2; + int32_t c_6 = 3; + int32_t c_7 = 4; + l_1 = START(l_16); + int32_t d_2 = COPY(c_7); + l_4 = SWITCH(l_1, d_2); + l_5 = CASE_VAL(l_4, c_4); + int32_t x_1 = COPY(c_4); + l_6 = END(l_5); + l_7 = CASE_VAL(l_4, c_5); + int32_t x_2 = COPY(c_5); + l_8 = END(l_7); + l_9 = CASE_VAL(l_4, c_6); + int32_t x_3 = COPY(c_6); + l_10 = END(l_9); + l_11 = CASE_DEFAULT(l_4); + int32_t x_4 = COPY(c_7); + l_12 = END(l_11); + l_13 = MERGE/4(l_6, l_8, l_10, l_12); + int32_t ret = PHI/4(l_13, x_1, x_2, x_3, x_4); + l_16 = RETURN(l_13, ret); +} +--EXPECT-- +test: + movl $4, %eax + retl diff --git a/tests/debug.x86/tailcall_001.irt b/tests/debug.x86/tailcall_001.irt new file mode 100644 index 0000000..bedc0b0 --- /dev/null +++ b/tests/debug.x86/tailcall_001.irt @@ -0,0 +1,31 @@ +--TEST-- +Simple CALL +--TARGET-- +x86 +--ARGS-- +-S --run +--CODE-- +{ + uintptr_t c_1 = 0; + bool c_2 = 0; + bool c_3 = 1; + int32_t c_4 = 42; + uintptr_t c_5 = func(printf); + uintptr_t c_6 = "hello %d!\n"; + l_1 = START(l_4); + char d_2, l_2 = TAILCALL/2(l_1, c_5, c_6, c_4); + l_4 = UNREACHABLE(l_2, d_2); +} +--EXPECT-- +test: + leaq .L1(%rip), %rdi + movl $0x2a, %esi + movabsq $_IO_printf, %rax + jmpq *%rax +.rodata +.L1: + .db 0x68, 0x65, 0x6c, 0x6c, 0x6f, 0x20, 0x25, 0x64, 0x21, 0x0a, 0x00 + +hello 42! + +exit code = 10 diff --git a/tests/debug.x86/tailcall_002.irt b/tests/debug.x86/tailcall_002.irt new file mode 100644 index 0000000..2b4df85 --- /dev/null +++ b/tests/debug.x86/tailcall_002.irt @@ -0,0 +1,24 @@ +--TEST-- +Indirect Tail CALL +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + uintptr_t c_6 = "hello %d!\n"; + l_1 = START(l_4); + uintptr_t f = PARAM(l_1, "f", 1); + int32_t p = PARAM(l_1, "p", 2); + int32_t d_2, l_2 = TAILCALL/2(l_1, f, c_6, p); + l_4 = UNREACHABLE(l_2, d_2); +} +--EXPECT-- +test: + movq %rdi, %rax + leaq .L1(%rip), %rdi + jmpq *%rax +.rodata + .db 0x90, 0x90, 0x90, 0x90 +.L1: + .db 0x68, 0x65, 0x6c, 0x6c, 0x6f, 0x20, 0x25, 0x64, 0x21, 0x0a, 0x00 diff --git a/tests/debug.x86/test-O0.irt b/tests/debug.x86/test-O0.irt new file mode 100644 index 0000000..a899ee8 --- /dev/null +++ b/tests/debug.x86/test-O0.irt @@ -0,0 +1,120 @@ +--TEST-- +Mandelbrot Test (-O0) +--TARGET-- +x86 +--ARGS-- +-S -O0 +--CODE-- +{ + uintptr_t c_1 = 0; + bool c_2 = 0; + bool c_3 = 1; + double c_4 = 0.5; + double c_5 = 0; + int32_t c_6 = 0; + int32_t c_7 = 1; + double c_8 = 16; + int32_t c_9 = 1000; + l_1 = START(l_35); + double d_2 = PARAM(l_1, "x", 0); + double d_3 = PARAM(l_1, "y", 1); + double d_4 = VAR(l_1, "cr"); + double d_5 = SUB(d_3, c_4); + double d_6 = VAR(l_1, "ci"); + double d_7 = VAR(l_1, "zi"); + double d_8 = VAR(l_1, "zr"); + int32_t d_9 = VAR(l_1, "i"); + l_10 = END(l_1); + l_11 = LOOP_BEGIN(l_10, l_37); + double d_12 = PHI(l_11, c_5, d_25); + double d_13 = PHI(l_11, c_5, d_23); + int32_t d_14 = PHI(l_11, c_6, d_15); + int32_t d_15 = ADD(d_14, c_7); + double d_16 = VAR(l_11, "temp"); + double d_17 = MUL(d_13, d_12); + double d_18 = VAR(l_11, "zr2"); + double d_19 = MUL(d_13, d_13); + double d_20 = VAR(l_11, "zi2"); + double d_21 = MUL(d_12, d_12); + double d_22 = SUB(d_19, d_21); + double d_23 = ADD(d_22, d_5); + double d_24 = ADD(d_17, d_17); + double d_25 = ADD(d_24, d_2); + double d_26 = ADD(d_21, d_19); + bool d_27 = GT(d_26, c_8); + l_28 = IF(l_11, d_27); + l_29 = IF_TRUE(l_28); + l_30 = RETURN(l_29, d_15); + l_31 = IF_FALSE(l_28); + bool d_32 = GT(d_15, c_9); + l_33 = IF(l_31, d_32); + l_34 = IF_TRUE(l_33); + l_35 = RETURN(l_34, c_6, l_30); + l_36 = IF_FALSE(l_33); + l_37 = LOOP_END(l_36, l_11); +} +--EXPECT-- +test: + subl $0x60, %esp + movsd 0x6c(%esp), %xmm0 + subsd .L4, %xmm0 + movsd %xmm0, (%esp) + xorpd %xmm0, %xmm0 + movsd %xmm0, 8(%esp) + xorpd %xmm0, %xmm0 + movsd %xmm0, 0x10(%esp) + movl $0, 0x18(%esp) +.L1: + movl 0x18(%esp), %eax + addl $1, %eax + movl %eax, 0x1c(%esp) + movsd 0x10(%esp), %xmm0 + mulsd 8(%esp), %xmm0 + movsd %xmm0, 0x20(%esp) + movsd 0x10(%esp), %xmm0 + mulsd %xmm0, %xmm0 + movsd %xmm0, 0x28(%esp) + movsd 8(%esp), %xmm0 + mulsd %xmm0, %xmm0 + movsd %xmm0, 0x30(%esp) + movsd 0x28(%esp), %xmm0 + subsd 0x30(%esp), %xmm0 + movsd %xmm0, 0x38(%esp) + movsd 0x38(%esp), %xmm0 + addsd (%esp), %xmm0 + movsd %xmm0, 0x40(%esp) + movsd 0x20(%esp), %xmm0 + addsd %xmm0, %xmm0 + movsd %xmm0, 0x48(%esp) + movsd 0x48(%esp), %xmm0 + addsd 0x64(%esp), %xmm0 + movsd %xmm0, 0x50(%esp) + movsd 0x30(%esp), %xmm0 + addsd 0x28(%esp), %xmm0 + movsd %xmm0, 0x58(%esp) + movsd 0x58(%esp), %xmm0 + ucomisd .L5, %xmm0 + jbe .L2 + movl 0x1c(%esp), %eax + addl $0x60, %esp + retl +.L2: + cmpl $0x3e8, 0x1c(%esp) + jle .L3 + xorl %eax, %eax + addl $0x60, %esp + retl +.L3: + movsd 0x50(%esp), %xmm0 + movsd %xmm0, 8(%esp) + movsd 0x40(%esp), %xmm0 + movsd %xmm0, 0x10(%esp) + movl 0x1c(%esp), %eax + movl %eax, 0x18(%esp) + jmp .L1 +.rodata + .db 0x90, 0x90, 0x90, 0x90, 0x90 +.L4: + .db 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x3f +.L5: + .db 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x40 diff --git a/tests/debug.x86/test-mavx.irt b/tests/debug.x86/test-mavx.irt new file mode 100644 index 0000000..a310036 --- /dev/null +++ b/tests/debug.x86/test-mavx.irt @@ -0,0 +1,89 @@ +--TEST-- +Mandelbrot Test (-mavx) +--TARGET-- +x86 +--ARGS-- +-S -mavx +--CODE-- +{ + uintptr_t c_1 = 0; + bool c_2 = 0; + bool c_3 = 1; + double c_4 = 0.5; + double c_5 = 0; + int32_t c_6 = 0; + int32_t c_7 = 1; + double c_8 = 16; + int32_t c_9 = 1000; + l_1 = START(l_35); + double d_2 = PARAM(l_1, "x", 0); + double d_3 = PARAM(l_1, "y", 1); + double d_4 = VAR(l_1, "cr"); + double d_5 = SUB(d_3, c_4); + double d_6 = VAR(l_1, "ci"); + double d_7 = VAR(l_1, "zi"); + double d_8 = VAR(l_1, "zr"); + int32_t d_9 = VAR(l_1, "i"); + l_10 = END(l_1); + l_11 = LOOP_BEGIN(l_10, l_37); + double d_12 = PHI(l_11, c_5, d_25); + double d_13 = PHI(l_11, c_5, d_23); + int32_t d_14 = PHI(l_11, c_6, d_15); + int32_t d_15 = ADD(d_14, c_7); + double d_16 = VAR(l_11, "temp"); + double d_17 = MUL(d_13, d_12); + double d_18 = VAR(l_11, "zr2"); + double d_19 = MUL(d_13, d_13); + double d_20 = VAR(l_11, "zi2"); + double d_21 = MUL(d_12, d_12); + double d_22 = SUB(d_19, d_21); + double d_23 = ADD(d_22, d_5); + double d_24 = ADD(d_17, d_17); + double d_25 = ADD(d_24, d_2); + double d_26 = ADD(d_21, d_19); + bool d_27 = GT(d_26, c_8); + l_28 = IF(l_11, d_27); + l_29 = IF_TRUE(l_28); + l_30 = RETURN(l_29, d_15); + l_31 = IF_FALSE(l_28); + bool d_32 = GT(d_15, c_9); + l_33 = IF(l_31, d_32); + l_34 = IF_TRUE(l_33); + l_35 = RETURN(l_34, c_6, l_30); + l_36 = IF_FALSE(l_33); + l_37 = LOOP_END(l_36, l_11); +} +--EXPECT-- +test: + vmovsd 4(%esp), %xmm0 + vmovsd 0xc(%esp), %xmm1 + vsubsd .L4, %xmm1, %xmm1 + vxorpd %xmm3, %xmm3, %xmm3 + vxorpd %xmm2, %xmm2, %xmm2 + xorl %eax, %eax +.L1: + leal 1(%eax), %eax + vmulsd %xmm2, %xmm2, %xmm4 + vmulsd %xmm3, %xmm3, %xmm5 + vaddsd %xmm4, %xmm5, %xmm6 + vucomisd .L5, %xmm6 + ja .L2 + cmpl $0x3e8, %eax + jg .L3 + vmulsd %xmm3, %xmm2, %xmm3 + vsubsd %xmm5, %xmm4, %xmm2 + vaddsd %xmm1, %xmm2, %xmm2 + vaddsd %xmm3, %xmm3, %xmm3 + vaddsd %xmm0, %xmm3, %xmm3 + jmp .L1 +.L2: + retl +.L3: + xorl %eax, %eax + retl +.rodata + .db 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90 +.L4: + .db 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x3f +.L5: + .db 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x40 diff --git a/tests/debug.x86/test.irt b/tests/debug.x86/test.irt new file mode 100644 index 0000000..cf5240c --- /dev/null +++ b/tests/debug.x86/test.irt @@ -0,0 +1,93 @@ +--TEST-- +Mandelbrot Test +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + uintptr_t c_1 = 0; + bool c_2 = 0; + bool c_3 = 1; + double c_4 = 0.5; + double c_5 = 0; + int32_t c_6 = 0; + int32_t c_7 = 1; + double c_8 = 16; + int32_t c_9 = 1000; + l_1 = START(l_35); + double d_2 = PARAM(l_1, "x", 0); + double d_3 = PARAM(l_1, "y", 1); + double d_4 = VAR(l_1, "cr"); + double d_5 = SUB(d_3, c_4); + double d_6 = VAR(l_1, "ci"); + double d_7 = VAR(l_1, "zi"); + double d_8 = VAR(l_1, "zr"); + int32_t d_9 = VAR(l_1, "i"); + l_10 = END(l_1); + l_11 = LOOP_BEGIN(l_10, l_37); + double d_12 = PHI(l_11, c_5, d_25); + double d_13 = PHI(l_11, c_5, d_23); + int32_t d_14 = PHI(l_11, c_6, d_15); + int32_t d_15 = ADD(d_14, c_7); + double d_16 = VAR(l_11, "temp"); + double d_17 = MUL(d_13, d_12); + double d_18 = VAR(l_11, "zr2"); + double d_19 = MUL(d_13, d_13); + double d_20 = VAR(l_11, "zi2"); + double d_21 = MUL(d_12, d_12); + double d_22 = SUB(d_19, d_21); + double d_23 = ADD(d_22, d_5); + double d_24 = ADD(d_17, d_17); + double d_25 = ADD(d_24, d_2); + double d_26 = ADD(d_21, d_19); + bool d_27 = GT(d_26, c_8); + l_28 = IF(l_11, d_27); + l_29 = IF_TRUE(l_28); + l_30 = RETURN(l_29, d_15); + l_31 = IF_FALSE(l_28); + bool d_32 = GT(d_15, c_9); + l_33 = IF(l_31, d_32); + l_34 = IF_TRUE(l_33); + l_35 = RETURN(l_34, c_6, l_30); + l_36 = IF_FALSE(l_33); + l_37 = LOOP_END(l_36, l_11); +} +--EXPECT-- +test: + movsd 4(%esp), %xmm0 + movsd 0xc(%esp), %xmm1 + subsd .L4, %xmm1 + xorpd %xmm3, %xmm3 + xorpd %xmm2, %xmm2 + xorl %eax, %eax +.L1: + leal 1(%eax), %eax + movapd %xmm2, %xmm4 + mulsd %xmm2, %xmm4 + movapd %xmm3, %xmm5 + mulsd %xmm3, %xmm5 + movapd %xmm5, %xmm6 + addsd %xmm4, %xmm6 + ucomisd .L5, %xmm6 + ja .L2 + cmpl $0x3e8, %eax + jg .L3 + mulsd %xmm2, %xmm3 + subsd %xmm5, %xmm4 + movapd %xmm4, %xmm2 + addsd %xmm1, %xmm2 + addsd %xmm3, %xmm3 + addsd %xmm0, %xmm3 + jmp .L1 +.L2: + retl +.L3: + xorl %eax, %eax + retl +.rodata + .db 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90 +.L4: + .db 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x3f +.L5: + .db 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x40 diff --git a/tests/debug.x86/test_mem.irt b/tests/debug.x86/test_mem.irt new file mode 100644 index 0000000..ee3d237 --- /dev/null +++ b/tests/debug.x86/test_mem.irt @@ -0,0 +1,137 @@ +--TEST-- +Mandelbrot Test (mem) +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + uintptr_t c_1 = 0; + bool c_2 = 0; + bool c_3 = 1; + double c_4 = 0.5; + double c_5 = 0; + int32_t c_6 = 0; + int32_t c_7 = 1; + uint32_t c_size = 4; + double c_8 = 16; + int32_t c_9 = 1000; + l_1 = START(l_35); + double d_2 = PARAM(l_1, "x", 0); + double d_3 = PARAM(l_1, "y", 1); + double cr = VAR(l_1, "cr"); + double d_5 = SUB(d_3, c_4); + l_1_1 = VSTORE(l_1, cr, d_5); + double ci = VAR(l_1, "ci"); + l_1_2 = VSTORE(l_1_1, ci, d_2); + double zi = VAR(l_1, "zi"); + l_1_3 = VSTORE(l_1_2, zi, c_5); + double zr = VAR(l_1, "zr"); + l_1_4 = VSTORE(l_1_3, zr, c_5); + uintptr_t i, l_1_5 = ALLOCA(l_1_4, c_size); + l_1_6 = STORE(l_1_5, i, c_6); + l_10 = END(l_1_6); + l_11 = LOOP_BEGIN(l_10, l_37); + + int32_t d_14, l_11_1 = LOAD(l_11, i); + int32_t d_15 = ADD(d_14, c_7); + l_11_2 = STORE(l_11_1, i, d_15); + + double temp = VAR(l_11, "temp"); + double zr_1, l_11_3 = VLOAD(l_11_2, zr); + double zi_1, l_11_4 = VLOAD(l_11_3, zi); + double d_17 = MUL(zr_1, zi_1); + l_11_5 = VSTORE(l_11_4, temp, d_17); + + double zr2 = VAR(l_11, "zr2"); + double d_19 = MUL(zr_1, zr_1); + l_11_6 = VSTORE(l_11_5, zr2, d_19); + + double zi2 = VAR(l_11, "zi2"); + double d_21 = MUL(zi_1, zi_1); + l_11_7 = VSTORE(l_11_6, zi2, d_21); + double zr2_1, l_11_8 = VLOAD(l_11_7, zr2); + double zi2_1, l_11_9 = VLOAD(l_11_8, zi2); + double d_22 = SUB(zr2_1, zi2_1); + double cr2_1, l_11_10 = VLOAD(l_11_9, cr); + double d_23 = ADD(d_22, cr2_1); + l_11_11 = VSTORE(l_11_10, zr, d_23); + double temp_1, l_11_12 = VLOAD(l_11_11, temp); + double d_24 = ADD(temp_1, temp_1); + double ci_1, l_11_13 = VLOAD(l_11_12, ci); + double d_25 = ADD(d_24, ci_1); + l_11_14 = VSTORE(l_11_13, zi, d_25); + double zi2_2, l_11_15 = VLOAD(l_11_14, zi2); + double zr2_2, l_11_16 = VLOAD(l_11_15, zr2); + double d_26 = ADD(zi2_2, zr2_2); + bool d_27 = GT(d_26, c_8); + l_28 = IF(l_11_16, d_27); + l_29 = IF_TRUE(l_28); + int32_t d_15_1, l_29_1 = LOAD(l_29, i); + l_30 = RETURN(l_29_1, d_15_1); + l_31 = IF_FALSE(l_28); + int32_t d_15_2, l_31_1 = LOAD(l_31, i); + bool d_32 = GT(d_15_2, c_9); + l_33 = IF(l_31_1, d_32); + l_34 = IF_TRUE(l_33); + l_35 = RETURN(l_34, c_6, l_30); + l_36 = IF_FALSE(l_33); + l_37 = LOOP_END(l_36, l_11); +} +--EXPECT-- +test: + pushl %ebp + movl %esp, %ebp + subl $0x38, %esp + movsd 8(%ebp), %xmm0 + movsd 0x10(%ebp), %xmm1 + subsd .L3, %xmm1 + movsd %xmm1, -0x38(%ebp) + movsd %xmm0, -0x30(%ebp) + xorpd %xmm0, %xmm0 + movsd %xmm0, -0x28(%ebp) + xorpd %xmm0, %xmm0 + movsd %xmm0, -0x20(%ebp) + subl $8, %esp + movl %esp, %eax + movl $0, (%eax) +.L1: + addl $1, (%eax) + movsd -0x20(%ebp), %xmm0 + movsd -0x28(%ebp), %xmm1 + movapd %xmm1, %xmm2 + mulsd %xmm0, %xmm2 + movsd %xmm2, -0x18(%ebp) + mulsd %xmm0, %xmm0 + movsd %xmm0, -0x10(%ebp) + mulsd %xmm1, %xmm1 + movsd %xmm1, -8(%ebp) + movsd -0x10(%ebp), %xmm0 + subsd -8(%ebp), %xmm0 + addsd -0x38(%ebp), %xmm0 + movsd %xmm0, -0x20(%ebp) + movsd -0x18(%ebp), %xmm0 + addsd %xmm0, %xmm0 + addsd -0x30(%ebp), %xmm0 + movsd %xmm0, -0x28(%ebp) + movsd -0x10(%ebp), %xmm0 + addsd -8(%ebp), %xmm0 + ucomisd .L4, %xmm0 + ja .L2 + cmpl $0x3e8, (%eax) + jle .L1 + xorl %eax, %eax + movl %ebp, %esp + popl %ebp + retl +.L2: + movl (%eax), %eax + movl %ebp, %esp + popl %ebp + retl +.rodata + .db 0x90, 0x90, 0x90, 0x90, 0x90, 0x90 +.L3: + .db 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x3f +.L4: + .db 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x40 diff --git a/tests/debug.x86/test_var-O0.irt b/tests/debug.x86/test_var-O0.irt new file mode 100644 index 0000000..2ff3ff9 --- /dev/null +++ b/tests/debug.x86/test_var-O0.irt @@ -0,0 +1,134 @@ +--TEST-- +Mandelbrot Test (var) +--TARGET-- +x86 +--ARGS-- +-S -O0 +--CODE-- +{ + uintptr_t c_1 = 0; + bool c_2 = 0; + bool c_3 = 1; + double c_4 = 0.5; + double c_5 = 0; + int32_t c_6 = 0; + int32_t c_7 = 1; + double c_8 = 16; + int32_t c_9 = 1000; + l_1 = START(l_35); + double d_2 = PARAM(l_1, "x", 0); + double d_3 = PARAM(l_1, "y", 1); + double cr = VAR(l_1, "cr"); + double d_5 = SUB(d_3, c_4); + l_1_1 = VSTORE(l_1, cr, d_5); + double ci = VAR(l_1, "ci"); + l_1_2 = VSTORE(l_1_1, ci, d_2); + double zi = VAR(l_1, "zi"); + l_1_3 = VSTORE(l_1_2, zi, c_5); + double zr = VAR(l_1, "zr"); + l_1_4 = VSTORE(l_1_3, zr, c_5); + int32_t i = VAR(l_1, "i"); + l_1_5 = VSTORE(l_1_4, i, c_6); + l_10 = END(l_1_5); + l_11 = LOOP_BEGIN(l_10, l_37); + int32_t d_14, l_11_1 = VLOAD(l_11, i); + int32_t d_15 = ADD(d_14, c_7); + l_11_2 = VSTORE(l_11_1, i, d_15); + double temp = VAR(l_11, "temp"); + double zr_1, l_11_3 = VLOAD(l_11_2, zr); + double zi_1, l_11_4 = VLOAD(l_11_3, zi); + double d_17 = MUL(zr_1, zi_1); + l_11_5 = VSTORE(l_11_4, temp, d_17); + double zr2 = VAR(l_11, "zr2"); + double d_19 = MUL(zr_1, zr_1); + l_11_6 = VSTORE(l_11_5, zr2, d_19); + double zi2 = VAR(l_11, "zi2"); + double d_21 = MUL(zi_1, zi_1); + l_11_7 = VSTORE(l_11_6, zi2, d_21); + double zr2_1, l_11_8 = VLOAD(l_11_7, zr2); + double zi2_1, l_11_9 = VLOAD(l_11_8, zi2); + double d_22 = SUB(zr2_1, zi2_1); + double cr2_1, l_11_10 = VLOAD(l_11_9, cr); + double d_23 = ADD(d_22, cr2_1); + l_11_11 = VSTORE(l_11_10, zr, d_23); + double temp_1, l_11_12 = VLOAD(l_11_11, temp); + double d_24 = ADD(temp_1, temp_1); + double ci_1, l_11_13 = VLOAD(l_11_12, ci); + double d_25 = ADD(d_24, ci_1); + l_11_14 = VSTORE(l_11_13, zi, d_25); + double zi2_2, l_11_15 = VLOAD(l_11_14, zi2); + double zr2_2, l_11_16 = VLOAD(l_11_15, zr2); + double d_26 = ADD(zi2_2, zr2_2); + bool d_27 = GT(d_26, c_8); + l_28 = IF(l_11_16, d_27); + l_29 = IF_TRUE(l_28); + int32_t d_15_1, l_29_1 = VLOAD(l_29, i); + l_30 = RETURN(l_29_1, d_15_1); + l_31 = IF_FALSE(l_28); + int32_t d_15_2, l_31_1 = VLOAD(l_31, i); + bool d_32 = GT(d_15_2, c_9); + l_33 = IF(l_31_1, d_32); + l_34 = IF_TRUE(l_33); + l_35 = RETURN(l_34, c_6, l_30); + l_36 = IF_FALSE(l_33); + l_37 = LOOP_END(l_36, l_11); +} +--EXPECT-- +test: + subl $0x54, %esp + movsd 0x60(%esp), %xmm0 + subsd .L3, %xmm0 + movsd %xmm0, (%esp) + movsd 0x58(%esp), %xmm0 + movsd %xmm0, 8(%esp) + xorpd %xmm0, %xmm0 + movsd %xmm0, 0x10(%esp) + xorpd %xmm0, %xmm0 + movsd %xmm0, 0x18(%esp) + movl $0, 0x20(%esp) +.L1: + movl 0x20(%esp), %eax + addl $1, %eax + movl %eax, 0x20(%esp) + movsd 0x18(%esp), %xmm0 + mulsd 0x10(%esp), %xmm0 + movsd %xmm0, 0x24(%esp) + movsd 0x18(%esp), %xmm0 + mulsd %xmm0, %xmm0 + movsd %xmm0, 0x2c(%esp) + movsd 0x10(%esp), %xmm0 + mulsd %xmm0, %xmm0 + movsd %xmm0, 0x34(%esp) + movsd 0x2c(%esp), %xmm0 + subsd 0x34(%esp), %xmm0 + movsd %xmm0, 0x3c(%esp) + movsd 0x3c(%esp), %xmm0 + addsd (%esp), %xmm0 + movsd %xmm0, 0x18(%esp) + movsd 0x24(%esp), %xmm0 + addsd %xmm0, %xmm0 + movsd %xmm0, 0x44(%esp) + movsd 0x44(%esp), %xmm0 + addsd 8(%esp), %xmm0 + movsd %xmm0, 0x10(%esp) + movsd 0x34(%esp), %xmm0 + addsd 0x2c(%esp), %xmm0 + movsd %xmm0, 0x4c(%esp) + movsd 0x4c(%esp), %xmm0 + ucomisd .L4, %xmm0 + jbe .L2 + movl 0x20(%esp), %eax + addl $0x54, %esp + retl +.L2: + cmpl $0x3e8, 0x20(%esp) + jle .L1 + xorl %eax, %eax + addl $0x54, %esp + retl +.rodata + .db 0x90, 0x90 +.L3: + .db 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x3f +.L4: + .db 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x40 diff --git a/tests/debug.x86/test_var.irt b/tests/debug.x86/test_var.irt new file mode 100644 index 0000000..1dd1aa5 --- /dev/null +++ b/tests/debug.x86/test_var.irt @@ -0,0 +1,126 @@ +--TEST-- +Mandelbrot Test (var) +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + uintptr_t c_1 = 0; + bool c_2 = 0; + bool c_3 = 1; + double c_4 = 0.5; + double c_5 = 0; + int32_t c_6 = 0; + int32_t c_7 = 1; + double c_8 = 16; + int32_t c_9 = 1000; + l_1 = START(l_35); + double d_2 = PARAM(l_1, "x", 0); + double d_3 = PARAM(l_1, "y", 1); + double cr = VAR(l_1, "cr"); + double d_5 = SUB(d_3, c_4); + l_1_1 = VSTORE(l_1, cr, d_5); + double ci = VAR(l_1, "ci"); + l_1_2 = VSTORE(l_1_1, ci, d_2); + double zi = VAR(l_1, "zi"); + l_1_3 = VSTORE(l_1_2, zi, c_5); + double zr = VAR(l_1, "zr"); + l_1_4 = VSTORE(l_1_3, zr, c_5); + int32_t i = VAR(l_1, "i"); + l_1_5 = VSTORE(l_1_4, i, c_6); + l_10 = END(l_1_5); + l_11 = LOOP_BEGIN(l_10, l_37); + int32_t d_14, l_11_1 = VLOAD(l_11, i); + int32_t d_15 = ADD(d_14, c_7); + l_11_2 = VSTORE(l_11_1, i, d_15); + double temp = VAR(l_11, "temp"); + double zr_1, l_11_3 = VLOAD(l_11_2, zr); + double zi_1, l_11_4 = VLOAD(l_11_3, zi); + double d_17 = MUL(zr_1, zi_1); + l_11_5 = VSTORE(l_11_4, temp, d_17); + double zr2 = VAR(l_11, "zr2"); + double d_19 = MUL(zr_1, zr_1); + l_11_6 = VSTORE(l_11_5, zr2, d_19); + double zi2 = VAR(l_11, "zi2"); + double d_21 = MUL(zi_1, zi_1); + l_11_7 = VSTORE(l_11_6, zi2, d_21); + double zr2_1, l_11_8 = VLOAD(l_11_7, zr2); + double zi2_1, l_11_9 = VLOAD(l_11_8, zi2); + double d_22 = SUB(zr2_1, zi2_1); + double cr2_1, l_11_10 = VLOAD(l_11_9, cr); + double d_23 = ADD(d_22, cr2_1); + l_11_11 = VSTORE(l_11_10, zr, d_23); + double temp_1, l_11_12 = VLOAD(l_11_11, temp); + double d_24 = ADD(temp_1, temp_1); + double ci_1, l_11_13 = VLOAD(l_11_12, ci); + double d_25 = ADD(d_24, ci_1); + l_11_14 = VSTORE(l_11_13, zi, d_25); + double zi2_2, l_11_15 = VLOAD(l_11_14, zi2); + double zr2_2, l_11_16 = VLOAD(l_11_15, zr2); + double d_26 = ADD(zi2_2, zr2_2); + bool d_27 = GT(d_26, c_8); + l_28 = IF(l_11_16, d_27); + l_29 = IF_TRUE(l_28); + int32_t d_15_1, l_29_1 = VLOAD(l_29, i); + l_30 = RETURN(l_29_1, d_15_1); + l_31 = IF_FALSE(l_28); + int32_t d_15_2, l_31_1 = VLOAD(l_31, i); + bool d_32 = GT(d_15_2, c_9); + l_33 = IF(l_31_1, d_32); + l_34 = IF_TRUE(l_33); + l_35 = RETURN(l_34, c_6, l_30); + l_36 = IF_FALSE(l_33); + l_37 = LOOP_END(l_36, l_11); +} +--EXPECT-- +test: + subl $0x3c, %esp + movsd 0x40(%esp), %xmm0 + movsd 0x48(%esp), %xmm1 + subsd .L3, %xmm1 + movsd %xmm1, (%esp) + movsd %xmm0, 8(%esp) + xorpd %xmm0, %xmm0 + movsd %xmm0, 0x10(%esp) + xorpd %xmm0, %xmm0 + movsd %xmm0, 0x18(%esp) + movl $0, 0x20(%esp) +.L1: + addl $1, 0x20(%esp) + movsd 0x18(%esp), %xmm0 + movsd 0x10(%esp), %xmm1 + movapd %xmm1, %xmm2 + mulsd %xmm0, %xmm2 + movsd %xmm2, 0x24(%esp) + mulsd %xmm0, %xmm0 + movsd %xmm0, 0x2c(%esp) + mulsd %xmm1, %xmm1 + movsd %xmm1, 0x34(%esp) + movsd 0x2c(%esp), %xmm0 + subsd 0x34(%esp), %xmm0 + addsd (%esp), %xmm0 + movsd %xmm0, 0x18(%esp) + movsd 0x24(%esp), %xmm0 + addsd %xmm0, %xmm0 + addsd 8(%esp), %xmm0 + movsd %xmm0, 0x10(%esp) + movsd 0x2c(%esp), %xmm0 + addsd 0x34(%esp), %xmm0 + ucomisd .L4, %xmm0 + ja .L2 + cmpl $0x3e8, 0x20(%esp) + jle .L1 + xorl %eax, %eax + addl $0x3c, %esp + retl +.L2: + movl 0x20(%esp), %eax + addl $0x3c, %esp + retl +.rodata + .db 0x90, 0x90, 0x90, 0x90 +.L3: + .db 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x3f +.L4: + .db 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x40 diff --git a/tests/debug/regset-fib.irt b/tests/debug/regset-fib.irt new file mode 100644 index 0000000..b0eb962 --- /dev/null +++ b/tests/debug/regset-fib.irt @@ -0,0 +1,138 @@ +--TEST-- +Fib +--TARGET-- +x86_64 +--ARGS-- +--debug-regset 0x3ffff --save --dump-live-ranges -S --run +--CODE-- +{ + int32_t zero = 0; + double c_0 = 0; + double c_1 = 1; + double c_10000 = 10000; + uintptr_t f = func(printf); + uintptr_t format = "%g\n"; + l_1 = START(l_6); + double lo_1 = COPY(c_0); + double hi_1 = COPY(c_1); + l_2 = END(l_1); + l_3 = LOOP_BEGIN(l_2, l_9); + double lo_2 = PHI(l_3, lo_1, lo_3); + double hi_2 = PHI(l_3, hi_1, hi_3); + bool b = LT(hi_2, c_10000); + l_4 = IF(l_3, b); + l_7 = IF_TRUE(l_4); + double hi_3 = ADD(hi_2, lo_2); + double lo_3 = SUB(hi_3, lo_2); + l_8 = CALL/2(l_7, f, format, lo_3); +# ll = CALL/2(l_7, f, format, lo_3); +# l_8 = CALL/2(ll, f, format, lo_3); + l_9 = LOOP_END(l_8, l_3); + l_5 = IF_FALSE(l_4); + l_6 = RETURN(l_5, zero); +} +--EXPECT-- +{ + uintptr_t c_1 = 0; + bool c_2 = 0; + bool c_3 = 1; + int32_t c_4 = 0; + double c_5 = 0; + double c_6 = 1; + double c_7 = 10000; + uintptr_t c_8 = func(printf); + uintptr_t c_9 = "%g\n"; + l_1 = START(l_15); + l_2 = END(l_1); + l_3 = LOOP_BEGIN(l_2, l_13); + double d_4 = PHI(l_3, c_5, d_10); + double d_5 = PHI(l_3, c_6, d_9); + bool d_6 = GT(c_7, d_5); + l_7 = IF(l_3, d_6); + l_8 = IF_TRUE(l_7); + double d_9 = ADD(d_5, d_4); + double d_10 = SUB(d_9, d_4); + l_11 = CALL/2(l_8, c_8, c_9, d_10); + l_13 = LOOP_END(l_11, l_3); + l_14 = IF_FALSE(l_7); + l_15 = RETURN(l_14, c_4); +} +{ # LIVE-RANGES (vregs_count=3) +TMP + [%xmm0]: [2.2-2.3) + [%xmm1]: [6.0-6.2) + [%rax]: [11.0-11.1) + [%xmm0]: [13.2-13.3) +R1 (d_4) [SPILL=0x0] + [%xmm1]: [3.0-6.0), DEF(4.2) + : [6.0-8.0) + [%xmm1]: [8.0-10.1), USE(9.1/2), USE(10.1/2) +R2 (d_5, d_9) [SPILL=0x8] + [%xmm0]: [3.0-10.0), DEF(5.2), USE(6.1/2), USE(9.0/1)!, DEF(9.0)!, DEF(9.2)!, USE(10.0/1, hint=%xmm0, hint=R3)! + : [10.0-14.0), PHI_USE(13.2, phi=d_5/3) +R3 (d_10) [SPILL=0x10] + [%xmm0]: [10.0-11.0), DEF(10.0, hint=R2)!, DEF(10.2)!, USE(11.0/4, hint=%xmm0) + : [11.0-14.0), PHI_USE(13.2, phi=d_4/3) +[%rax] : [15.0-15.1) +[%rdi] : [11.0-11.1) +[%xmm0] : [11.0-11.1) +[%SCRATCH] : [11.1-11.2) +} +test: + subq $0x18, %rsp + xorpd %xmm1, %xmm1 + movsd %xmm1, (%rsp) + movsd .L3(%rip), %xmm0 + movsd %xmm0, 8(%rsp) +.L1: + movsd .L4(%rip), %xmm1 + ucomisd 8(%rsp), %xmm1 + jbe .L2 + movsd 8(%rsp), %xmm0 + addsd (%rsp), %xmm0 + movsd %xmm0, 8(%rsp) + movsd 8(%rsp), %xmm0 + subsd (%rsp), %xmm0 + movsd %xmm0, 0x10(%rsp) + movsd 0x10(%rsp), %xmm0 + leaq .L5(%rip), %rdi + movabsq $_IO_printf, %rax + callq *%rax + movsd 0x10(%rsp), %xmm1 + movsd %xmm1, (%rsp) + jmp .L1 +.L2: + xorl %eax, %eax + addq $0x18, %rsp + retq +.rodata + .db 0x90, 0x90, 0x90, 0x90, 0x90, 0x90 +.L3: + .db 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x3f +.L4: + .db 0x00, 0x00, 0x00, 0x00, 0x00, 0x88, 0xc3, 0x40 +.L5: + .db 0x25, 0x67, 0x0a, 0x00 + +1 +1 +2 +3 +5 +8 +13 +21 +34 +55 +89 +144 +233 +377 +610 +987 +1597 +2584 +4181 +6765 + +exit code = 0 diff --git a/tests/debug/regset-fib2.irt b/tests/debug/regset-fib2.irt new file mode 100644 index 0000000..74af358 --- /dev/null +++ b/tests/debug/regset-fib2.irt @@ -0,0 +1,163 @@ +--TEST-- +Fib2 +--TARGET-- +x86_64 +--ARGS-- +--debug-regset 0x3ffff --save --dump-live-ranges -S --run +--CODE-- +{ + int32_t zero = 0; + double c_0 = 0; + double c_1 = 1; + double c_10000 = 10000; + uintptr_t f = func(printf); + uintptr_t format = "%g\n"; + l_1 = START(l_6); + double lo_1 = COPY(c_0); + double hi_1 = COPY(c_1); + l_2 = END(l_1); + l_3 = LOOP_BEGIN(l_2, l_9); + double lo_2 = PHI(l_3, lo_1, lo_3); + double hi_2 = PHI(l_3, hi_1, hi_3); + bool b = LT(hi_2, c_10000); + l_4 = IF(l_3, b); + l_7 = IF_TRUE(l_4); + double hi_3 = ADD(hi_2, lo_2); + double lo_3 = SUB(hi_3, lo_2); + ll = CALL/2(l_7, f, format, lo_3); + l_8 = CALL/2(ll, f, format, lo_3); + l_9 = LOOP_END(l_8, l_3); + l_5 = IF_FALSE(l_4); + l_6 = RETURN(l_5, zero); +} +--EXPECT-- +{ + uintptr_t c_1 = 0; + bool c_2 = 0; + bool c_3 = 1; + int32_t c_4 = 0; + double c_5 = 0; + double c_6 = 1; + double c_7 = 10000; + uintptr_t c_8 = func(printf); + uintptr_t c_9 = "%g\n"; + l_1 = START(l_17); + l_2 = END(l_1); + l_3 = LOOP_BEGIN(l_2, l_15); + double d_4 = PHI(l_3, c_5, d_10); + double d_5 = PHI(l_3, c_6, d_9); + bool d_6 = GT(c_7, d_5); + l_7 = IF(l_3, d_6); + l_8 = IF_TRUE(l_7); + double d_9 = ADD(d_5, d_4); + double d_10 = SUB(d_9, d_4); + l_11 = CALL/2(l_8, c_8, c_9, d_10); + l_13 = CALL/2(l_11, c_8, c_9, d_10); + l_15 = LOOP_END(l_13, l_3); + l_16 = IF_FALSE(l_7); + l_17 = RETURN(l_16, c_4); +} +{ # LIVE-RANGES (vregs_count=3) +TMP + [%xmm0]: [2.2-2.3) + [%xmm1]: [6.0-6.2) + [%rax]: [11.0-11.1) + [%rax]: [13.0-13.1) + [%xmm0]: [15.2-15.3) +R1 (d_4) [SPILL=0x0] + [%xmm1]: [3.0-6.0), DEF(4.2) + : [6.0-8.0) + [%xmm1]: [8.0-10.1), USE(9.1/2), USE(10.1/2) +R2 (d_5, d_9) [SPILL=0x8] + [%xmm0]: [3.0-10.0), DEF(5.2), USE(6.1/2), USE(9.0/1)!, DEF(9.0)!, DEF(9.2)!, USE(10.0/1, hint=%xmm0, hint=R3)! + : [10.0-16.0), PHI_USE(15.2, phi=d_5/3) +R3 (d_10) [SPILL=0x10] + [%xmm0]: [10.0-11.0), DEF(10.0, hint=R2)!, DEF(10.2)!, USE(11.0/4, hint=%xmm0) + : [11.0-16.0), USE(13.0/4, hint=%xmm0), PHI_USE(15.2, phi=d_4/3) +[%rax] : [17.0-17.1) +[%rdi] : [11.0-11.1), [13.0-13.1) +[%xmm0] : [11.0-11.1), [13.0-13.1) +[%SCRATCH] : [11.1-11.2), [13.1-13.2) +} +test: + subq $0x18, %rsp + xorpd %xmm1, %xmm1 + movsd %xmm1, (%rsp) + movsd .L3(%rip), %xmm0 + movsd %xmm0, 8(%rsp) +.L1: + movsd .L4(%rip), %xmm1 + ucomisd 8(%rsp), %xmm1 + jbe .L2 + movsd 8(%rsp), %xmm0 + addsd (%rsp), %xmm0 + movsd %xmm0, 8(%rsp) + movsd 8(%rsp), %xmm0 + subsd (%rsp), %xmm0 + movsd %xmm0, 0x10(%rsp) + movsd 0x10(%rsp), %xmm0 + leaq .L5(%rip), %rdi + movabsq $_IO_printf, %rax + callq *%rax + leaq .L5(%rip), %rdi + movsd 0x10(%rsp), %xmm0 + movabsq $_IO_printf, %rax + callq *%rax + movsd 0x10(%rsp), %xmm1 + movsd %xmm1, (%rsp) + jmp .L1 +.L2: + xorl %eax, %eax + addq $0x18, %rsp + retq +.rodata + .db 0x90, 0x90, 0x90, 0x90, 0x90 +.L3: + .db 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x3f +.L4: + .db 0x00, 0x00, 0x00, 0x00, 0x00, 0x88, 0xc3, 0x40 +.L5: + .db 0x25, 0x67, 0x0a, 0x00 + +1 +1 +1 +1 +2 +2 +3 +3 +5 +5 +8 +8 +13 +13 +21 +21 +34 +34 +55 +55 +89 +89 +144 +144 +233 +233 +377 +377 +610 +610 +987 +987 +1597 +1597 +2584 +2584 +4181 +4181 +6765 +6765 + +exit code = 0 diff --git a/tests/debug/regset-fibi.irt b/tests/debug/regset-fibi.irt new file mode 100644 index 0000000..7a98d46 --- /dev/null +++ b/tests/debug/regset-fibi.irt @@ -0,0 +1,119 @@ +--TEST-- +FibI +--TARGET-- +x86_64 +--ARGS-- +--save --dump-live-ranges -S --run +--CODE-- +{ + int32_t c_0 = 0; + int32_t c_1 = 1; + int32_t c_10000 = 10000; + uintptr_t f = func(printf); + uintptr_t format = "%d\n"; + l_1 = START(l_6); + int32_t lo_1 = COPY(c_0); + int32_t hi_1 = COPY(c_1); + l_2 = END(l_1); + l_3 = LOOP_BEGIN(l_2, l_9); + int32_t lo_2 = PHI(l_3, lo_1, lo_3); + int32_t hi_2 = PHI(l_3, hi_1, hi_3); + bool b = LT(hi_2, c_10000); + l_4 = IF(l_3, b); + l_7 = IF_TRUE(l_4); + int32_t hi_3 = ADD(hi_2, lo_2); + int32_t lo_3 = SUB(hi_3, lo_2); + l_8 = CALL/2(l_7, f, format, lo_3); + l_9 = LOOP_END(l_8, l_3); + l_5 = IF_FALSE(l_4); + l_6 = RETURN(l_5, c_0); +} +--EXPECT-- +{ + uintptr_t c_1 = 0; + bool c_2 = 0; + bool c_3 = 1; + int32_t c_4 = 0; + int32_t c_5 = 1; + int32_t c_6 = 10000; + uintptr_t c_7 = func(printf); + uintptr_t c_8 = "%d\n"; + l_1 = START(l_15); + l_2 = END(l_1); + l_3 = LOOP_BEGIN(l_2, l_13); + int32_t d_4 = PHI(l_3, c_4, d_10); + int32_t d_5 = PHI(l_3, c_5, d_9); + bool d_6 = LT(d_5, c_6); + l_7 = IF(l_3, d_6); + l_8 = IF_TRUE(l_7); + int32_t d_9 = ADD(d_5, d_4); + int32_t d_10 = SUB(d_9, d_4); + l_11 = CALL/2(l_8, c_7, c_8, d_10); + l_13 = LOOP_END(l_11, l_3); + l_14 = IF_FALSE(l_7); + l_15 = RETURN(l_14, c_4); +} +{ # LIVE-RANGES (vregs_count=3) +TMP + [%eax]: [2.2-2.3) + [%rax]: [11.0-11.1) + [%eax]: [13.2-13.3) +R1 (d_4) [%eax]: [3.0-10.1), DEF(4.2), USE(9.1/2)!, USE(10.1/2) +R2 (d_5, d_9) [%ebx]: [3.0-9.1), [9.2-14.0), DEF(5.2), USE(6.1/1), USE(9.1/1)!, DEF(9.2)!, USE(10.0/1, hint=%esi, hint=R3)!, PHI_USE(13.2, phi=d_5/3) +R3 (d_10) [%ebp]: [10.0-14.0), DEF(10.0, hint=R2)!, DEF(10.2)!, USE(11.0/4, hint=%esi), PHI_USE(13.2, phi=d_4/3) +[%rax] : [15.0-15.1) +[%rsi] : [11.0-11.1) +[%rdi] : [11.0-11.1) +[%SCRATCH] : [11.1-11.2) +} +test: + subq $0x18, %rsp + movq %rbx, 0x10(%rsp) + movq %rbp, 8(%rsp) + xorl %eax, %eax + movl $1, %ebx +.L1: + cmpl $0x2710, %ebx + jge .L2 + leal (%rbx, %rax), %ebx + movl %ebx, %ebp + subl %eax, %ebp + movl %ebp, %esi + leaq .L3(%rip), %rdi + movabsq $_IO_printf, %rax + callq *%rax + movl %ebp, %eax + jmp .L1 +.L2: + xorl %eax, %eax + movq 0x10(%rsp), %rbx + movq 8(%rsp), %rbp + addq $0x18, %rsp + retq +.rodata + .db 0x90, 0x90 +.L3: + .db 0x25, 0x64, 0x0a, 0x00 + +1 +1 +2 +3 +5 +8 +13 +21 +34 +55 +89 +144 +233 +377 +610 +987 +1597 +2584 +4181 +6765 + +exit code = 0 diff --git a/tests/debug/regset-test.irt b/tests/debug/regset-test.irt new file mode 100644 index 0000000..fb81142 --- /dev/null +++ b/tests/debug/regset-test.irt @@ -0,0 +1,184 @@ +--TEST-- +Test +--TARGET-- +x86_64 +--ARGS-- +--debug-regset 0x3ffff --save --dump-live-ranges -S +--CODE-- +{ + uintptr_t c_1 = 0; + bool c_2 = 0; + bool c_3 = 1; + double c_4 = 0.5; + double c_5 = 0; + int32_t c_6 = 0; + int32_t c_7 = 1; + double c_8 = 16; + int32_t c_9 = 1000; + l_1 = START(l_35); + double d_2 = PARAM(l_1, "x", 0); + double d_3 = PARAM(l_1, "y", 1); + double d_4 = VAR(l_1, "cr"); + double d_5 = SUB(d_3, c_4); + double d_6 = VAR(l_1, "ci"); + double d_7 = VAR(l_1, "zi"); + double d_8 = VAR(l_1, "zr"); + int32_t d_9 = VAR(l_1, "i"); + l_10 = END(l_1); + l_11 = LOOP_BEGIN(l_10, l_37); + double d_12 = PHI(l_11, c_5, d_25); + double d_13 = PHI(l_11, c_5, d_23); + int32_t d_14 = PHI(l_11, c_6, d_15); + int32_t d_15 = ADD(d_14, c_7); + double d_16 = VAR(l_11, "temp"); + double d_17 = MUL(d_13, d_12); + double d_18 = VAR(l_11, "zr2"); + double d_19 = MUL(d_13, d_13); + double d_20 = VAR(l_11, "zi2"); + double d_21 = MUL(d_12, d_12); + double d_22 = SUB(d_19, d_21); + double d_23 = ADD(d_22, d_5); + double d_24 = ADD(d_17, d_17); + double d_25 = ADD(d_24, d_2); + double d_26 = ADD(d_21, d_19); + bool d_27 = GT(d_26, c_8); + l_28 = IF(l_11, d_27); + l_29 = IF_TRUE(l_28); + l_30 = RETURN(l_29, d_15); + l_31 = IF_FALSE(l_28); + bool d_32 = GT(d_15, c_9); + l_33 = IF(l_31, d_32); + l_34 = IF_TRUE(l_33); + l_35 = RETURN(l_34, c_6, l_30); + l_36 = IF_FALSE(l_33); + l_37 = LOOP_END(l_36, l_11); +} +--EXPECT-- +{ + uintptr_t c_1 = 0; + bool c_2 = 0; + bool c_3 = 1; + double c_4 = 0.5; + double c_5 = 0; + int32_t c_6 = 0; + int32_t c_7 = 1; + double c_8 = 16; + int32_t c_9 = 1000; + l_1 = START(l_30); + double d_2 = PARAM(l_1, "x", 0); + double d_3 = PARAM(l_1, "y", 1); + double d_4 = VAR(l_1, "cr"); + double d_5 = SUB(d_3, c_4); + double d_6 = VAR(l_1, "ci"); + double d_7 = VAR(l_1, "zi"); + double d_8 = VAR(l_1, "zr"); + int32_t d_9 = VAR(l_1, "i"); + l_10 = END(l_1); + l_11 = LOOP_BEGIN(l_10, l_37); + double d_12 = PHI(l_11, c_5, d_36); + double d_13 = PHI(l_11, c_5, d_34); + int32_t d_14 = PHI(l_11, c_6, d_15); + int32_t d_15 = ADD(d_14, c_7); + double d_16 = VAR(l_11, "temp"); + double d_17 = VAR(l_11, "zr2"); + double d_18 = MUL(d_13, d_13); + double d_19 = VAR(l_11, "zi2"); + double d_20 = MUL(d_12, d_12); + double d_21 = ADD(d_20, d_18); + bool d_22 = GT(d_21, c_8); + l_23 = IF(l_11, d_22); + l_24 = IF_TRUE(l_23); + l_25 = RETURN(l_24, d_15); + l_26 = IF_FALSE(l_23); + bool d_27 = GT(d_15, c_9); + l_28 = IF(l_26, d_27); + l_29 = IF_TRUE(l_28); + l_30 = RETURN(l_29, c_6, l_25); + l_31 = IF_FALSE(l_28); + double d_32 = MUL(d_12, d_13); + double d_33 = SUB(d_18, d_20); + double d_34 = ADD(d_33, d_5); + double d_35 = ADD(d_32, d_32); + double d_36 = ADD(d_35, d_2); + l_37 = LOOP_END(l_31, l_11); +} +{ # LIVE-RANGES (vregs_count=12) +TMP + [%xmm0]: [10.2-10.3) + [%eax]: [10.2-10.3) +R1 (d_2) [SPILL=0x0] + [%xmm0]: [2.3-10.2), DEF(2.3, hint=%xmm0) + : [10.2-24.0), [26.0-29.0), [31.0-36.0) + : [36.0-38.0), USE(36.1/2) +R2 (d_3) [%xmm1]: [3.3-5.0), DEF(3.3, hint=%xmm1), USE(5.0/1, hint=R3)! +R3 (d_5) [SPILL=0x8] + [%xmm1]: [5.0-10.2), DEF(5.0, hint=R2)!, DEF(5.2)! + : [10.2-24.0), [26.0-29.0), [31.0-34.0) + : [34.0-38.0), USE(34.1/2) +R4 (d_12, d_36) [%xmm1]: [11.0-24.0), [26.0-29.0), [31.0-32.0), [36.0-38.0), DEF(12.2), USE(20.0/1, hint=R8)!, USE(20.0/2), USE(32.0/1)!, DEF(36.0, hint=R12)!, DEF(36.2)!, PHI_USE(37.2, phi=d_12/3) +R5 (d_13, d_34) [SPILL=0x10] + [%xmm0]: [11.0-18.0), DEF(13.2), USE(18.0/1, hint=R7)!, USE(18.0/2) + : [18.0-24.0), [26.0-29.0), [31.0-32.0) + [%xmm0]: [32.0-32.1), [34.0-38.0), USE(32.1/2, hint=R10), DEF(34.0, hint=R11)!, DEF(34.2)!, PHI_USE(37.2, phi=d_13/3) +R6 (d_14, d_15) [%eax]: [11.0-15.1), [15.2-25.0), [26.0-29.0), [31.0-38.0), DEF(14.2), USE(15.1/1)!, DEF(15.2)!, USE(25.0/2, hint=%eax), USE(27.1/1), PHI_USE(37.2, phi=d_14/3) +R7 (d_18) [SPILL=0x18] + [%xmm0]: [18.0-20.0), DEF(18.0, hint=R5)!, DEF(18.2)! + : [20.0-21.0) + : [21.0-24.0), [26.0-29.0), [31.0-32.3), USE(21.1/2) + [%xmm0]: [32.3-33.0), USE(33.0/1, hint=R11)! +R8 (d_20) [SPILL=0x20] + [%xmm0]: [20.0-21.0), DEF(20.0, hint=R4)!, DEF(20.2)!, USE(21.0/1, hint=R9)! + : [21.0-24.0), [26.0-29.0), [31.0-33.0) + : [33.0-33.1), USE(33.1/2) +R9 (d_21) [%xmm0]: [21.0-22.1), DEF(21.0, hint=R8)!, DEF(21.2)!, USE(22.1/1)! +R10 (d_32) [%xmm1]: [32.0-35.0), DEF(32.0, hint=R4)!, DEF(32.2)!, USE(35.0/1, hint=R12)!, USE(35.0/2) +R11 (d_33) [%xmm0]: [33.0-34.0), DEF(33.0, hint=R7)!, DEF(33.2)!, USE(34.0/1, hint=R5)! +R12 (d_35) [%xmm1]: [35.0-36.0), DEF(35.0, hint=R10)!, DEF(35.2)!, USE(36.0/1, hint=R4)! +[%rax] : [25.0-25.1), [30.0-30.1) +[%xmm0] : [1.0-2.3) +[%xmm1] : [1.0-3.3) +} +test: + subq $0x28, %rsp + movsd %xmm0, (%rsp) + subsd .L4(%rip), %xmm1 + movsd %xmm1, 8(%rsp) + xorpd %xmm1, %xmm1 + xorpd %xmm0, %xmm0 + movsd %xmm0, 0x10(%rsp) + xorl %eax, %eax +.L1: + leal 1(%rax), %eax + movsd 0x10(%rsp), %xmm0 + mulsd %xmm0, %xmm0 + movsd %xmm0, 0x18(%rsp) + movapd %xmm1, %xmm0 + mulsd %xmm1, %xmm0 + movsd %xmm0, 0x20(%rsp) + movsd 0x20(%rsp), %xmm0 + addsd 0x18(%rsp), %xmm0 + ucomisd .L5(%rip), %xmm0 + ja .L2 + cmpl $0x3e8, %eax + jg .L3 + mulsd 0x10(%rsp), %xmm1 + movsd 0x18(%rsp), %xmm0 + subsd 0x20(%rsp), %xmm0 + addsd 8(%rsp), %xmm0 + movsd %xmm0, 0x10(%rsp) + addsd %xmm1, %xmm1 + addsd (%rsp), %xmm1 + jmp .L1 +.L2: + addq $0x28, %rsp + retq +.L3: + xorl %eax, %eax + addq $0x28, %rsp + retq +.rodata + .db 0x90, 0x90, 0x90, 0x90, 0x90 +.L4: + .db 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x3f +.L5: + .db 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x40 diff --git a/tests/x86/abs_001.irt b/tests/x86/abs_001.irt new file mode 100644 index 0000000..04db898 --- /dev/null +++ b/tests/x86/abs_001.irt @@ -0,0 +1,21 @@ +--TEST-- +001: abs function +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + l_1 = START(l_4); + int32_t x = PARAM(l_1, "x", 1); + int32_t ret = ABS(x); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + movl 4(%esp), %eax + movl %eax, %ecx + negl %ecx + cmovsl %eax, %ecx + movl %ecx, %eax + retl diff --git a/tests/x86/abs_002.irt b/tests/x86/abs_002.irt new file mode 100644 index 0000000..f8bcc29 --- /dev/null +++ b/tests/x86/abs_002.irt @@ -0,0 +1,26 @@ +--TEST-- +002: abs function +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + l_1 = START(l_4); + double x = PARAM(l_1, "x", 1); + double ret = ABS(x); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + subl $8, %esp + movsd 0xc(%esp), %xmm0 + andpd .L1, %xmm0 + movsd %xmm0, (%esp) + fldl (%esp) + addl $8, %esp + retl +.rodata + .db 0x90, 0x90, 0x90 +.L1: + .db 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 diff --git a/tests/x86/abs_003.irt b/tests/x86/abs_003.irt new file mode 100644 index 0000000..465538a --- /dev/null +++ b/tests/x86/abs_003.irt @@ -0,0 +1,26 @@ +--TEST-- +003: abs function +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + l_1 = START(l_4); + float x = PARAM(l_1, "x", 1); + float ret = ABS(x); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + subl $4, %esp + movss 8(%esp), %xmm0 + andps .L1, %xmm0 + movss %xmm0, (%esp) + flds (%esp) + addl $4, %esp + retl +.rodata + .db 0x90, 0x90, 0x90, 0x90 +.L1: + .db 0xff, 0xff, 0xff, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 diff --git a/tests/x86/add_001.irt b/tests/x86/add_001.irt new file mode 100644 index 0000000..d835d37 --- /dev/null +++ b/tests/x86/add_001.irt @@ -0,0 +1,20 @@ +--TEST-- +001: add function +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + l_1 = START(l_4); + int32_t x = PARAM(l_1, "x", 1); + int32_t y = PARAM(l_1, "y", 2); + int32_t ret = ADD(x, y); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + movl 4(%esp), %eax + movl 8(%esp), %ecx + leal (%ecx, %eax), %eax + retl diff --git a/tests/x86/add_002.irt b/tests/x86/add_002.irt new file mode 100644 index 0000000..3ad7f50 --- /dev/null +++ b/tests/x86/add_002.irt @@ -0,0 +1,19 @@ +--TEST-- +002: add function +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + int32_t c = 17; + l_1 = START(l_4); + int32_t x = PARAM(l_1, "x", 1); + int32_t ret = ADD(x, c); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + movl 4(%esp), %eax + leal 0x11(%eax), %eax + retl diff --git a/tests/x86/add_003.irt b/tests/x86/add_003.irt new file mode 100644 index 0000000..1abb61f --- /dev/null +++ b/tests/x86/add_003.irt @@ -0,0 +1,20 @@ +--TEST-- +003: add function +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + l_1 = START(l_4); + int32_t x = PARAM(l_1, "x", 1); + int32_t y = PARAM(l_1, "y", 2); + int32_t ret = ADD(y, x); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + movl 4(%esp), %eax + movl 8(%esp), %ecx + leal (%ecx, %eax), %eax + retl diff --git a/tests/x86/add_004.irt b/tests/x86/add_004.irt new file mode 100644 index 0000000..a3e6005 --- /dev/null +++ b/tests/x86/add_004.irt @@ -0,0 +1,19 @@ +--TEST-- +004: add function +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + int32_t c = 17; + l_1 = START(l_4); + int32_t x = PARAM(l_1, "x", 1); + int32_t ret = ADD(c, x); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + movl 4(%esp), %eax + leal 0x11(%eax), %eax + retl diff --git a/tests/x86/add_005.irt b/tests/x86/add_005.irt new file mode 100644 index 0000000..0ad0d5d --- /dev/null +++ b/tests/x86/add_005.irt @@ -0,0 +1,23 @@ +--TEST-- +005: add function +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + l_1 = START(l_4); + double x = PARAM(l_1, "x", 1); + double y = PARAM(l_1, "y", 2); + double ret = ADD(x, y); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + subl $8, %esp + movsd 0x14(%esp), %xmm0 + addsd 0xc(%esp), %xmm0 + movsd %xmm0, (%esp) + fldl (%esp) + addl $8, %esp + retl diff --git a/tests/x86/add_006.irt b/tests/x86/add_006.irt new file mode 100644 index 0000000..73a3488 --- /dev/null +++ b/tests/x86/add_006.irt @@ -0,0 +1,23 @@ +--TEST-- +006: add function +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + l_1 = START(l_4); + double x = PARAM(l_1, "x", 1); + double y = PARAM(l_1, "y", 2); + double ret = ADD(y, x); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + subl $8, %esp + movsd 0x14(%esp), %xmm0 + addsd 0xc(%esp), %xmm0 + movsd %xmm0, (%esp) + fldl (%esp) + addl $8, %esp + retl diff --git a/tests/x86/add_007.irt b/tests/x86/add_007.irt new file mode 100644 index 0000000..9d684ca --- /dev/null +++ b/tests/x86/add_007.irt @@ -0,0 +1,23 @@ +--TEST-- +007: add function +--TARGET-- +x86 +--ARGS-- +-S -mavx +--CODE-- +{ + l_1 = START(l_4); + double x = PARAM(l_1, "x", 1); + double y = PARAM(l_1, "y", 2); + double ret = ADD(x, y); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + subl $8, %esp + vmovsd 0x14(%esp), %xmm0 + vaddsd 0xc(%esp), %xmm0, %xmm0 + vmovsd %xmm0, (%esp) + fldl (%esp) + addl $8, %esp + retl diff --git a/tests/x86/add_008.irt b/tests/x86/add_008.irt new file mode 100644 index 0000000..3c97235 --- /dev/null +++ b/tests/x86/add_008.irt @@ -0,0 +1,23 @@ +--TEST-- +008: add function +--TARGET-- +x86 +--ARGS-- +-S -mavx +--CODE-- +{ + l_1 = START(l_4); + double x = PARAM(l_1, "x", 1); + double y = PARAM(l_1, "y", 2); + double ret = ADD(y, x); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + subl $8, %esp + vmovsd 0x14(%esp), %xmm0 + vaddsd 0xc(%esp), %xmm0, %xmm0 + vmovsd %xmm0, (%esp) + fldl (%esp) + addl $8, %esp + retl diff --git a/tests/x86/add_009.irt b/tests/x86/add_009.irt new file mode 100644 index 0000000..828d26d --- /dev/null +++ b/tests/x86/add_009.irt @@ -0,0 +1,20 @@ +--TEST-- +009: add function +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + uint64_t c = 0x100000000; + l_1 = START(l_4); + uint64_t x = PARAM(l_1, "x", 1); + uint64_t ret = ADD(x, c); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + movq %rdi, %rax + movabsq $0x100000000, %rcx + addq %rcx, %rax + retq diff --git a/tests/x86/add_010.irt b/tests/x86/add_010.irt new file mode 100644 index 0000000..2c7c05e --- /dev/null +++ b/tests/x86/add_010.irt @@ -0,0 +1,19 @@ +--TEST-- +010: add function +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + uint16_t c = 1; + l_1 = START(l_4); + uint16_t x = PARAM(l_1, "x", 1); + uint16_t ret = ADD(x, c); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + movw 4(%esp), %ax + incw %ax + retl diff --git a/tests/x86/add_011.irt b/tests/x86/add_011.irt new file mode 100644 index 0000000..af69dd7 --- /dev/null +++ b/tests/x86/add_011.irt @@ -0,0 +1,27 @@ +--TEST-- +011: add function +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + double c = 0.5; + l_1 = START(l_4); + double x = PARAM(l_1, "x", 1); + double ret = ADD(x, c); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + subl $8, %esp + movsd 0xc(%esp), %xmm0 + addsd .L1, %xmm0 + movsd %xmm0, (%esp) + fldl (%esp) + addl $8, %esp + retl +.rodata + .db 0x90, 0x90, 0x90 +.L1: + .db 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x3f diff --git a/tests/x86/add_012.irt b/tests/x86/add_012.irt new file mode 100644 index 0000000..15fa319 --- /dev/null +++ b/tests/x86/add_012.irt @@ -0,0 +1,27 @@ +--TEST-- +012: add function +--TARGET-- +x86 +--ARGS-- +-S -mavx +--CODE-- +{ + double c = 0.5; + l_1 = START(l_4); + double x = PARAM(l_1, "x", 1); + double ret = ADD(x, c); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + subl $8, %esp + vmovsd 0xc(%esp), %xmm0 + vaddsd .L1, %xmm0, %xmm0 + vmovsd %xmm0, (%esp) + fldl (%esp) + addl $8, %esp + retl +.rodata + .db 0x90, 0x90 +.L1: + .db 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x3f diff --git a/tests/x86/add_ov_001.irt b/tests/x86/add_ov_001.irt new file mode 100644 index 0000000..55a7302 --- /dev/null +++ b/tests/x86/add_ov_001.irt @@ -0,0 +1,21 @@ +--TEST-- +001: add_ov function +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + int32_t c = 2; + l_1 = START(l_2); + int32_t x = PARAM(l_1, "x", 1); + int32_t ret = ADD_OV(x, c); + bool ov = OVERFLOW(ret); + l_2 = RETURN(l_1, ov); +} +--EXPECT-- +test: + movl 4(%esp), %eax + addl $2, %eax + seto %al + retl diff --git a/tests/x86/add_ov_002.irt b/tests/x86/add_ov_002.irt new file mode 100644 index 0000000..8e81399 --- /dev/null +++ b/tests/x86/add_ov_002.irt @@ -0,0 +1,21 @@ +--TEST-- +002: add_ov function +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + uint32_t c = 2; + l_1 = START(l_2); + uint32_t x = PARAM(l_1, "x", 1); + uint32_t ret = ADD_OV(x, c); + bool ov = OVERFLOW(ret); + l_2 = RETURN(l_1, ov); +} +--EXPECT-- +test: + movl 4(%esp), %eax + addl $2, %eax + setb %al + retl diff --git a/tests/x86/add_ov_003.irt b/tests/x86/add_ov_003.irt new file mode 100644 index 0000000..701bf36 --- /dev/null +++ b/tests/x86/add_ov_003.irt @@ -0,0 +1,31 @@ +--TEST-- +003: add_ov function +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + int32_t c_1 = 0; + int32_t c = 2; + l_1 = START(l_8); + int32_t x = PARAM(l_1, "x", 1); + int32_t ret1 = ADD_OV(x, c); + bool ov = OVERFLOW(ret1); + l_2 = IF(l_1, ov); + l_3 = IF_TRUE(l_2); + l_4 = END(l_3); + l_5 = IF_FALSE(l_2); + l_6 = END(l_5); + l_7 = MERGE(l_4, l_6); + int32_t ret = PHI(l_7, c_1, ret1); + l_8 = RETURN(l_7, ret); +} +--EXPECT-- +test: + movl 4(%esp), %eax + addl $2, %eax + jno .L1 + xorl %eax, %eax +.L1: + retl diff --git a/tests/x86/add_ov_004.irt b/tests/x86/add_ov_004.irt new file mode 100644 index 0000000..eb2ea2b --- /dev/null +++ b/tests/x86/add_ov_004.irt @@ -0,0 +1,33 @@ +--TEST-- +004: add_ov function (jmp probability) +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + int32_t c_1 = 0; + int32_t c = 2; + l_1 = START(l_8); + int32_t x = PARAM(l_1, "x", 1); + int32_t ret1 = ADD_OV(x, c); + bool ov = OVERFLOW(ret1); + l_2 = IF(l_1, ov); + l_3 = IF_TRUE(l_2, 1); + l_4 = END(l_3); + l_5 = IF_FALSE(l_2); + l_6 = END(l_5); + l_7 = MERGE(l_4, l_6); + int32_t ret = PHI(l_7, c_1, ret1); + l_8 = RETURN(l_7, ret); +} +--EXPECT-- +test: + movl 4(%esp), %eax + addl $2, %eax + jo .L2 +.L1: + retl +.L2: + xorl %eax, %eax + jmp .L1 diff --git a/tests/x86/alloca_001.irt b/tests/x86/alloca_001.irt new file mode 100644 index 0000000..4c0b71f --- /dev/null +++ b/tests/x86/alloca_001.irt @@ -0,0 +1,22 @@ +--TEST-- +001: alloca function +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + int32_t size = 10; + l_1 = START(l_4); + uintptr_t ret, l_2 = ALLOCA(l_1, size); + l_4 = RETURN(l_2, ret); +} +--EXPECT-- +test: + pushl %ebp + movl %esp, %ebp + subl $0x10, %esp + movl %esp, %eax + movl %ebp, %esp + popl %ebp + retl diff --git a/tests/x86/alloca_002.irt b/tests/x86/alloca_002.irt new file mode 100644 index 0000000..65b005e --- /dev/null +++ b/tests/x86/alloca_002.irt @@ -0,0 +1,25 @@ +--TEST-- +002: alloca function +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + l_1 = START(l_4); + int32_t x = PARAM(l_1, "x", 1); + uintptr_t ret, l_2 = ALLOCA(l_1, x); + l_4 = RETURN(l_2, ret); +} +--EXPECT-- +test: + pushl %ebp + movl %esp, %ebp + movl 8(%ebp), %eax + addl $7, %eax + andl $0xfffffff8, %eax + subl %eax, %esp + movl %esp, %eax + movl %ebp, %esp + popl %ebp + retl diff --git a/tests/x86/bswap_001.irt b/tests/x86/bswap_001.irt new file mode 100644 index 0000000..0bab96c --- /dev/null +++ b/tests/x86/bswap_001.irt @@ -0,0 +1,18 @@ +--TEST-- +001: bswap function +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + l_1 = START(l_4); + int32_t x = PARAM(l_1, "x", 1); + int32_t ret = BSWAP(x); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + movl 4(%esp), %eax + bswapl %eax + retl diff --git a/tests/x86/conv_001.irt b/tests/x86/conv_001.irt new file mode 100644 index 0000000..34416ab --- /dev/null +++ b/tests/x86/conv_001.irt @@ -0,0 +1,17 @@ +--TEST-- +001: type conversion SEXT +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + l_1 = START(l_4); + int32_t x = PARAM(l_1, "x", 1); + int64_t ret = SEXT(x); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + movslq %edi, %rax + retq diff --git a/tests/x86/conv_002.irt b/tests/x86/conv_002.irt new file mode 100644 index 0000000..3191a9f --- /dev/null +++ b/tests/x86/conv_002.irt @@ -0,0 +1,17 @@ +--TEST-- +002: type conversion ZEXT +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + l_1 = START(l_4); + uint32_t x = PARAM(l_1, "x", 1); + uint64_t ret = ZEXT(x); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + movl %edi, %eax + retq diff --git a/tests/x86/conv_003.irt b/tests/x86/conv_003.irt new file mode 100644 index 0000000..ef4d1fe --- /dev/null +++ b/tests/x86/conv_003.irt @@ -0,0 +1,18 @@ +--TEST-- +003: type conversion BITCAST +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + l_1 = START(l_4); + int32_t x = PARAM(l_1, "x", 1); + uint32_t ret = BITCAST(x); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + movl 4(%esp), %eax + retl + diff --git a/tests/x86/conv_004.irt b/tests/x86/conv_004.irt new file mode 100644 index 0000000..1796947 --- /dev/null +++ b/tests/x86/conv_004.irt @@ -0,0 +1,17 @@ +--TEST-- +004: type conversion BITCAST +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + l_1 = START(l_4); + double x = PARAM(l_1, "x", 1); + uint64_t ret = BITCAST(x); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + movd %xmm0, %rax + retq diff --git a/tests/x86/conv_005.irt b/tests/x86/conv_005.irt new file mode 100644 index 0000000..2d7c871 --- /dev/null +++ b/tests/x86/conv_005.irt @@ -0,0 +1,18 @@ +--TEST-- +005: type conversion BITCAST +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + l_1 = START(l_4); + float x = PARAM(l_1, "x", 1); + uint32_t ret = BITCAST(x); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + movss 4(%esp), %xmm0 + movd %xmm0, %eax + retl diff --git a/tests/x86/conv_006.irt b/tests/x86/conv_006.irt new file mode 100644 index 0000000..ad7d4a5 --- /dev/null +++ b/tests/x86/conv_006.irt @@ -0,0 +1,22 @@ +--TEST-- +006: type conversion INT2FP +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + l_1 = START(l_4); + int32_t x = PARAM(l_1, "x", 1); + double ret = INT2FP(x); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + subl $8, %esp + movl 0xc(%esp), %eax + cvtsi2sdl %eax, %xmm0 + movsd %xmm0, (%esp) + fldl (%esp) + addl $8, %esp + retl diff --git a/tests/x86/conv_007.irt b/tests/x86/conv_007.irt new file mode 100644 index 0000000..9a2366d --- /dev/null +++ b/tests/x86/conv_007.irt @@ -0,0 +1,18 @@ +--TEST-- +007: type conversion FP2INT +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + l_1 = START(l_4); + float x = PARAM(l_1, "x", 1); + int32_t ret = FP2INT(x); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + movss 4(%esp), %xmm0 + cvtss2si %xmm0, %eax + retl diff --git a/tests/x86/conv_008.irt b/tests/x86/conv_008.irt new file mode 100644 index 0000000..7e76734 --- /dev/null +++ b/tests/x86/conv_008.irt @@ -0,0 +1,22 @@ +--TEST-- +008: type conversion FP2FP +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + l_1 = START(l_4); + float x = PARAM(l_1, "x", 1); + double ret = FP2FP(x); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + subl $8, %esp + movss 0xc(%esp), %xmm0 + cvtss2sd %xmm0, %xmm0 + movsd %xmm0, (%esp) + fldl (%esp) + addl $8, %esp + retl diff --git a/tests/x86/conv_009.irt b/tests/x86/conv_009.irt new file mode 100644 index 0000000..64bc6d7 --- /dev/null +++ b/tests/x86/conv_009.irt @@ -0,0 +1,22 @@ +--TEST-- +009: type conversion FP2FP +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + l_1 = START(l_4); + double x = PARAM(l_1, "x", 1); + float ret = FP2FP(x); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + subl $4, %esp + movsd 8(%esp), %xmm0 + cvtsd2ss %xmm0, %xmm0 + movss %xmm0, (%esp) + flds (%esp) + addl $4, %esp + retl diff --git a/tests/x86/conv_010.irt b/tests/x86/conv_010.irt new file mode 100644 index 0000000..8cc1608 --- /dev/null +++ b/tests/x86/conv_010.irt @@ -0,0 +1,17 @@ +--TEST-- +010: type conversion BITCAST +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + l_1 = START(l_4); + uint64_t x = PARAM(l_1, "x", 1); + double ret = BITCAST(x); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + movd %rdi, %xmm0 + retq diff --git a/tests/x86/conv_011.irt b/tests/x86/conv_011.irt new file mode 100644 index 0000000..c9e6d53 --- /dev/null +++ b/tests/x86/conv_011.irt @@ -0,0 +1,17 @@ +--TEST-- +011: type conversion TRUNC +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + l_1 = START(l_4); + int32_t x = PARAM(l_1, "x", 1); + int8_t ret = TRUNC(x); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + movl 4(%esp), %eax + retl diff --git a/tests/x86/div_001.irt b/tests/x86/div_001.irt new file mode 100644 index 0000000..509fe72 --- /dev/null +++ b/tests/x86/div_001.irt @@ -0,0 +1,20 @@ +--TEST-- +001: div function +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + l_1 = START(l_4); + int32_t x = PARAM(l_1, "x", 1); + int32_t y = PARAM(l_1, "y", 2); + int32_t ret = DIV(x, y); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + movl 4(%esp), %eax + cltd + idivl 8(%esp) + retl diff --git a/tests/x86/div_002.irt b/tests/x86/div_002.irt new file mode 100644 index 0000000..139f63c --- /dev/null +++ b/tests/x86/div_002.irt @@ -0,0 +1,21 @@ +--TEST-- +002: div function +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + int32_t c = 17; + l_1 = START(l_4); + int32_t x = PARAM(l_1, "x", 1); + int32_t ret = DIV(x, c); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + movl 4(%esp), %eax + movl $0x11, %ecx + cltd + idivl %ecx + retl diff --git a/tests/x86/div_003.irt b/tests/x86/div_003.irt new file mode 100644 index 0000000..5a3bd5f --- /dev/null +++ b/tests/x86/div_003.irt @@ -0,0 +1,20 @@ +--TEST-- +003: div function +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + l_1 = START(l_4); + int32_t x = PARAM(l_1, "x", 1); + int32_t y = PARAM(l_1, "y", 2); + int32_t ret = DIV(y, x); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + movl 8(%esp), %eax + cltd + idivl 4(%esp) + retl diff --git a/tests/x86/div_004.irt b/tests/x86/div_004.irt new file mode 100644 index 0000000..430bb0a --- /dev/null +++ b/tests/x86/div_004.irt @@ -0,0 +1,20 @@ +--TEST-- +004: div function +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + int32_t c = 17; + l_1 = START(l_4); + int32_t x = PARAM(l_1, "x", 1); + int32_t ret = DIV(c, x); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + movl $0x11, %eax + cltd + idivl 4(%esp) + retl diff --git a/tests/x86/div_005.irt b/tests/x86/div_005.irt new file mode 100644 index 0000000..643a727 --- /dev/null +++ b/tests/x86/div_005.irt @@ -0,0 +1,19 @@ +--TEST-- +005: div function +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + uint32_t c = 16; + l_1 = START(l_4); + uint32_t x = PARAM(l_1, "x", 1); + uint32_t ret = DIV(x, c); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + movl 4(%esp), %eax + shrl $4, %eax + retl diff --git a/tests/x86/div_006.irt b/tests/x86/div_006.irt new file mode 100644 index 0000000..03148cb --- /dev/null +++ b/tests/x86/div_006.irt @@ -0,0 +1,20 @@ +--TEST-- +006: div function +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + l_1 = START(l_4); + uint32_t x = PARAM(l_1, "x", 1); + uint32_t y = PARAM(l_1, "y", 2); + uint32_t ret = DIV(x, y); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + movl 4(%esp), %eax + xorl %edx, %edx + divl 8(%esp) + retl diff --git a/tests/x86/eq_001.irt b/tests/x86/eq_001.irt new file mode 100644 index 0000000..ea4f394 --- /dev/null +++ b/tests/x86/eq_001.irt @@ -0,0 +1,20 @@ +--TEST-- +001: eq function +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + l_1 = START(l_4); + int32_t x = PARAM(l_1, "x", 1); + int32_t y = PARAM(l_1, "y", 2); + bool ret = EQ(x, y); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + movl 8(%esp), %eax + cmpl 4(%esp), %eax + sete %al + retl diff --git a/tests/x86/eq_002.irt b/tests/x86/eq_002.irt new file mode 100644 index 0000000..9add543 --- /dev/null +++ b/tests/x86/eq_002.irt @@ -0,0 +1,19 @@ +--TEST-- +002: eq function +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + int32_t c = 17; + l_1 = START(l_4); + int32_t x = PARAM(l_1, "x", 1); + bool ret = EQ(x, c); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + cmpl $0x11, 4(%esp) + sete %al + retl diff --git a/tests/x86/eq_003.irt b/tests/x86/eq_003.irt new file mode 100644 index 0000000..3084eca --- /dev/null +++ b/tests/x86/eq_003.irt @@ -0,0 +1,19 @@ +--TEST-- +003: eq function +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + int32_t c = 0; + l_1 = START(l_4); + int32_t x = PARAM(l_1, "x", 1); + bool ret = EQ(x, c); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + cmpl $0, 4(%esp) + sete %al + retl diff --git a/tests/x86/eq_004.irt b/tests/x86/eq_004.irt new file mode 100644 index 0000000..b9096da --- /dev/null +++ b/tests/x86/eq_004.irt @@ -0,0 +1,26 @@ +--TEST-- +004: eq function +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + double c = 0; + l_1 = START(l_4); + double x = PARAM(l_1, "x", 1); + bool ret = EQ(x, c); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + movsd 4(%esp), %xmm0 + ucomisd .L1, %xmm0 + setnp %al + movl $0, %ecx + cmovnel %ecx, %eax + retl +.rodata + .db 0x90, 0x90, 0x90, 0x90, 0x90, 0x90 +.L1: + .db 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 diff --git a/tests/x86/eq_005.irt b/tests/x86/eq_005.irt new file mode 100644 index 0000000..0d90775 --- /dev/null +++ b/tests/x86/eq_005.irt @@ -0,0 +1,26 @@ +--TEST-- +005: eq function +--TARGET-- +x86 +--ARGS-- +-S -mavx +--CODE-- +{ + double c = 0; + l_1 = START(l_4); + double x = PARAM(l_1, "x", 1); + bool ret = EQ(x, c); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + vmovsd 4(%esp), %xmm0 + vucomisd .L1, %xmm0 + setnp %al + movl $0, %ecx + cmovnel %ecx, %eax + retl +.rodata + .db 0x90, 0x90, 0x90, 0x90, 0x90, 0x90 +.L1: + .db 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 diff --git a/tests/x86/ge_001.irt b/tests/x86/ge_001.irt new file mode 100644 index 0000000..71bddce --- /dev/null +++ b/tests/x86/ge_001.irt @@ -0,0 +1,20 @@ +--TEST-- +001: ge function +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + l_1 = START(l_4); + int32_t x = PARAM(l_1, "x", 1); + int32_t y = PARAM(l_1, "y", 2); + bool ret = GE(x, y); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + movl 8(%esp), %eax + cmpl 4(%esp), %eax + setle %al + retl diff --git a/tests/x86/ge_002.irt b/tests/x86/ge_002.irt new file mode 100644 index 0000000..b08a1e0 --- /dev/null +++ b/tests/x86/ge_002.irt @@ -0,0 +1,19 @@ +--TEST-- +002: ge function +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + int32_t c = 17; + l_1 = START(l_4); + int32_t x = PARAM(l_1, "x", 1); + bool ret = GE(x, c); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + cmpl $0x11, 4(%esp) + setge %al + retl diff --git a/tests/x86/ge_003.irt b/tests/x86/ge_003.irt new file mode 100644 index 0000000..3c56df4 --- /dev/null +++ b/tests/x86/ge_003.irt @@ -0,0 +1,19 @@ +--TEST-- +003: ge function +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + int32_t c = 0; + l_1 = START(l_4); + int32_t x = PARAM(l_1, "x", 1); + bool ret = GE(x, c); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + cmpl $0, 4(%esp) + setge %al + retl diff --git a/tests/x86/ge_004.irt b/tests/x86/ge_004.irt new file mode 100644 index 0000000..2fcb6e2 --- /dev/null +++ b/tests/x86/ge_004.irt @@ -0,0 +1,24 @@ +--TEST-- +004: ge function +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + double c = 0; + l_1 = START(l_4); + double x = PARAM(l_1, "x", 1); + bool ret = GE(x, c); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + movsd 4(%esp), %xmm0 + ucomisd .L1, %xmm0 + setae %al + retl +.rodata + .db 0x90, 0x90, 0x90, 0x90, 0x90, 0x90 +.L1: + .db 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 diff --git a/tests/x86/ge_005.irt b/tests/x86/ge_005.irt new file mode 100644 index 0000000..e9c74d1 --- /dev/null +++ b/tests/x86/ge_005.irt @@ -0,0 +1,24 @@ +--TEST-- +005: ge function +--TARGET-- +x86 +--ARGS-- +-S -mavx +--CODE-- +{ + double c = 0; + l_1 = START(l_4); + double x = PARAM(l_1, "x", 1); + bool ret = GE(x, c); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + vmovsd 4(%esp), %xmm0 + vucomisd .L1, %xmm0 + setae %al + retl +.rodata + .db 0x90, 0x90, 0x90, 0x90, 0x90, 0x90 +.L1: + .db 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 diff --git a/tests/x86/gt_001.irt b/tests/x86/gt_001.irt new file mode 100644 index 0000000..3624bfe --- /dev/null +++ b/tests/x86/gt_001.irt @@ -0,0 +1,20 @@ +--TEST-- +001: gt function +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + l_1 = START(l_4); + int32_t x = PARAM(l_1, "x", 1); + int32_t y = PARAM(l_1, "y", 2); + bool ret = GT(x, y); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + movl 8(%esp), %eax + cmpl 4(%esp), %eax + setl %al + retl diff --git a/tests/x86/gt_002.irt b/tests/x86/gt_002.irt new file mode 100644 index 0000000..50904eb --- /dev/null +++ b/tests/x86/gt_002.irt @@ -0,0 +1,19 @@ +--TEST-- +002: gt function +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + int32_t c = 17; + l_1 = START(l_4); + int32_t x = PARAM(l_1, "x", 1); + bool ret = GT(x, c); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + cmpl $0x11, 4(%esp) + setg %al + retl diff --git a/tests/x86/gt_003.irt b/tests/x86/gt_003.irt new file mode 100644 index 0000000..77e6ee9 --- /dev/null +++ b/tests/x86/gt_003.irt @@ -0,0 +1,19 @@ +--TEST-- +003: gt function +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + int32_t c = 0; + l_1 = START(l_4); + int32_t x = PARAM(l_1, "x", 1); + bool ret = GT(x, c); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + cmpl $0, 4(%esp) + setg %al + retl diff --git a/tests/x86/gt_004.irt b/tests/x86/gt_004.irt new file mode 100644 index 0000000..08e2dc5 --- /dev/null +++ b/tests/x86/gt_004.irt @@ -0,0 +1,24 @@ +--TEST-- +004: gt function +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + double c = 0; + l_1 = START(l_4); + double x = PARAM(l_1, "x", 1); + bool ret = GT(x, c); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + movsd 4(%esp), %xmm0 + ucomisd .L1, %xmm0 + seta %al + retl +.rodata + .db 0x90, 0x90, 0x90, 0x90, 0x90, 0x90 +.L1: + .db 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 diff --git a/tests/x86/gt_005.irt b/tests/x86/gt_005.irt new file mode 100644 index 0000000..1357350 --- /dev/null +++ b/tests/x86/gt_005.irt @@ -0,0 +1,24 @@ +--TEST-- +005: gt function +--TARGET-- +x86 +--ARGS-- +-S -mavx +--CODE-- +{ + double c = 0; + l_1 = START(l_4); + double x = PARAM(l_1, "x", 1); + bool ret = GT(x, c); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + vmovsd 4(%esp), %xmm0 + vucomisd .L1, %xmm0 + seta %al + retl +.rodata + .db 0x90, 0x90, 0x90, 0x90, 0x90, 0x90 +.L1: + .db 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 diff --git a/tests/x86/if_001.irt b/tests/x86/if_001.irt new file mode 100644 index 0000000..d609c22 --- /dev/null +++ b/tests/x86/if_001.irt @@ -0,0 +1,31 @@ +--TEST-- +001: if function +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + int32_t c_1 = 0; + int32_t c_2 = 42; + l_1 = START(l_8); + int32_t x = PARAM(l_1, "x", 1); + l_2 = IF(l_1, x); + l_3 = IF_TRUE(l_2); + l_4 = END(l_3); + l_5 = IF_FALSE(l_2); + l_6 = END(l_5); + l_7 = MERGE(l_4, l_6); + int32_t ret = PHI(l_7, c_1, c_2); + l_8 = RETURN(l_7, ret); +} +--EXPECT-- +test: + cmpl $0, 4(%esp) + je .L2 + xorl %eax, %eax +.L1: + retl +.L2: + movl $0x2a, %eax + jmp .L1 diff --git a/tests/x86/jcc_001.irt b/tests/x86/jcc_001.irt new file mode 100644 index 0000000..3a399c0 --- /dev/null +++ b/tests/x86/jcc_001.irt @@ -0,0 +1,31 @@ +--TEST-- +001: IF(_, ADD(_,_)) -> JCC +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + int32_t c1 = 0; + int32_t c2 = 1; + int32_t c3 = -1; + l_1 = START(l_8); + int32_t x = PARAM(l_1, "x", 1); + int32_t d_1 = ADD(x, c2); + l_2 = IF(l_1, d_1); + l_3 = IF_FALSE(l_2); + l_4 = END(l_3); + l_5 = IF_TRUE(l_2); + l_6 = END(l_5); + l_7 = MERGE(l_4, l_6); + int32_t ret = PHI(l_7, c3, d_1); + l_8 = RETURN(l_7, ret); +} +--EXPECT-- +test: + movl 4(%esp), %eax + addl $1, %eax + jne .L1 + movl $0xffffffff, %eax +.L1: + retl diff --git a/tests/x86/le_001.irt b/tests/x86/le_001.irt new file mode 100644 index 0000000..fe34fc1 --- /dev/null +++ b/tests/x86/le_001.irt @@ -0,0 +1,20 @@ +--TEST-- +001: le function +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + l_1 = START(l_4); + int32_t x = PARAM(l_1, "x", 1); + int32_t y = PARAM(l_1, "y", 2); + bool ret = LE(x, y); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + movl 8(%esp), %eax + cmpl 4(%esp), %eax + setge %al + retl diff --git a/tests/x86/le_002.irt b/tests/x86/le_002.irt new file mode 100644 index 0000000..c613a3b --- /dev/null +++ b/tests/x86/le_002.irt @@ -0,0 +1,19 @@ +--TEST-- +002: le function +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + int32_t c = 17; + l_1 = START(l_4); + int32_t x = PARAM(l_1, "x", 1); + bool ret = LE(x, c); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + cmpl $0x11, 4(%esp) + setle %al + retl diff --git a/tests/x86/le_003.irt b/tests/x86/le_003.irt new file mode 100644 index 0000000..ac7cd75 --- /dev/null +++ b/tests/x86/le_003.irt @@ -0,0 +1,19 @@ +--TEST-- +003: le function +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + int32_t c = 0; + l_1 = START(l_4); + int32_t x = PARAM(l_1, "x", 1); + bool ret = LE(x, c); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + cmpl $0, 4(%esp) + setle %al + retl diff --git a/tests/x86/le_004.irt b/tests/x86/le_004.irt new file mode 100644 index 0000000..0a03c2f --- /dev/null +++ b/tests/x86/le_004.irt @@ -0,0 +1,20 @@ +--TEST-- +004: le function +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + double c = 0; + l_1 = START(l_4); + double x = PARAM(l_1, "x", 1); + bool ret = LE(x, c); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + xorpd %xmm0, %xmm0 + ucomisd 4(%esp), %xmm0 + setae %al + retl diff --git a/tests/x86/le_005.irt b/tests/x86/le_005.irt new file mode 100644 index 0000000..86645e8 --- /dev/null +++ b/tests/x86/le_005.irt @@ -0,0 +1,20 @@ +--TEST-- +005: le function +--TARGET-- +x86 +--ARGS-- +-S -mavx +--CODE-- +{ + double c = 0; + l_1 = START(l_4); + double x = PARAM(l_1, "x", 1); + bool ret = LE(x, c); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + vxorpd %xmm0, %xmm0, %xmm0 + vucomisd 4(%esp), %xmm0 + setae %al + retl diff --git a/tests/x86/lt_001.irt b/tests/x86/lt_001.irt new file mode 100644 index 0000000..17decf1 --- /dev/null +++ b/tests/x86/lt_001.irt @@ -0,0 +1,20 @@ +--TEST-- +001: lt function +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + l_1 = START(l_4); + int32_t x = PARAM(l_1, "x", 1); + int32_t y = PARAM(l_1, "y", 2); + bool ret = LT(x, y); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + movl 8(%esp), %eax + cmpl 4(%esp), %eax + setg %al + retl diff --git a/tests/x86/lt_002.irt b/tests/x86/lt_002.irt new file mode 100644 index 0000000..bb5d025 --- /dev/null +++ b/tests/x86/lt_002.irt @@ -0,0 +1,19 @@ +--TEST-- +002: lt function +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + int32_t c = 17; + l_1 = START(l_4); + int32_t x = PARAM(l_1, "x", 1); + bool ret = LT(x, c); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + cmpl $0x11, 4(%esp) + setl %al + retl diff --git a/tests/x86/lt_003.irt b/tests/x86/lt_003.irt new file mode 100644 index 0000000..6c031ec --- /dev/null +++ b/tests/x86/lt_003.irt @@ -0,0 +1,19 @@ +--TEST-- +003: lt function +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + int32_t c = 0; + l_1 = START(l_4); + int32_t x = PARAM(l_1, "x", 1); + bool ret = LT(x, c); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + cmpl $0, 4(%esp) + setl %al + retl diff --git a/tests/x86/lt_004.irt b/tests/x86/lt_004.irt new file mode 100644 index 0000000..dd3dcf7 --- /dev/null +++ b/tests/x86/lt_004.irt @@ -0,0 +1,20 @@ +--TEST-- +004: lt function +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + double c = 0; + l_1 = START(l_4); + double x = PARAM(l_1, "x", 1); + bool ret = LT(x, c); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + xorpd %xmm0, %xmm0 + ucomisd 4(%esp), %xmm0 + seta %al + retl diff --git a/tests/x86/lt_005.irt b/tests/x86/lt_005.irt new file mode 100644 index 0000000..c3a0493 --- /dev/null +++ b/tests/x86/lt_005.irt @@ -0,0 +1,20 @@ +--TEST-- +005: lt function +--TARGET-- +x86 +--ARGS-- +-S -mavx +--CODE-- +{ + double c = 0; + l_1 = START(l_4); + double x = PARAM(l_1, "x", 1); + bool ret = LT(x, c); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + vxorpd %xmm0, %xmm0, %xmm0 + vucomisd 4(%esp), %xmm0 + seta %al + retl diff --git a/tests/x86/min_001.irt b/tests/x86/min_001.irt new file mode 100644 index 0000000..f90c4fb --- /dev/null +++ b/tests/x86/min_001.irt @@ -0,0 +1,23 @@ +--TEST-- +001: min function +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + l_1 = START(l_4); + float x = PARAM(l_1, "x", 1); + float y = PARAM(l_1, "y", 2); + float ret = MIN(x, y); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + subl $4, %esp + movss 0xc(%esp), %xmm0 + minss 8(%esp), %xmm0 + movss %xmm0, (%esp) + flds (%esp) + addl $4, %esp + retl diff --git a/tests/x86/min_002.irt b/tests/x86/min_002.irt new file mode 100644 index 0000000..2695162 --- /dev/null +++ b/tests/x86/min_002.irt @@ -0,0 +1,23 @@ +--TEST-- +002: min function +--TARGET-- +x86 +--ARGS-- +-S -mavx +--CODE-- +{ + l_1 = START(l_4); + float x = PARAM(l_1, "x", 1); + float y = PARAM(l_1, "y", 2); + float ret = MIN(x, y); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + subl $4, %esp + vmovss 0xc(%esp), %xmm0 + vminss 8(%esp), %xmm0, %xmm0 + vmovss %xmm0, (%esp) + flds (%esp) + addl $4, %esp + retl diff --git a/tests/x86/min_003.irt b/tests/x86/min_003.irt new file mode 100644 index 0000000..d313063 --- /dev/null +++ b/tests/x86/min_003.irt @@ -0,0 +1,23 @@ +--TEST-- +003: min function +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + l_1 = START(l_4); + double x = PARAM(l_1, "x", 1); + double y = PARAM(l_1, "y", 2); + double ret = MIN(x, y); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + subl $8, %esp + movsd 0x14(%esp), %xmm0 + minsd 0xc(%esp), %xmm0 + movsd %xmm0, (%esp) + fldl (%esp) + addl $8, %esp + retl diff --git a/tests/x86/min_004.irt b/tests/x86/min_004.irt new file mode 100644 index 0000000..85aaaf9 --- /dev/null +++ b/tests/x86/min_004.irt @@ -0,0 +1,23 @@ +--TEST-- +004: min function +--TARGET-- +x86 +--ARGS-- +-S -mavx +--CODE-- +{ + l_1 = START(l_4); + double x = PARAM(l_1, "x", 1); + double y = PARAM(l_1, "y", 2); + double ret = MIN(x, y); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + subl $8, %esp + vmovsd 0x14(%esp), %xmm0 + vminsd 0xc(%esp), %xmm0, %xmm0 + vmovsd %xmm0, (%esp) + fldl (%esp) + addl $8, %esp + retl diff --git a/tests/x86/min_005.irt b/tests/x86/min_005.irt new file mode 100644 index 0000000..e3dab8d --- /dev/null +++ b/tests/x86/min_005.irt @@ -0,0 +1,22 @@ +--TEST-- +005: min function +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + l_1 = START(l_4); + int32_t x = PARAM(l_1, "x", 1); + int32_t y = PARAM(l_1, "y", 2); + int32_t ret = MIN(x, y); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + movl 4(%esp), %eax + movl 8(%esp), %ecx + cmpl %eax, %ecx + cmovll %eax, %ecx + movl %ecx, %eax + retl diff --git a/tests/x86/min_006.irt b/tests/x86/min_006.irt new file mode 100644 index 0000000..453c9e9 --- /dev/null +++ b/tests/x86/min_006.irt @@ -0,0 +1,22 @@ +--TEST-- +006: min function +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + l_1 = START(l_4); + uint8_t x = PARAM(l_1, "x", 1); + uint8_t y = PARAM(l_1, "y", 2); + uint8_t ret = MIN(x, y); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + movb 4(%esp), %al + movb 8(%esp), %cl + cmpb %al, %cl + cmovbw %ax, %cx + movb %cl, %al + retl diff --git a/tests/x86/min_007.irt b/tests/x86/min_007.irt new file mode 100644 index 0000000..599ca3c --- /dev/null +++ b/tests/x86/min_007.irt @@ -0,0 +1,21 @@ +--TEST-- +007: min function +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + int32_t c = 47; + l_1 = START(l_4); + int32_t x = PARAM(l_1, "x", 1); + int32_t ret = MIN(x, c); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + movl 4(%esp), %eax + movl $0x2f, %ecx + cmpl %ecx, %eax + cmovll %ecx, %eax + retl diff --git a/tests/x86/mod_001.irt b/tests/x86/mod_001.irt new file mode 100644 index 0000000..aa72fd1 --- /dev/null +++ b/tests/x86/mod_001.irt @@ -0,0 +1,21 @@ +--TEST-- +001: mod function +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + l_1 = START(l_4); + int32_t x = PARAM(l_1, "x", 1); + int32_t y = PARAM(l_1, "y", 2); + int32_t ret = MOD(x, y); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + movl 4(%esp), %eax + cltd + idivl 8(%esp) + movl %edx, %eax + retl diff --git a/tests/x86/mod_002.irt b/tests/x86/mod_002.irt new file mode 100644 index 0000000..bf2a241 --- /dev/null +++ b/tests/x86/mod_002.irt @@ -0,0 +1,22 @@ +--TEST-- +002: mod function +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + int32_t c = 17; + l_1 = START(l_4); + int32_t x = PARAM(l_1, "x", 1); + int32_t ret = MOD(x, c); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + movl 4(%esp), %eax + movl $0x11, %ecx + cltd + idivl %ecx + movl %edx, %eax + retl diff --git a/tests/x86/mod_003.irt b/tests/x86/mod_003.irt new file mode 100644 index 0000000..1b6071d --- /dev/null +++ b/tests/x86/mod_003.irt @@ -0,0 +1,21 @@ +--TEST-- +003: mod function +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + l_1 = START(l_4); + int32_t x = PARAM(l_1, "x", 1); + int32_t y = PARAM(l_1, "y", 2); + int32_t ret = MOD(y, x); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + movl 8(%esp), %eax + cltd + idivl 4(%esp) + movl %edx, %eax + retl diff --git a/tests/x86/mod_004.irt b/tests/x86/mod_004.irt new file mode 100644 index 0000000..fcd359a --- /dev/null +++ b/tests/x86/mod_004.irt @@ -0,0 +1,21 @@ +--TEST-- +004: mod function +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + int32_t c = 17; + l_1 = START(l_4); + int32_t x = PARAM(l_1, "x", 1); + int32_t ret = MOD(c, x); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + movl $0x11, %eax + cltd + idivl 4(%esp) + movl %edx, %eax + retl diff --git a/tests/x86/mod_005.irt b/tests/x86/mod_005.irt new file mode 100644 index 0000000..da98b81 --- /dev/null +++ b/tests/x86/mod_005.irt @@ -0,0 +1,19 @@ +--TEST-- +005: mod function +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + uint32_t c = 16; + l_1 = START(l_4); + uint32_t x = PARAM(l_1, "x", 1); + uint32_t ret = MOD(x, c); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + movl 4(%esp), %eax + andl $0xf, %eax + retl diff --git a/tests/x86/mul_001.irt b/tests/x86/mul_001.irt new file mode 100644 index 0000000..9af66a6 --- /dev/null +++ b/tests/x86/mul_001.irt @@ -0,0 +1,19 @@ +--TEST-- +001: mul function +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + l_1 = START(l_4); + uint32_t x = PARAM(l_1, "x", 1); + uint32_t y = PARAM(l_1, "y", 2); + uint32_t ret = MUL(x, y); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + movl 8(%esp), %eax + mull 4(%esp) + retl diff --git a/tests/x86/mul_002.irt b/tests/x86/mul_002.irt new file mode 100644 index 0000000..21cf215 --- /dev/null +++ b/tests/x86/mul_002.irt @@ -0,0 +1,20 @@ +--TEST-- +002: mul function +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + uint32_t c = 17; + l_1 = START(l_4); + uint32_t x = PARAM(l_1, "x", 1); + uint32_t ret = MUL(x, c); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + movl 4(%esp), %eax + movl $0x11, %edx + mull %edx + retl diff --git a/tests/x86/mul_003.irt b/tests/x86/mul_003.irt new file mode 100644 index 0000000..777304f --- /dev/null +++ b/tests/x86/mul_003.irt @@ -0,0 +1,19 @@ +--TEST-- +003: mul function +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + l_1 = START(l_4); + uint32_t x = PARAM(l_1, "x", 1); + uint32_t y = PARAM(l_1, "y", 2); + uint32_t ret = MUL(y, x); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + movl 8(%esp), %eax + mull 4(%esp) + retl diff --git a/tests/x86/mul_004.irt b/tests/x86/mul_004.irt new file mode 100644 index 0000000..4bd8cbe --- /dev/null +++ b/tests/x86/mul_004.irt @@ -0,0 +1,20 @@ +--TEST-- +004: mul function +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + uint32_t c = 17; + l_1 = START(l_4); + uint32_t x = PARAM(l_1, "x", 1); + uint32_t ret = MUL(c, x); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + movl 4(%esp), %eax + movl $0x11, %edx + mull %edx + retl diff --git a/tests/x86/mul_005.irt b/tests/x86/mul_005.irt new file mode 100644 index 0000000..7eff09c --- /dev/null +++ b/tests/x86/mul_005.irt @@ -0,0 +1,19 @@ +--TEST-- +005: mul function +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + uint32_t c = 2; + l_1 = START(l_4); + uint16_t x = PARAM(l_1, "x", 1); + uint16_t ret = MUL(c, x); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + movw 4(%esp), %ax + addw %ax, %ax + retl diff --git a/tests/x86/mul_006.irt b/tests/x86/mul_006.irt new file mode 100644 index 0000000..9c8d4cd --- /dev/null +++ b/tests/x86/mul_006.irt @@ -0,0 +1,19 @@ +--TEST-- +006: mul function +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + uint32_t c = 16; + l_1 = START(l_4); + uint16_t x = PARAM(l_1, "x", 1); + uint16_t ret = MUL(c, x); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + movw 4(%esp), %ax + shlw $4, %ax + retl diff --git a/tests/x86/mul_007.irt b/tests/x86/mul_007.irt new file mode 100644 index 0000000..74ed418 --- /dev/null +++ b/tests/x86/mul_007.irt @@ -0,0 +1,19 @@ +--TEST-- +007: mul function +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + l_1 = START(l_4); + int32_t x = PARAM(l_1, "x", 1); + int32_t y = PARAM(l_1, "y", 2); + int32_t ret = MUL(x, y); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + movl 8(%esp), %eax + imull 4(%esp), %eax + retl diff --git a/tests/x86/mul_ov_001.irt b/tests/x86/mul_ov_001.irt new file mode 100644 index 0000000..d83c303 --- /dev/null +++ b/tests/x86/mul_ov_001.irt @@ -0,0 +1,20 @@ +--TEST-- +001: mul_ov function +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + int32_t c = 2; + l_1 = START(l_2); + int32_t x = PARAM(l_1, "x", 1); + int32_t ret = MUL_OV(x, c); + bool ov = OVERFLOW(ret); + l_2 = RETURN(l_1, ov); +} +--EXPECT-- +test: + imull $2, 4(%esp), %eax + seto %al + retl diff --git a/tests/x86/mul_ov_002.irt b/tests/x86/mul_ov_002.irt new file mode 100644 index 0000000..7afdf1f --- /dev/null +++ b/tests/x86/mul_ov_002.irt @@ -0,0 +1,22 @@ +--TEST-- +002: mul_ov function +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + uint32_t c = 2; + l_1 = START(l_2); + uint32_t x = PARAM(l_1, "x", 1); + uint32_t ret = MUL_OV(x, c); + bool ov = OVERFLOW(ret); + l_2 = RETURN(l_1, ov); +} +--EXPECT-- +test: + movl 4(%esp), %eax + movl $2, %edx + mull %edx + setb %al + retl diff --git a/tests/x86/ne_001.irt b/tests/x86/ne_001.irt new file mode 100644 index 0000000..387fab7 --- /dev/null +++ b/tests/x86/ne_001.irt @@ -0,0 +1,20 @@ +--TEST-- +001: ne function +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + l_1 = START(l_4); + int32_t x = PARAM(l_1, "x", 1); + int32_t y = PARAM(l_1, "y", 2); + bool ret = NE(x, y); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + movl 8(%esp), %eax + cmpl 4(%esp), %eax + setne %al + retl diff --git a/tests/x86/ne_002.irt b/tests/x86/ne_002.irt new file mode 100644 index 0000000..05a560a --- /dev/null +++ b/tests/x86/ne_002.irt @@ -0,0 +1,19 @@ +--TEST-- +002: ne function +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + int32_t c = 17; + l_1 = START(l_4); + int32_t x = PARAM(l_1, "x", 1); + bool ret = NE(x, c); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + cmpl $0x11, 4(%esp) + setne %al + retl diff --git a/tests/x86/ne_003.irt b/tests/x86/ne_003.irt new file mode 100644 index 0000000..f752328 --- /dev/null +++ b/tests/x86/ne_003.irt @@ -0,0 +1,19 @@ +--TEST-- +003: ne function +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + int32_t c = 0; + l_1 = START(l_4); + int32_t x = PARAM(l_1, "x", 1); + bool ret = NE(x, c); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + cmpl $0, 4(%esp) + setne %al + retl diff --git a/tests/x86/ne_004.irt b/tests/x86/ne_004.irt new file mode 100644 index 0000000..08d81c5 --- /dev/null +++ b/tests/x86/ne_004.irt @@ -0,0 +1,26 @@ +--TEST-- +004: ne function +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + double c = 0; + l_1 = START(l_4); + double x = PARAM(l_1, "x", 1); + bool ret = NE(x, c); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + movsd 4(%esp), %xmm0 + ucomisd .L1, %xmm0 + setp %al + movl $1, %ecx + cmovnel %ecx, %eax + retl +.rodata + .db 0x90, 0x90, 0x90, 0x90, 0x90, 0x90 +.L1: + .db 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 diff --git a/tests/x86/ne_005.irt b/tests/x86/ne_005.irt new file mode 100644 index 0000000..420dd2b --- /dev/null +++ b/tests/x86/ne_005.irt @@ -0,0 +1,26 @@ +--TEST-- +005: ne function +--TARGET-- +x86 +--ARGS-- +-S -mavx +--CODE-- +{ + double c = 0; + l_1 = START(l_4); + double x = PARAM(l_1, "x", 1); + bool ret = NE(x, c); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + vmovsd 4(%esp), %xmm0 + vucomisd .L1, %xmm0 + setp %al + movl $1, %ecx + cmovnel %ecx, %eax + retl +.rodata + .db 0x90, 0x90, 0x90, 0x90, 0x90, 0x90 +.L1: + .db 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 diff --git a/tests/x86/neg_001.irt b/tests/x86/neg_001.irt new file mode 100644 index 0000000..0967dd6 --- /dev/null +++ b/tests/x86/neg_001.irt @@ -0,0 +1,18 @@ +--TEST-- +001: neg function +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + l_1 = START(l_4); + int32_t x = PARAM(l_1, "x", 1); + int32_t ret = NEG(x); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + movl 4(%esp), %eax + negl %eax + retl diff --git a/tests/x86/neg_002.irt b/tests/x86/neg_002.irt new file mode 100644 index 0000000..2e2e990 --- /dev/null +++ b/tests/x86/neg_002.irt @@ -0,0 +1,26 @@ +--TEST-- +002: neg function +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + l_1 = START(l_4); + double x = PARAM(l_1, "x", 1); + double ret = NEG(x); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + subl $8, %esp + movsd 0xc(%esp), %xmm0 + xorpd .L1, %xmm0 + movsd %xmm0, (%esp) + fldl (%esp) + addl $8, %esp + retl +.rodata + .db 0x90, 0x90, 0x90 +.L1: + .db 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 diff --git a/tests/x86/neg_003.irt b/tests/x86/neg_003.irt new file mode 100644 index 0000000..2213ca1 --- /dev/null +++ b/tests/x86/neg_003.irt @@ -0,0 +1,26 @@ +--TEST-- +003: neg function +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + l_1 = START(l_4); + float x = PARAM(l_1, "x", 1); + float ret = NEG(x); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + subl $4, %esp + movss 8(%esp), %xmm0 + xorps .L1, %xmm0 + movss %xmm0, (%esp) + flds (%esp) + addl $4, %esp + retl +.rodata + .db 0x90, 0x90, 0x90, 0x90 +.L1: + .db 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 diff --git a/tests/x86/not_001.irt b/tests/x86/not_001.irt new file mode 100644 index 0000000..3cb3d0e --- /dev/null +++ b/tests/x86/not_001.irt @@ -0,0 +1,18 @@ +--TEST-- +001: not function +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + l_1 = START(l_4); + int32_t x = PARAM(l_1, "x", 1); + int32_t ret = NOT(x); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + movl 4(%esp), %eax + notl %eax + retl diff --git a/tests/x86/not_002.irt b/tests/x86/not_002.irt new file mode 100644 index 0000000..6abe265 --- /dev/null +++ b/tests/x86/not_002.irt @@ -0,0 +1,19 @@ +--TEST-- +002: not function +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + l_1 = START(l_4); + bool x = PARAM(l_1, "x", 1); + bool ret = NOT(x); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + movb 4(%esp), %al + testb %al, %al + sete %al + retl diff --git a/tests/x86/ra_001.irt b/tests/x86/ra_001.irt new file mode 100644 index 0000000..d251791 --- /dev/null +++ b/tests/x86/ra_001.irt @@ -0,0 +1,22 @@ +--TEST-- +001: Register Allocation (MUL + MUL) +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + l_1 = START(l_4); + uint32_t x_1 = PARAM(l_1, "x", 1); + uint32_t y_1 = PARAM(l_1, "y", 2); + uint32_t z_1 = PARAM(l_1, "z", 3); + uint32_t x_2 = MUL(x_1, y_1); + uint32_t x_3 = MUL(x_2, z_1); + l_4 = RETURN(l_1, x_3); +} +--EXPECT-- +test: + movl 8(%esp), %eax + mull 4(%esp) + mull 0xc(%esp) + retl diff --git a/tests/x86/ra_002.irt b/tests/x86/ra_002.irt new file mode 100644 index 0000000..3ea4150 --- /dev/null +++ b/tests/x86/ra_002.irt @@ -0,0 +1,23 @@ +--TEST-- +002: Register Allocation (MUL + DIV) +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + l_1 = START(l_4); + uint32_t x_1 = PARAM(l_1, "x", 1); + uint32_t y_1 = PARAM(l_1, "y", 2); + uint32_t z_1 = PARAM(l_1, "z", 3); + uint32_t x_2 = MUL(x_1, y_1); + uint32_t x_3 = DIV(x_2, z_1); + l_4 = RETURN(l_1, x_3); +} +--EXPECT-- +test: + movl 8(%esp), %eax + mull 4(%esp) + xorl %edx, %edx + divl 0xc(%esp) + retl diff --git a/tests/x86/ra_003.irt b/tests/x86/ra_003.irt new file mode 100644 index 0000000..01bf42f --- /dev/null +++ b/tests/x86/ra_003.irt @@ -0,0 +1,24 @@ +--TEST-- +003: Register Allocation (MUL + MOD) +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + l_1 = START(l_4); + uint32_t x_1 = PARAM(l_1, "x", 1); + uint32_t y_1 = PARAM(l_1, "y", 2); + uint32_t z_1 = PARAM(l_1, "z", 3); + uint32_t x_2 = MUL(x_1, y_1); + uint32_t x_3 = MOD(x_2, z_1); + l_4 = RETURN(l_1, x_3); +} +--EXPECT-- +test: + movl 8(%esp), %eax + mull 4(%esp) + xorl %edx, %edx + divl 0xc(%esp) + movl %edx, %eax + retl diff --git a/tests/x86/ra_004.irt b/tests/x86/ra_004.irt new file mode 100644 index 0000000..aa88450 --- /dev/null +++ b/tests/x86/ra_004.irt @@ -0,0 +1,23 @@ +--TEST-- +004: Register Allocation (DIV + MUL) +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + l_1 = START(l_4); + uint32_t x_1 = PARAM(l_1, "x", 1); + uint32_t y_1 = PARAM(l_1, "y", 2); + uint32_t z_1 = PARAM(l_1, "z", 3); + uint32_t x_2 = DIV(x_1, y_1); + uint32_t x_3 = MUL(x_2, z_1); + l_4 = RETURN(l_1, x_3); +} +--EXPECT-- +test: + movl 4(%esp), %eax + xorl %edx, %edx + divl 8(%esp) + mull 0xc(%esp) + retl diff --git a/tests/x86/ra_005.irt b/tests/x86/ra_005.irt new file mode 100644 index 0000000..e53ac2a --- /dev/null +++ b/tests/x86/ra_005.irt @@ -0,0 +1,24 @@ +--TEST-- +005: Register Allocation (DIV + DIV) +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + l_1 = START(l_4); + uint32_t x_1 = PARAM(l_1, "x", 1); + uint32_t y_1 = PARAM(l_1, "y", 2); + uint32_t z_1 = PARAM(l_1, "z", 3); + uint32_t x_2 = DIV(x_1, y_1); + uint32_t x_3 = DIV(x_2, z_1); + l_4 = RETURN(l_1, x_3); +} +--EXPECT-- +test: + movl 4(%esp), %eax + xorl %edx, %edx + divl 8(%esp) + xorl %edx, %edx + divl 0xc(%esp) + retl diff --git a/tests/x86/ra_006.irt b/tests/x86/ra_006.irt new file mode 100644 index 0000000..031ebfa --- /dev/null +++ b/tests/x86/ra_006.irt @@ -0,0 +1,25 @@ +--TEST-- +006: Register Allocation (DIV + MOD) +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + l_1 = START(l_4); + uint32_t x_1 = PARAM(l_1, "x", 1); + uint32_t y_1 = PARAM(l_1, "y", 2); + uint32_t z_1 = PARAM(l_1, "z", 3); + uint32_t x_2 = DIV(x_1, y_1); + uint32_t x_3 = MOD(x_2, z_1); + l_4 = RETURN(l_1, x_3); +} +--EXPECT-- +test: + movl 4(%esp), %eax + xorl %edx, %edx + divl 8(%esp) + xorl %edx, %edx + divl 0xc(%esp) + movl %edx, %eax + retl diff --git a/tests/x86/ra_007.irt b/tests/x86/ra_007.irt new file mode 100644 index 0000000..0cd8b1e --- /dev/null +++ b/tests/x86/ra_007.irt @@ -0,0 +1,24 @@ +--TEST-- +007: Register Allocation (MOD + MUL) +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + l_1 = START(l_4); + uint32_t x_1 = PARAM(l_1, "x", 1); + uint32_t y_1 = PARAM(l_1, "y", 2); + uint32_t z_1 = PARAM(l_1, "z", 3); + uint32_t x_2 = MOD(x_1, y_1); + uint32_t x_3 = MUL(x_2, z_1); + l_4 = RETURN(l_1, x_3); +} +--EXPECT-- +test: + movl 4(%esp), %eax + xorl %edx, %edx + divl 8(%esp) + movl 0xc(%esp), %eax + mull %edx + retl diff --git a/tests/x86/ra_008.irt b/tests/x86/ra_008.irt new file mode 100644 index 0000000..3560786 --- /dev/null +++ b/tests/x86/ra_008.irt @@ -0,0 +1,25 @@ +--TEST-- +008: Register Allocation (MOD + DIV) +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + l_1 = START(l_4); + uint32_t x_1 = PARAM(l_1, "x", 1); + uint32_t y_1 = PARAM(l_1, "y", 2); + uint32_t z_1 = PARAM(l_1, "z", 3); + uint32_t x_2 = MOD(x_1, y_1); + uint32_t x_3 = DIV(x_2, z_1); + l_4 = RETURN(l_1, x_3); +} +--EXPECT-- +test: + movl 4(%esp), %eax + xorl %edx, %edx + divl 8(%esp) + movl %edx, %eax + xorl %edx, %edx + divl 0xc(%esp) + retl diff --git a/tests/x86/ra_009.irt b/tests/x86/ra_009.irt new file mode 100644 index 0000000..c1a4677 --- /dev/null +++ b/tests/x86/ra_009.irt @@ -0,0 +1,26 @@ +--TEST-- +009: Register Allocation (MOD + MOD) +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + l_1 = START(l_4); + uint32_t x_1 = PARAM(l_1, "x", 1); + uint32_t y_1 = PARAM(l_1, "y", 2); + uint32_t z_1 = PARAM(l_1, "z", 3); + uint32_t x_2 = MOD(x_1, y_1); + uint32_t x_3 = MOD(x_2, z_1); + l_4 = RETURN(l_1, x_3); +} +--EXPECT-- +test: + movl 4(%esp), %eax + xorl %edx, %edx + divl 8(%esp) + movl %edx, %eax + xorl %edx, %edx + divl 0xc(%esp) + movl %edx, %eax + retl diff --git a/tests/x86/ra_010.irt b/tests/x86/ra_010.irt new file mode 100644 index 0000000..9f40bb9 --- /dev/null +++ b/tests/x86/ra_010.irt @@ -0,0 +1,23 @@ +--TEST-- +010: Register Allocation (ADD + MUL) +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + l_1 = START(l_4); + uint32_t x_1 = PARAM(l_1, "x", 1); + uint32_t y_1 = PARAM(l_1, "y", 2); + uint32_t z_1 = PARAM(l_1, "z", 3); + uint32_t x_2 = ADD(x_1, y_1); + uint32_t x_3 = MUL(x_2, z_1); + l_4 = RETURN(l_1, x_3); +} +--EXPECT-- +test: + movl 4(%esp), %eax + movl 8(%esp), %ecx + leal (%ecx, %eax), %eax + mull 0xc(%esp) + retl diff --git a/tests/x86/ra_011.irt b/tests/x86/ra_011.irt new file mode 100644 index 0000000..6b2eaf3 --- /dev/null +++ b/tests/x86/ra_011.irt @@ -0,0 +1,24 @@ +--TEST-- +011: Register Allocation (ADD + DIV) +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + l_1 = START(l_4); + uint32_t x_1 = PARAM(l_1, "x", 1); + uint32_t y_1 = PARAM(l_1, "y", 2); + uint32_t z_1 = PARAM(l_1, "z", 3); + uint32_t x_2 = ADD(x_1, y_1); + uint32_t x_3 = DIV(x_2, z_1); + l_4 = RETURN(l_1, x_3); +} +--EXPECT-- +test: + movl 4(%esp), %eax + movl 8(%esp), %ecx + leal (%ecx, %eax), %eax + xorl %edx, %edx + divl 0xc(%esp) + retl diff --git a/tests/x86/ra_012.irt b/tests/x86/ra_012.irt new file mode 100644 index 0000000..36f1924 --- /dev/null +++ b/tests/x86/ra_012.irt @@ -0,0 +1,25 @@ +--TEST-- +012: Register Allocation (ADD + MOD) +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + l_1 = START(l_4); + uint32_t x_1 = PARAM(l_1, "x", 1); + uint32_t y_1 = PARAM(l_1, "y", 2); + uint32_t z_1 = PARAM(l_1, "z", 3); + uint32_t x_2 = ADD(x_1, y_1); + uint32_t x_3 = MOD(x_2, z_1); + l_4 = RETURN(l_1, x_3); +} +--EXPECT-- +test: + movl 4(%esp), %eax + movl 8(%esp), %ecx + leal (%ecx, %eax), %eax + xorl %edx, %edx + divl 0xc(%esp) + movl %edx, %eax + retl diff --git a/tests/x86/ra_013.irt b/tests/x86/ra_013.irt new file mode 100644 index 0000000..88b7877 --- /dev/null +++ b/tests/x86/ra_013.irt @@ -0,0 +1,32 @@ +--TEST-- +013: Register Allocation (MOD + MOD + MOD) +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + l_1 = START(l_4); + uint32_t x_1 = PARAM(l_1, "x", 1); + uint32_t y_1 = PARAM(l_1, "y", 2); + uint32_t z_1 = PARAM(l_1, "z", 3); + uint32_t v_1 = PARAM(l_1, "v", 4); + uint32_t x_2 = MOD(x_1, y_1); + uint32_t x_3 = MOD(x_2, z_1); + uint32_t x_4 = MOD(v_1, x_3); + l_4 = RETURN(l_1, x_4); +} +--EXPECT-- +test: + movl 4(%esp), %eax + xorl %edx, %edx + divl 8(%esp) + movl %edx, %eax + xorl %edx, %edx + divl 0xc(%esp) + movl %edx, %ecx + movl 0x10(%esp), %eax + xorl %edx, %edx + divl %ecx + movl %edx, %eax + retl diff --git a/tests/x86/ra_014.irt b/tests/x86/ra_014.irt new file mode 100644 index 0000000..eb99da8 --- /dev/null +++ b/tests/x86/ra_014.irt @@ -0,0 +1,25 @@ +--TEST-- +014: Register Allocation (SHL + SHL) +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + l_1 = START(l_4); + uint32_t x = PARAM(l_1, "x", 1); + uint32_t y = PARAM(l_1, "y", 2); + uint32_t ret = SHL(x, y); + uint32_t ret2 = SHL(x, ret); + l_4 = RETURN(l_1, ret2); +} +--EXPECT-- +test: + movl 4(%esp), %eax + movl 8(%esp), %ecx + movl %eax, %edx + shll %cl, %edx + movl %edx, %ecx + shll %cl, %eax + retl + diff --git a/tests/x86/ra_015.irt b/tests/x86/ra_015.irt new file mode 100644 index 0000000..f102c8c --- /dev/null +++ b/tests/x86/ra_015.irt @@ -0,0 +1,25 @@ +--TEST-- +015: Register Allocation (SHL + SHL + reuse/vreg hint) +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + l_1 = START(l_4); + uint32_t x = PARAM(l_1, "x", 1); + uint32_t y = PARAM(l_1, "y", 2); + uint32_t ret = SHL(x, y); + uint32_t ret2 = SHL(y, ret); + l_4 = RETURN(l_1, ret2); +} +--EXPECT-- +test: + movl 4(%esp), %ecx + movl 8(%esp), %eax + movl %ecx, %edx + movl %eax, %ecx + shll %cl, %edx + movl %edx, %ecx + shll %cl, %eax + retl diff --git a/tests/x86/setcc_001.irt b/tests/x86/setcc_001.irt new file mode 100644 index 0000000..5944a8a --- /dev/null +++ b/tests/x86/setcc_001.irt @@ -0,0 +1,22 @@ +--TEST-- +001: EQ(ADD(_,_), 0) -> SETCC +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + int32_t c1 = 0; + int32_t c2 = 1; + l_1 = START(l_2); + int32_t x = PARAM(l_1, "x", 1); + int32_t d_1 = ADD(x, c2); + bool d_2 = EQ(d_1, c1); + l_2 = RETURN(l_1, d_2); +} +--EXPECT-- +test: + movl 4(%esp), %eax + addl $1, %eax + sete %al + retl diff --git a/tests/x86/shl_001.irt b/tests/x86/shl_001.irt new file mode 100644 index 0000000..25a6c92 --- /dev/null +++ b/tests/x86/shl_001.irt @@ -0,0 +1,20 @@ +--TEST-- +001: shl function +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + l_1 = START(l_4); + int32_t x = PARAM(l_1, "x", 1); + int32_t y = PARAM(l_1, "y", 2); + int32_t ret = SHL(x, y); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + movl 4(%esp), %eax + movl 8(%esp), %ecx + shll %cl, %eax + retl diff --git a/tests/x86/shl_002.irt b/tests/x86/shl_002.irt new file mode 100644 index 0000000..2908b95 --- /dev/null +++ b/tests/x86/shl_002.irt @@ -0,0 +1,19 @@ +--TEST-- +002: shl function +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + int32_t c = 17; + l_1 = START(l_4); + int32_t x = PARAM(l_1, "x", 1); + int32_t ret = SHL(x, c); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + movl 4(%esp), %eax + shll $0x11, %eax + retl diff --git a/tests/x86/shl_003.irt b/tests/x86/shl_003.irt new file mode 100644 index 0000000..5031cf4 --- /dev/null +++ b/tests/x86/shl_003.irt @@ -0,0 +1,20 @@ +--TEST-- +003: shl function +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + l_1 = START(l_4); + int32_t x = PARAM(l_1, "x", 1); + int32_t y = PARAM(l_1, "y", 2); + int32_t ret = SHL(y, x); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + movl 4(%esp), %ecx + movl 8(%esp), %eax + shll %cl, %eax + retl diff --git a/tests/x86/shl_004.irt b/tests/x86/shl_004.irt new file mode 100644 index 0000000..62aebc8 --- /dev/null +++ b/tests/x86/shl_004.irt @@ -0,0 +1,20 @@ +--TEST-- +004: shl function +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + int32_t c = 17; + l_1 = START(l_4); + int32_t x = PARAM(l_1, "x", 1); + int32_t ret = SHL(c, x); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + movl 4(%esp), %ecx + movl $0x11, %eax + shll %cl, %eax + retl diff --git a/tests/x86/sub_001.irt b/tests/x86/sub_001.irt new file mode 100644 index 0000000..1267371 --- /dev/null +++ b/tests/x86/sub_001.irt @@ -0,0 +1,19 @@ +--TEST-- +001: sub function +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + l_1 = START(l_4); + int32_t x = PARAM(l_1, "x", 1); + int32_t y = PARAM(l_1, "y", 2); + int32_t ret = SUB(x, y); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + movl 4(%esp), %eax + subl 8(%esp), %eax + retl diff --git a/tests/x86/sub_002.irt b/tests/x86/sub_002.irt new file mode 100644 index 0000000..2dc08a5 --- /dev/null +++ b/tests/x86/sub_002.irt @@ -0,0 +1,19 @@ +--TEST-- +002: sub function +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + int32_t c = 17; + l_1 = START(l_4); + int32_t x = PARAM(l_1, "x", 1); + int32_t ret = SUB(x, c); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + movl 4(%esp), %eax + leal -0x11(%eax), %eax + retl diff --git a/tests/x86/sub_003.irt b/tests/x86/sub_003.irt new file mode 100644 index 0000000..b086209 --- /dev/null +++ b/tests/x86/sub_003.irt @@ -0,0 +1,19 @@ +--TEST-- +003: sub function +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + l_1 = START(l_4); + int32_t x = PARAM(l_1, "x", 1); + int32_t y = PARAM(l_1, "y", 2); + int32_t ret = SUB(y, x); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + movl 8(%esp), %eax + subl 4(%esp), %eax + retl diff --git a/tests/x86/sub_004.irt b/tests/x86/sub_004.irt new file mode 100644 index 0000000..5fd9435 --- /dev/null +++ b/tests/x86/sub_004.irt @@ -0,0 +1,19 @@ +--TEST-- +004: sub function +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + int32_t c = 17; + l_1 = START(l_4); + int32_t x = PARAM(l_1, "x", 1); + int32_t ret = SUB(c, x); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + movl $0x11, %eax + subl 4(%esp), %eax + retl diff --git a/tests/x86/sub_005.irt b/tests/x86/sub_005.irt new file mode 100644 index 0000000..4a0cc0c --- /dev/null +++ b/tests/x86/sub_005.irt @@ -0,0 +1,23 @@ +--TEST-- +005: sub function +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + l_1 = START(l_4); + double x = PARAM(l_1, "x", 1); + double y = PARAM(l_1, "y", 2); + double ret = SUB(x, y); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + subl $8, %esp + movsd 0xc(%esp), %xmm0 + subsd 0x14(%esp), %xmm0 + movsd %xmm0, (%esp) + fldl (%esp) + addl $8, %esp + retl diff --git a/tests/x86/sub_006.irt b/tests/x86/sub_006.irt new file mode 100644 index 0000000..fe5ce94 --- /dev/null +++ b/tests/x86/sub_006.irt @@ -0,0 +1,23 @@ +--TEST-- +006: sub function +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + l_1 = START(l_4); + double x = PARAM(l_1, "x", 1); + double y = PARAM(l_1, "y", 2); + double ret = SUB(y, x); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + subl $8, %esp + movsd 0x14(%esp), %xmm0 + subsd 0xc(%esp), %xmm0 + movsd %xmm0, (%esp) + fldl (%esp) + addl $8, %esp + retl diff --git a/tests/x86/sub_007.irt b/tests/x86/sub_007.irt new file mode 100644 index 0000000..b58cd5b --- /dev/null +++ b/tests/x86/sub_007.irt @@ -0,0 +1,23 @@ +--TEST-- +007: sub function +--TARGET-- +x86 +--ARGS-- +-S -mavx +--CODE-- +{ + l_1 = START(l_4); + double x = PARAM(l_1, "x", 1); + double y = PARAM(l_1, "y", 2); + double ret = SUB(x, y); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + subl $8, %esp + vmovsd 0xc(%esp), %xmm0 + vsubsd 0x14(%esp), %xmm0, %xmm0 + vmovsd %xmm0, (%esp) + fldl (%esp) + addl $8, %esp + retl diff --git a/tests/x86/sub_008.irt b/tests/x86/sub_008.irt new file mode 100644 index 0000000..4b63590 --- /dev/null +++ b/tests/x86/sub_008.irt @@ -0,0 +1,23 @@ +--TEST-- +008: sub function +--TARGET-- +x86 +--ARGS-- +-S -mavx +--CODE-- +{ + l_1 = START(l_4); + double x = PARAM(l_1, "x", 1); + double y = PARAM(l_1, "y", 2); + double ret = SUB(y, x); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + subl $8, %esp + vmovsd 0x14(%esp), %xmm0 + vsubsd 0xc(%esp), %xmm0, %xmm0 + vmovsd %xmm0, (%esp) + fldl (%esp) + addl $8, %esp + retl diff --git a/tests/x86/sub_009.irt b/tests/x86/sub_009.irt new file mode 100644 index 0000000..94aa998 --- /dev/null +++ b/tests/x86/sub_009.irt @@ -0,0 +1,19 @@ +--TEST-- +009: sub function +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + uint64_t c = 0x100000000; + l_1 = START(l_4); + uint64_t x = PARAM(l_1, "x", 1); + uint64_t ret = SUB(c, x); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + movabsq $0x100000000, %rax + subq %rdi, %rax + retq diff --git a/tests/x86/sub_010.irt b/tests/x86/sub_010.irt new file mode 100644 index 0000000..6cdd3bd --- /dev/null +++ b/tests/x86/sub_010.irt @@ -0,0 +1,19 @@ +--TEST-- +010: sub function +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + uint16_t c = 1; + l_1 = START(l_4); + uint16_t x = PARAM(l_1, "x", 1); + uint16_t ret = SUB(x, c); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + movw 4(%esp), %ax + decw %ax + retl diff --git a/tests/x86/sub_011.irt b/tests/x86/sub_011.irt new file mode 100644 index 0000000..53268f8 --- /dev/null +++ b/tests/x86/sub_011.irt @@ -0,0 +1,27 @@ +--TEST-- +011: sub function +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + double c = 0.5; + l_1 = START(l_4); + double x = PARAM(l_1, "x", 1); + double ret = SUB(c, x); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + subl $8, %esp + movsd .L1, %xmm0 + subsd 0xc(%esp), %xmm0 + movsd %xmm0, (%esp) + fldl (%esp) + addl $8, %esp + retl +.rodata + .db 0x90, 0x90, 0x90 +.L1: + .db 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x3f diff --git a/tests/x86/sub_012.irt b/tests/x86/sub_012.irt new file mode 100644 index 0000000..e95f014 --- /dev/null +++ b/tests/x86/sub_012.irt @@ -0,0 +1,27 @@ +--TEST-- +012: sub function +--TARGET-- +x86 +--ARGS-- +-S -mavx +--CODE-- +{ + double c = 0.5; + l_1 = START(l_4); + double x = PARAM(l_1, "x", 1); + double ret = SUB(c, x); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + subl $8, %esp + vmovsd .L1, %xmm0 + vsubsd 0xc(%esp), %xmm0, %xmm0 + vmovsd %xmm0, (%esp) + fldl (%esp) + addl $8, %esp + retl +.rodata + .db 0x90, 0x90 +.L1: + .db 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x3f diff --git a/tests/x86/test_001.irt b/tests/x86/test_001.irt new file mode 100644 index 0000000..bb5bade --- /dev/null +++ b/tests/x86/test_001.irt @@ -0,0 +1,21 @@ +--TEST-- +001: EQ(AND(_,_), 0) -> TEST +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + int32_t c1 = 0; + int32_t c2 = 3; + l_1 = START(l_2); + int32_t x = PARAM(l_1, "x", 1); + int32_t d_1 = AND(x, c2); + bool d_2 = EQ(d_1, c1); + l_2 = RETURN(l_1, d_2); +} +--EXPECT-- +test: + testl $3, 4(%esp) + sete %al + retl diff --git a/tests/x86/uge_001.irt b/tests/x86/uge_001.irt new file mode 100644 index 0000000..cab688f --- /dev/null +++ b/tests/x86/uge_001.irt @@ -0,0 +1,20 @@ +--TEST-- +001: uge function +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + l_1 = START(l_4); + uint32_t x = PARAM(l_1, "x", 1); + uint32_t y = PARAM(l_1, "y", 2); + bool ret = UGE(x, y); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + movl 8(%esp), %eax + cmpl 4(%esp), %eax + setbe %al + retl diff --git a/tests/x86/uge_002.irt b/tests/x86/uge_002.irt new file mode 100644 index 0000000..6e583d7 --- /dev/null +++ b/tests/x86/uge_002.irt @@ -0,0 +1,19 @@ +--TEST-- +002: uge function +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + uint32_t c = 17; + l_1 = START(l_4); + uint32_t x = PARAM(l_1, "x", 1); + bool ret = UGE(x, c); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + cmpl $0x11, 4(%esp) + setae %al + retl diff --git a/tests/x86/uge_003.irt b/tests/x86/uge_003.irt new file mode 100644 index 0000000..f9d06b7 --- /dev/null +++ b/tests/x86/uge_003.irt @@ -0,0 +1,18 @@ +--TEST-- +003: uge function +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + uint32_t c = 0; + l_1 = START(l_4); + uint32_t x = PARAM(l_1, "x", 1); + bool ret = UGE(x, c); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + movb $1, %al + retl diff --git a/tests/x86/ugt_001.irt b/tests/x86/ugt_001.irt new file mode 100644 index 0000000..c6d512e --- /dev/null +++ b/tests/x86/ugt_001.irt @@ -0,0 +1,20 @@ +--TEST-- +001: ugt function +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + l_1 = START(l_4); + uint32_t x = PARAM(l_1, "x", 1); + uint32_t y = PARAM(l_1, "y", 2); + bool ret = UGT(x, y); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + movl 8(%esp), %eax + cmpl 4(%esp), %eax + setb %al + retl diff --git a/tests/x86/ugt_002.irt b/tests/x86/ugt_002.irt new file mode 100644 index 0000000..a9e8b46 --- /dev/null +++ b/tests/x86/ugt_002.irt @@ -0,0 +1,19 @@ +--TEST-- +002: ugt function +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + uint32_t c = 17; + l_1 = START(l_4); + uint32_t x = PARAM(l_1, "x", 1); + bool ret = UGT(x, c); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + cmpl $0x11, 4(%esp) + seta %al + retl diff --git a/tests/x86/ugt_003.irt b/tests/x86/ugt_003.irt new file mode 100644 index 0000000..1089860 --- /dev/null +++ b/tests/x86/ugt_003.irt @@ -0,0 +1,19 @@ +--TEST-- +003: ugt function +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + uint32_t c = 0; + l_1 = START(l_4); + uint32_t x = PARAM(l_1, "x", 1); + bool ret = UGT(x, c); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + cmpl $0, 4(%esp) + setne %al + retl diff --git a/tests/x86/ule_001.irt b/tests/x86/ule_001.irt new file mode 100644 index 0000000..732eb5c --- /dev/null +++ b/tests/x86/ule_001.irt @@ -0,0 +1,20 @@ +--TEST-- +001: ule function +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + l_1 = START(l_4); + uint32_t x = PARAM(l_1, "x", 1); + uint32_t y = PARAM(l_1, "y", 2); + bool ret = ULE(x, y); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + movl 8(%esp), %eax + cmpl 4(%esp), %eax + setae %al + retl diff --git a/tests/x86/ule_002.irt b/tests/x86/ule_002.irt new file mode 100644 index 0000000..dbf3f68 --- /dev/null +++ b/tests/x86/ule_002.irt @@ -0,0 +1,19 @@ +--TEST-- +002: ule function +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + uint32_t c = 17; + l_1 = START(l_4); + uint32_t x = PARAM(l_1, "x", 2); + bool ret = ULE(x, c); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + cmpl $0x11, 4(%esp) + setbe %al + retl diff --git a/tests/x86/ule_003.irt b/tests/x86/ule_003.irt new file mode 100644 index 0000000..20715aa --- /dev/null +++ b/tests/x86/ule_003.irt @@ -0,0 +1,19 @@ +--TEST-- +003: ule function +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + uint32_t c = 0; + l_1 = START(l_4); + uint32_t x = PARAM(l_1, "x", 2); + bool ret = ULE(x, c); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + cmpl $0, 4(%esp) + sete %al + retl diff --git a/tests/x86/ult_001.irt b/tests/x86/ult_001.irt new file mode 100644 index 0000000..3c42ac8 --- /dev/null +++ b/tests/x86/ult_001.irt @@ -0,0 +1,20 @@ +--TEST-- +001: ult function +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + l_1 = START(l_4); + uint32_t x = PARAM(l_1, "x", 1); + uint32_t y = PARAM(l_1, "y", 2); + bool ret = ULT(x, y); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + movl 8(%esp), %eax + cmpl 4(%esp), %eax + seta %al + retl diff --git a/tests/x86/ult_002.irt b/tests/x86/ult_002.irt new file mode 100644 index 0000000..36866cc --- /dev/null +++ b/tests/x86/ult_002.irt @@ -0,0 +1,19 @@ +--TEST-- +002: ult function +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + uint32_t c = 17; + l_1 = START(l_4); + uint32_t x = PARAM(l_1, "x", 1); + bool ret = ULT(x, c); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + cmpl $0x11, 4(%esp) + setb %al + retl diff --git a/tests/x86/ult_003.irt b/tests/x86/ult_003.irt new file mode 100644 index 0000000..63c7556 --- /dev/null +++ b/tests/x86/ult_003.irt @@ -0,0 +1,18 @@ +--TEST-- +003: ult function +--TARGET-- +x86 +--ARGS-- +-S +--CODE-- +{ + uint32_t c = 0; + l_1 = START(l_4); + uint32_t x = PARAM(l_1, "x", 1); + bool ret = ULT(x, c); + l_4 = RETURN(l_1, ret); +} +--EXPECT-- +test: + xorl %eax, %eax + retl