mirror of
https://github.com/danog/ir.git
synced 2025-01-22 05:31:32 +01:00
Revisit and optimize GCM implementation
Use two different queues to schedule early and late
This commit is contained in:
Dmitry Stogov
parent
6fdce28d65
commit
406b08030d
204
ir_gcm.c
204
ir_gcm.c
@ -13,8 +13,9 @@
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static void ir_gcm_schedule_early(ir_ctx *ctx, uint32_t *_blocks, ir_ref ref)
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{
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ir_ref j, n, *p;
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ir_ref n, *p, input;
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ir_insn *insn;
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uint32_t dom_depth, b;
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insn = &ctx->ir_base[ref];
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@ -22,16 +23,19 @@ static void ir_gcm_schedule_early(ir_ctx *ctx, uint32_t *_blocks, ir_ref ref)
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IR_ASSERT(insn->op != IR_PHI && insn->op != IR_PI);
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_blocks[ref] = 1;
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dom_depth = 0;
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n = ir_input_edges_count(ctx, insn);
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for (j = 1, p = insn->ops + 1; j <= n; j++, p++) {
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ir_ref input = *p;
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for (p = insn->ops + 1; n > 0; p++, n--) {
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input = *p;
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if (input > 0) {
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if (_blocks[input] == 0) {
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ir_gcm_schedule_early(ctx, _blocks, input);
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}
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if (ctx->cfg_blocks[_blocks[ref]].dom_depth < ctx->cfg_blocks[_blocks[input]].dom_depth) {
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_blocks[ref] = _blocks[input];
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b = _blocks[input];
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if (dom_depth < ctx->cfg_blocks[b].dom_depth) {
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dom_depth = ctx->cfg_blocks[b].dom_depth;
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_blocks[ref] = b;
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}
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}
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}
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@ -40,10 +44,14 @@ static void ir_gcm_schedule_early(ir_ctx *ctx, uint32_t *_blocks, ir_ref ref)
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/* Last Common Ancestor */
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static uint32_t ir_gcm_find_lca(ir_ctx *ctx, uint32_t b1, uint32_t b2)
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{
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while (ctx->cfg_blocks[b1].dom_depth > ctx->cfg_blocks[b2].dom_depth) {
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uint32_t dom_depth;
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dom_depth = ctx->cfg_blocks[b2].dom_depth;
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while (ctx->cfg_blocks[b1].dom_depth > dom_depth) {
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b1 = ctx->cfg_blocks[b1].dom_parent;
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}
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while (ctx->cfg_blocks[b2].dom_depth > ctx->cfg_blocks[b1].dom_depth) {
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dom_depth = ctx->cfg_blocks[b1].dom_depth;
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while (ctx->cfg_blocks[b2].dom_depth > dom_depth) {
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b2 = ctx->cfg_blocks[b2].dom_parent;
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}
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while (b1 != b2) {
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@ -55,7 +63,7 @@ static uint32_t ir_gcm_find_lca(ir_ctx *ctx, uint32_t b1, uint32_t b2)
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static void ir_gcm_schedule_late(ir_ctx *ctx, uint32_t *_blocks, ir_bitset visited, ir_ref ref)
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{
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ir_ref i, n, *p, use;
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ir_ref n, *p, use;
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ir_insn *insn;
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ir_bitset_incl(visited, ref);
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@ -68,44 +76,43 @@ static void ir_gcm_schedule_late(ir_ctx *ctx, uint32_t *_blocks, ir_bitset visit
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IR_ASSERT(insn->op != IR_PHI && insn->op != IR_PI);
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lca = 0;
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for (i = 0, p = &ctx->use_edges[ctx->use_lists[ref].refs]; i < n; i++, p++) {
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for (p = &ctx->use_edges[ctx->use_lists[ref].refs]; n > 0; p++, n--) {
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use = *p;
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if (!ir_bitset_in(visited, use) && _blocks[use]) {
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ir_gcm_schedule_late(ctx, _blocks, visited, use);
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}
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b = _blocks[use];
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if (!b) {
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continue;
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} else if (!ir_bitset_in(visited, use)) {
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ir_gcm_schedule_late(ctx, _blocks, visited, use);
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b = _blocks[use];
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IR_ASSERT(b != 0);
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}
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insn = &ctx->ir_base[use];
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if (insn->op == IR_PHI) {
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if (insn->op2 == ref) {
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b = _blocks[ctx->ir_base[insn->op1].op1];
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} else if (insn->op3 == ref) {
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b = _blocks[ctx->ir_base[insn->op1].op2];
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} else {
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ir_ref j, n, *p;
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ir_ref *p = insn->ops + 2; /* PHI data inputs */
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ir_ref *q = ctx->ir_base[insn->op1].ops + 1; /* MERGE inputs */
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b = 0;
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n = ir_input_edges_count(ctx, insn);
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for (j = 3, p = insn->ops + 4; j < n; j++, p++) {
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if (*p == ref) {
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b = _blocks[ir_insn_op(&ctx->ir_base[insn->op1], j)];
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break;
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}
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}
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IR_ASSERT(b != 0);
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while (*p != ref) {
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p++;
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q++;
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}
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b = _blocks[*q];
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}
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lca = !lca ? b : ir_gcm_find_lca(ctx, lca, b);
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}
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IR_ASSERT(lca != 0 && "No Common Antecessor");
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b = lca;
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while (ctx->cfg_blocks[b].loop_depth && lca != ctx->cfg_blocks[_blocks[ref]].dom_parent) {
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if (ctx->cfg_blocks[lca].loop_depth < ctx->cfg_blocks[b].loop_depth) {
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b = lca;
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uint32_t loop_depth = ctx->cfg_blocks[b].loop_depth;
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if (loop_depth) {
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while (lca != ctx->cfg_blocks[_blocks[ref]].dom_parent) {
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if (ctx->cfg_blocks[lca].loop_depth < loop_depth) {
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loop_depth = ctx->cfg_blocks[lca].loop_depth;
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b = lca;
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if (!loop_depth) {
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break;
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}
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}
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lca = ctx->cfg_blocks[lca].dom_parent;
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}
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lca = ctx->cfg_blocks[lca].dom_parent;
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}
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_blocks[ref] = b;
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}
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@ -113,10 +120,11 @@ static void ir_gcm_schedule_late(ir_ctx *ctx, uint32_t *_blocks, ir_bitset visit
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int ir_gcm(ir_ctx *ctx)
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{
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ir_ref i, j, k, n, *p, ref;
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ir_ref k, n, *p, ref;
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ir_bitset visited;
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ir_block *bb;
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ir_list queue;
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ir_list queue_early;
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ir_list queue_late;
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uint32_t *_blocks, b;
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ir_insn *insn, *use_insn;
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ir_use_list *use_list;
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@ -124,71 +132,71 @@ int ir_gcm(ir_ctx *ctx)
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IR_ASSERT(ctx->cfg_map);
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_blocks = ctx->cfg_map;
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ir_list_init(&queue, ctx->insns_count);
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ir_list_init(&queue_early, ctx->insns_count);
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ir_list_init(&queue_late, ctx->insns_count);
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visited = ir_bitset_malloc(ctx->insns_count);
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/* pin and collect control and control depended (PARAM, VAR, PHI, PI) instructions */
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for (b = 1, bb = ctx->cfg_blocks + 1; b <= ctx->cfg_blocks_count; b++, bb++) {
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b = ctx->cfg_blocks_count;
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for (bb = ctx->cfg_blocks + b; b > 0; bb--, b--) {
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if (bb->flags & IR_BB_UNREACHABLE) {
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continue;
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}
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j = bb->end;
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while (1) {
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insn = &ctx->ir_base[j];
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ir_bitset_incl(visited, j);
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_blocks[j] = b; /* pin to block */
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ref = bb->end;
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do {
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insn = &ctx->ir_base[ref];
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ir_bitset_incl(visited, ref);
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_blocks[ref] = b; /* pin to block */
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flags = ir_op_flags[insn->op];
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#if 1
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n = IR_INPUT_EDGES_COUNT(flags);
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if (!IR_IS_FIXED_INPUTS_COUNT(n) || n > 1) {
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ir_list_push(&queue_early, ref);
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}
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#else
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if (IR_OPND_KIND(flags, 2) == IR_OPND_DATA
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|| IR_OPND_KIND(flags, 3) == IR_OPND_DATA
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|| ((flags & IR_OP_FLAG_MEM) && insn->type != IR_VOID)) {
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ir_list_push(&queue, j);
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|| IR_OPND_KIND(flags, 3) == IR_OPND_DATA) {
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ir_list_push(&queue_early, ref);
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}
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if (j == bb->start) {
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use_list = &ctx->use_lists[j];
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n = use_list->count;
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for (p = &ctx->use_edges[use_list->refs]; n > 0; n--, p++) {
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ref = *p;
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use_insn = &ctx->ir_base[ref];
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if (use_insn->op == IR_PARAM || use_insn->op == IR_VAR) {
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_blocks[ref] = b; /* pin to block */
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ir_bitset_incl(visited, ref);
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} else
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if (use_insn->op == IR_PHI || use_insn->op == IR_PI) {
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ir_bitset_incl(visited, ref);
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if (UNEXPECTED(ctx->use_lists[ref].count == 0)) {
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// TODO: Unused PHI ???
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} else {
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_blocks[ref] = b; /* pin to block */
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ir_list_push(&queue, ref);
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}
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}
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#endif
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if (insn->type != IR_VOID) {
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IR_ASSERT(flags & IR_OP_FLAG_MEM);
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ir_list_push(&queue_late, ref);
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}
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ref = insn->op1; /* control predecessor */
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} while (ref != bb->start);
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ir_bitset_incl(visited, ref);
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_blocks[ref] = b; /* pin to block */
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use_list = &ctx->use_lists[ref];
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n = use_list->count;
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for (p = &ctx->use_edges[use_list->refs]; n > 0; n--, p++) {
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ref = *p;
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use_insn = &ctx->ir_base[ref];
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if (use_insn->op == IR_PARAM || use_insn->op == IR_VAR) {
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_blocks[ref] = b; /* pin to block */
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ir_bitset_incl(visited, ref);
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} else if (use_insn->op == IR_PHI || use_insn->op == IR_PI) {
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ir_bitset_incl(visited, ref);
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if (EXPECTED(ctx->use_lists[ref].count != 0)) {
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_blocks[ref] = b; /* pin to block */
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ir_list_push(&queue_early, ref);
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ir_list_push(&queue_late, ref);
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}
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break;
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}
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j = insn->op1; /* control predecessor */
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}
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}
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n = ir_list_len(&queue);
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for (i = 0; i < n; i++) {
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ref = ir_list_at(&queue, i);
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n = ir_list_len(&queue_early);
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while (n > 0) {
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n--;
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ref = ir_list_at(&queue_early, n);
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insn = &ctx->ir_base[ref];
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flags = ir_op_flags[insn->op];
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if (IR_OPND_KIND(flags, 2) == IR_OPND_DATA) {
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if (insn->op2 > 0 && _blocks[insn->op2] == 0) {
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ir_gcm_schedule_early(ctx, _blocks, insn->op2);
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}
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}
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if (IR_OPND_KIND(flags, 3) == IR_OPND_DATA) {
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if (insn->op3 > 0 && _blocks[insn->op3] == 0) {
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ir_gcm_schedule_early(ctx, _blocks, insn->op3);
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}
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ir_ref n = ir_input_edges_count(ctx, insn);
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for (k = 4, p = insn->ops + 4; k <= n; k++, p++) {
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ref = *p;
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if (ref > 0 && _blocks[ref] == 0) {
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ir_gcm_schedule_early(ctx, _blocks, ref);
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}
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k = ir_input_edges_count(ctx, insn) - 1;
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for (p = insn->ops + 2; k > 0; p++, k--) {
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ref = *p;
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if (ref > 0 && _blocks[ref] == 0) {
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ir_gcm_schedule_early(ctx, _blocks, ref);
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}
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}
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}
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@ -196,35 +204,35 @@ int ir_gcm(ir_ctx *ctx)
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#ifdef IR_DEBUG
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if (ctx->flags & IR_DEBUG_GCM) {
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fprintf(stderr, "GCM Schedule Early\n");
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for (i = 1; i < ctx->insns_count; i++) {
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fprintf(stderr, "%d -> %d\n", i, _blocks[i]);
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for (n = 1; n < ctx->insns_count; n++) {
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fprintf(stderr, "%d -> %d\n", n, _blocks[n]);
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}
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}
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#endif
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n = ir_list_len(&queue);
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for (i = 0; i < n; i++) {
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ref = ir_list_at(&queue, i);
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n = ir_list_len(&queue_late);
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while (n > 0) {
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n--;
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ref = ir_list_at(&queue_late, n);
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use_list = &ctx->use_lists[ref];
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ir_ref n = use_list->count;
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if (n > 0) {
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for (p = &ctx->use_edges[use_list->refs]; n > 0; n--, p++) {
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ref = *p;
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if (!ir_bitset_in(visited, ref) && _blocks[ref]) {
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ir_gcm_schedule_late(ctx, _blocks, visited, ref);
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}
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k = use_list->count;
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for (p = &ctx->use_edges[use_list->refs]; k > 0; p++, k--) {
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ref = *p;
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if (!ir_bitset_in(visited, ref) && _blocks[ref]) {
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ir_gcm_schedule_late(ctx, _blocks, visited, ref);
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}
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}
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}
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ir_mem_free(visited);
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ir_list_free(&queue);
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ir_list_free(&queue_early);
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ir_list_free(&queue_late);
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#ifdef IR_DEBUG
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if (ctx->flags & IR_DEBUG_GCM) {
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fprintf(stderr, "GCM Schedule Late\n");
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for (i = 1; i < ctx->insns_count; i++) {
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fprintf(stderr, "%d -> %d\n", i, _blocks[i]);
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for (n = 1; n < ctx->insns_count; n++) {
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fprintf(stderr, "%d -> %d\n", n, _blocks[n]);
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}
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}
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#endif
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