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Allow genearion of TEST MEM, IMM
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parent
9b558e544f
commit
5034f8dedb
14
ir_x86.dasc
14
ir_x86.dasc
@ -1284,6 +1284,12 @@ static uint32_t ir_match_insn(ir_ctx *ctx, ir_ref ref, ir_block *bb)
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ir_match_swap_commutative(ctx, op1_insn);
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ir_match_fuse_load(ctx, op1_insn->op2, bb);
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if (op1_insn->op == IR_AND && ctx->use_lists[insn->op1].count == 1) {
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if (IR_IS_CONST_REF(op1_insn->op2)
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&& op1_insn->op1 > bb->start
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&& op1_insn->op1 < ref
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&& !ctx->rules[op1_insn->op1]) {
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ir_match_fuse_load(ctx, op1_insn->op1, bb);
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}
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ctx->rules[insn->op1] = IR_SKIP_TEST_INT;
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return IR_TEST_INT;
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} else {
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@ -1855,6 +1861,12 @@ store_int:
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} else if (op2_insn->op == IR_AND) { // TODO: OR, XOR. etc
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ir_match_swap_commutative(ctx, op2_insn);
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ir_match_fuse_load(ctx, op2_insn->op2, bb);
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if (IR_IS_CONST_REF(op2_insn->op2)
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&& op2_insn->op1 > bb->start
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&& op2_insn->op1 < ref
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&& !ctx->rules[op2_insn->op1]) {
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ir_match_fuse_load(ctx, op2_insn->op1, bb);
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}
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ctx->rules[insn->op2] = IR_SKIP_TEST_INT;
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return IR_TEST_AND_BRANCH_INT;
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} else if (op2_insn->op == IR_OVERFLOW) {
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@ -3858,7 +3870,7 @@ static void ir_emit_test_int_common(ir_ctx *ctx, ir_ref ref, ir_op op)
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op1_reg &= ~IR_REG_SPILL_LOAD;
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ir_emit_load(ctx, type, op1_reg, op1);
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}
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if (op2_reg != IR_REG_NONE) {
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if (op2_reg != IR_REG_NONE && ctx->rules[op2] != IR_SKIP_MEM) {
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if ((op2_reg & IR_REG_SPILL_LOAD) || IR_IS_CONST_REF(op2)) {
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op2_reg &= ~IR_REG_SPILL_LOAD;
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if (op1 != op2) {
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