From 5103c18269f1d0af68943851fa1c7c0526a42c4f Mon Sep 17 00:00:00 2001
From: Dmitry Stogov <dmitry@zend.com>
Date: Thu, 19 Jan 2023 13:39:29 +0300
Subject: [PATCH] Fix load fusion in combination with depended register spill
 load

---
 ir_ra.c     | 1 +
 ir_x86.dasc | 4 ++--
 2 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/ir_ra.c b/ir_ra.c
index 4820c41..24fd264 100644
--- a/ir_ra.c
+++ b/ir_ra.c
@@ -564,6 +564,7 @@ int ir_compute_live_ranges(ir_ctx *ctx)
 						do {
 							if (ctx->ir_base[input].op == IR_LOAD) {
 								input = ctx->ir_base[input].op2;
+								use_flags = IR_USE_MUST_BE_IN_REG;
 								if (input < 0 || ctx->rules[input] != IR_SKIP_MEM) {
 									break;
 								}
diff --git a/ir_x86.dasc b/ir_x86.dasc
index a32a813..f6cb16f 100644
--- a/ir_x86.dasc
+++ b/ir_x86.dasc
@@ -1956,14 +1956,14 @@ static int32_t ir_fuse_load(ir_ctx *ctx, ir_ref ref, ir_reg *preg)
 	if (!IR_IS_CONST_REF(load_insn->op2)
 	 && ir_rule(ctx, load_insn->op2) != IR_SKIP_MEM) {
 		/* just fuse the LOAD itself */
-		if (*preg != IR_REG_NONE) {
+		if (*preg != IR_REG_NONE && *preg != ctx->regs[load_insn->op2][0]) {
 			IR_ASSERT(!((*preg) & IR_REG_SPILL_LOAD));
 		} else {
 			ir_reg reg = ctx->regs[load_insn->op2][0];
 			IR_ASSERT(reg != IR_REG_NONE);
 			if (reg & IR_REG_SPILL_LOAD) {
 				reg &= ~IR_REG_SPILL_LOAD;
-				ir_emit_load(ctx, load_insn->type, reg, load_insn->op2);
+				ir_emit_load(ctx, IR_ADDR, reg, load_insn->op2);
 			}
 			*preg = reg;
 		}