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Create fixed interval for a temporary register used for DESSA moves
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parent
8770d21673
commit
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2
TODO
2
TODO
@ -73,7 +73,7 @@
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- dessa_move (push, pop)
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- param_move
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- temporary register (e.g. for unsupported immediate operand in mul, div)
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- temporary register for swap (dessa3.ir)
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+ temporary register for swap (dessa3.ir)
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- temporary register for spill loads and stores
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- parallel parameter loading
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+ parallel argument passing
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27
ir_ra.c
27
ir_ra.c
@ -929,8 +929,26 @@ static int ir_live_range_cmp(const void *r1, const void *r2, void *data)
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return lrg2->start - lrg1->start;
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}
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static int ir_fix_dessa_tmps(ir_ctx *ctx, uint8_t type, int from, int to)
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{
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if (to == 0) {
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ir_block *bb = ctx->data;
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if (IR_IS_TYPE_INT(type)) {
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ir_add_fixed_live_range(ctx, IR_REG_R0, bb->end * 2, bb->end * 2); // TODO: Temporary register
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} else if (IR_IS_TYPE_FP(type)) {
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ir_add_fixed_live_range(ctx, IR_REG_XMM0, bb->end * 2, bb->end * 2); // TODO: Temporary register
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} else {
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IR_ASSERT(0);
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}
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}
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return 1;
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}
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static int ir_linear_scan(ir_ctx *ctx)
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{
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int b;
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ir_block *bb;
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ir_worklist unhandled;
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ir_bitset active, inactive;
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ir_live_interval *ival;
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@ -944,6 +962,15 @@ static int ir_linear_scan(ir_ctx *ctx)
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return 0;
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}
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/* Add fixed intervals for temporary registers used for DESSA moves */
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for (b = 1, bb = &ctx->cfg_blocks[1]; b <= ctx->cfg_blocks_count; b++, bb++) {
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if (bb->flags & IR_BB_DESSA_MOVES) {
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ctx->data = bb;
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ir_gen_dessa_moves(ctx, b, ir_fix_dessa_tmps);
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}
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}
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ctx->data = &data;
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data.stack_frame_size = 0;
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ir_worklist_init(&unhandled, ctx->vregs_count + 1);
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len = ir_bitset_len(ctx->vregs_count + 1 + IR_REG_NUM);
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