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Eliminate duplicate spill loads at the same basic block

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This commit is contained in:
Dmitry Stogov 2023-06-22 01:24:50 +03:00
parent bfb527509d
commit 5d05d78462
11 changed files with 49 additions and 46 deletions
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55
ir_ra.c
View File

@ -3561,11 +3561,13 @@ static void assign_regs(ir_ctx *ctx)
if (ival) {
do {
if (ival->reg != IR_REG_NONE) {
ir_ref prev_use_ref = IR_UNUSED;
IR_REGSET_INCL(used_regs, ival->reg);
use_pos = ival->use_pos;
while (use_pos) {
reg = ival->reg;
ref = (use_pos->hint_ref < 0) ? -use_pos->hint_ref : IR_LIVE_POS_TO_REF(use_pos->pos);
ref = IR_LIVE_POS_TO_REF(use_pos->pos);
if (use_pos->op_num == 0
&& (use_pos->flags & IR_DEF_REUSES_OP1_REG)
&& ctx->regs[ref][1] != IR_REG_NONE
@ -3592,31 +3594,51 @@ static void assign_regs(ir_ctx *ctx)
// TODO: Insert spill loads and stotres in optimal positons (resolution)
if (use_pos->op_num == 0) {
if (top_ival->flags & IR_LIVE_INTERVAL_SPILL_SPECIAL) {
reg |= IR_REG_SPILL_SPECIAL;
if (ctx->ir_base[ref].op == IR_PHI) {
/* Spilled PHI var is passed through memory */
reg = IR_REG_NONE;
} else {
reg |= IR_REG_SPILL_STORE;
if (top_ival->flags & IR_LIVE_INTERVAL_SPILL_SPECIAL) {
reg |= IR_REG_SPILL_SPECIAL;
} else {
reg |= IR_REG_SPILL_STORE;
}
prev_use_ref = ref;
}
} else {
if ((use_pos->flags & IR_USE_MUST_BE_IN_REG)
|| ctx->ir_base[ref].op == IR_CALL
|| ctx->ir_base[ref].op == IR_TAILCALL
|| ctx->ir_base[ref].op == IR_SNAPSHOT) {
} else if (!prev_use_ref
|| ctx->cfg_map[prev_use_ref] != ctx->cfg_map[ref]) {
if (!(use_pos->flags & IR_USE_MUST_BE_IN_REG)
&& use_pos->hint != reg
// && ctx->ir_base[ref].op != IR_CALL
// && ctx->ir_base[ref].op != IR_TAILCALL) {
&& ctx->ir_base[ref].op != IR_SNAPSHOT) {
/* fuse spill load (valid only when register is not reused) */
reg = IR_REG_NONE;
} else {
if (top_ival->flags & IR_LIVE_INTERVAL_SPILL_SPECIAL) {
reg |= IR_REG_SPILL_SPECIAL;
} else {
reg |= IR_REG_SPILL_LOAD;
}
} else if (use_pos->op_num == 2
&& ctx->ir_base[ref].op1 == ctx->ir_base[ref].op2
&& IR_REG_NUM(ctx->regs[ref][1]) == reg) {
/* pass */
} else {
/* fuse spill load (valid only when register is not reused) */
if (ctx->ir_base[ref].op != IR_SNAPSHOT) {
prev_use_ref = ref;
}
}
} else if (use_pos->flags & IR_PHI_USE) {
IR_ASSERT(use_pos->hint_ref < 0);
IR_ASSERT(ctx->vregs[-use_pos->hint_ref]);
IR_ASSERT(ctx->live_intervals[ctx->vregs[-use_pos->hint_ref]]);
if (ctx->live_intervals[ctx->vregs[-use_pos->hint_ref]]->flags & IR_LIVE_INTERVAL_SPILLED) {
/* Spilled PHI var is passed through memory */
reg = IR_REG_NONE;
}
} else {
/* reuse register without spill load */
}
}
if (use_pos->hint_ref < 0) {
ref = -use_pos->hint_ref;
}
ir_set_alocated_reg(ctx, ref, use_pos->op_num, reg);
use_pos = use_pos->next;
@ -3625,8 +3647,9 @@ static void assign_regs(ir_ctx *ctx)
&& !(top_ival->flags & IR_LIVE_INTERVAL_SPILL_SPECIAL)) {
use_pos = ival->use_pos;
while (use_pos) {
ref = (use_pos->hint_ref < 0) ? -use_pos->hint_ref : IR_LIVE_POS_TO_REF(use_pos->pos);
ref = IR_LIVE_POS_TO_REF(use_pos->pos);
if (ctx->ir_base[ref].op == IR_SNAPSHOT) {
IR_ASSERT(use_pos->hint_ref >= 0);
/* A reference to a CPU spill slot */
reg = IR_REG_SPILL_STORE | IR_REG_STACK_POINTER;
ir_set_alocated_reg(ctx, ref, use_pos->op_num, reg);

4
tests/debug.aarch64/regset-fib.irt
View File

@ -89,11 +89,8 @@ test:
ldr d0, [x29, #0x10]
fadd d1, d1, d0
str d1, [x29, #0x18]
ldr d1, [x29, #0x18]
ldr d0, [x29, #0x10]
fsub d0, d1, d0
str d0, [x29, #0x10]
ldr d0, [x29, #0x10]
adr x0, .L5
bl _IO_printf
b .L1
@ -102,7 +99,6 @@ test:
ldp x29, x30, [sp], #0x20
ret
.rodata
.db 0x1f, 0x20, 0x03, 0xd5
.L3:
.db 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x3f
.L4:

4
tests/debug.aarch64/regset-fib2.irt
View File

@ -89,11 +89,8 @@ test:
ldr d0, [x29, #0x10]
fadd d1, d1, d0
str d1, [x29, #0x18]
ldr d1, [x29, #0x18]
ldr d0, [x29, #0x10]
fsub d0, d1, d0
str d0, [x29, #0x10]
ldr d0, [x29, #0x10]
adr x0, .L5
bl _IO_printf
adr x0, .L5
@ -105,6 +102,7 @@ test:
ldp x29, x30, [sp], #0x20
ret
.rodata
.db 0x1f, 0x20, 0x03, 0xd5
.L3:
.db 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x3f
.L4:

2
tests/debug.aarch64/regset-test.irt
View File

@ -167,8 +167,6 @@ test:
ldr d0, [sp, #0x10]
fmul d0, d0, d0
str d0, [sp, #0x28]
ldr d0, [sp, #0x28]
ldr d1, [sp, #0x20]
fadd d0, d0, d1
ldr d1, .L5
fcmp d0, d1

6
tests/debug.x86/fig.irt
View File

@ -78,15 +78,14 @@ test:
movl %edx, %ebp
imull %ecx, %ebp
movl %ebp, (%esp)
movl (%esp), %ebp
leal 4(%ebp), %ebp
movl %ebp, 4(%esp)
.L1:
cmpl $0, 0x3c(%esp)
je .L3
movl 4(%esp), %eax
movl %eax, 0x30(%esp)
movl %edx, %eax
movl 4(%esp), %ebp
movl %ebp, 0x30(%esp)
.L2:
cmpl $0, 0x40(%esp)
jne .L1
@ -114,7 +113,6 @@ test:
movl %eax, %esi
imull %ecx, %esi
movl %esi, 0x34(%esp)
movl 0x34(%esp), %esi
leal 1(%esi), %edi
movl %edi, 0x38(%esp)
movl %edx, %ebx

6
tests/debug.x86/regset-fib.irt
View File

@ -84,12 +84,10 @@ test:
movsd 0xc(%esp), %xmm0
addsd %xmm1, %xmm0
movsd %xmm0, 0xc(%esp)
movsd 0xc(%esp), %xmm0
subsd %xmm1, %xmm0
movsd %xmm0, 0x14(%esp)
movl $.L5, (%esp)
movsd 0x14(%esp), %xmm0
movsd %xmm0, 4(%esp)
movl $.L5, (%esp)
calll printf
movsd 0x14(%esp), %xmm1
jmp .L1
@ -98,7 +96,7 @@ test:
addl $0x1c, %esp
retl
.rodata
.db 0x90, 0x90, 0x90
.db 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90
.L3:
.db 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x3f
.L4:

6
tests/debug.x86/regset-fib2.irt
View File

@ -84,12 +84,10 @@ test:
movsd 0xc(%esp), %xmm0
addsd %xmm1, %xmm0
movsd %xmm0, 0xc(%esp)
movsd 0xc(%esp), %xmm0
subsd %xmm1, %xmm0
movsd %xmm0, 0x14(%esp)
movl $.L5, (%esp)
movsd 0x14(%esp), %xmm0
movsd %xmm0, 4(%esp)
movl $.L5, (%esp)
calll printf
movl $.L5, (%esp)
movsd 0x14(%esp), %xmm7
@ -102,7 +100,7 @@ test:
addl $0x1c, %esp
retl
.rodata
.db 0x90, 0x90, 0x90
.db 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90
.L3:
.db 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x3f
.L4:

2
tests/debug.x86/regset-test.irt
View File

@ -153,7 +153,6 @@ test:
movapd %xmm1, %xmm0
mulsd %xmm1, %xmm0
movsd %xmm0, 0x18(%esp)
movsd 0x18(%esp), %xmm0
addsd 0x10(%esp), %xmm0
ucomisd .L5, %xmm0
ja .L2
@ -175,6 +174,7 @@ test:
addl $0x20, %esp
retl
.rodata
.db 0x90, 0x90, 0x90, 0x90, 0x90, 0x90
.L4:
.db 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x3f
.L5:

3
tests/debug/regset-fib.irt
View File

@ -86,10 +86,8 @@ test:
movsd (%rsp), %xmm0
addsd %xmm1, %xmm0
movsd %xmm0, (%rsp)
movsd (%rsp), %xmm0
subsd %xmm1, %xmm0
movsd %xmm0, 8(%rsp)
movsd 8(%rsp), %xmm0
leaq .L5(%rip), %rdi
movabsq $_IO_printf, %rax
callq *%rax
@ -100,7 +98,6 @@ test:
addq $0x18, %rsp
retq
.rodata
.db 0x90, 0x90, 0x90, 0x90, 0x90
.L3:
.db 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x3f
.L4:

4
tests/debug/regset-fib2.irt
View File

@ -86,10 +86,8 @@ test:
movsd (%rsp), %xmm0
addsd %xmm1, %xmm0
movsd %xmm0, (%rsp)
movsd (%rsp), %xmm0
subsd %xmm1, %xmm0
movsd %xmm0, 8(%rsp)
movsd 8(%rsp), %xmm0
leaq .L5(%rip), %rdi
movabsq $_IO_printf, %rax
callq *%rax
@ -104,7 +102,7 @@ test:
addq $0x18, %rsp
retq
.rodata
.db 0x90, 0x90, 0x90, 0x90
.db 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90
.L3:
.db 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x3f
.L4:

3
tests/debug/regset-test.irt
View File

@ -155,7 +155,6 @@ test:
movapd %xmm1, %xmm0
mulsd %xmm1, %xmm0
movsd %xmm0, 0x20(%rsp)
movsd 0x20(%rsp), %xmm0
addsd 0x18(%rsp), %xmm0
ucomisd .L5(%rip), %xmm0
ja .L2
@ -177,7 +176,7 @@ test:
addq $0x28, %rsp
retq
.rodata
.db 0x90, 0x90, 0x90, 0x90, 0x90
.db 0x90, 0x90, 0x90
.L4:
.db 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x3f
.L5: