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https://github.com/danog/ir.git
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Speed-up liner scan
- Don't add allocated interval into "active" list, if it doesn't overlap with next unhandled - More efficient selection of registers available for the whole range
This commit is contained in:
Dmitry Stogov
parent
38ee633419
commit
6009e376b7
102
ir_ra.c
102
ir_ra.c
@ -2517,7 +2517,7 @@ static ir_reg ir_try_allocate_free_reg(ir_ctx *ctx, ir_live_interval *ival, ir_l
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int i, reg;
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ir_live_pos pos, next;
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ir_live_interval *other;
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ir_regset available;
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ir_regset available, overlapped, scratch;
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if (IR_IS_TYPE_FP(ival->type)) {
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available = IR_REGSET_FP;
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@ -2570,6 +2570,7 @@ static ir_reg ir_try_allocate_free_reg(ir_ctx *ctx, ir_live_interval *ival, ir_l
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* This loop is not necessary for program in SSA form (see LSRA on SSA fig. 6),
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* but it is still necessary after coalescing and splitting
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*/
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overlapped = IR_REGSET_EMPTY;
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other = inactive;
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pos = ival->end;
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while (other) {
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@ -2588,12 +2589,14 @@ static ir_reg ir_try_allocate_free_reg(ir_ctx *ctx, ir_live_interval *ival, ir_l
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IR_ASSERT(reg == IR_REG_ALL);
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regset = available;
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}
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overlapped = IR_REGSET_UNION(overlapped, regset);
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IR_REGSET_FOREACH(regset, reg) {
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if (next < freeUntilPos[reg]) {
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freeUntilPos[reg] = next;
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}
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} IR_REGSET_FOREACH_END();
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} else if (IR_REGSET_IN(available, reg)) {
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IR_REGSET_INCL(overlapped, reg);
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if (next < freeUntilPos[reg]) {
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freeUntilPos[reg] = next;
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}
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@ -2603,36 +2606,57 @@ static ir_reg ir_try_allocate_free_reg(ir_ctx *ctx, ir_live_interval *ival, ir_l
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other = other->list_next;
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}
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if (ival->flags & (IR_LIVE_INTERVAL_HAS_HINT_REGS|IR_LIVE_INTERVAL_HAS_HINT_REFS)) {
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/* Try to use hint */
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reg = ir_try_allocate_preferred_reg(ctx, ival, available, freeUntilPos);
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if (reg != IR_REG_NONE) {
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ival->reg = reg;
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IR_LOG_LSRA_ASSIGN(" ---- Assign", ival, " (hint available without spilling)");
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ival->list_next = *active;
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*active = ival;
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return reg;
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}
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}
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available = IR_REGSET_DIFFERENCE(available, overlapped);
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if (available != IR_REGSET_EMPTY) {
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if (ival->flags & IR_LIVE_INTERVAL_SPLIT_CHILD) {
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/* Try to reuse the register previously allocated for splited interval */
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reg = ctx->live_intervals[ival->vreg]->reg;
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if (reg >= 0
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&& IR_REGSET_IN(available, reg)
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&& ival->end <= freeUntilPos[reg]) {
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ival->reg = reg;
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IR_LOG_LSRA_ASSIGN(" ---- Assign", ival, " (available without spilling)");
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if (ival->flags & (IR_LIVE_INTERVAL_HAS_HINT_REGS|IR_LIVE_INTERVAL_HAS_HINT_REFS)) {
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/* Try to use hint */
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reg = ir_try_allocate_preferred_reg(ctx, ival, available, freeUntilPos);
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if (reg != IR_REG_NONE) {
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ival->reg = reg;
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IR_LOG_LSRA_ASSIGN(" ---- Assign", ival, " (hint available without spilling)");
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if (*unhandled && ival->end > (*unhandled)->range.start) {
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ival->list_next = *active;
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*active = ival;
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}
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return reg;
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}
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}
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if (ival->flags & IR_LIVE_INTERVAL_SPLIT_CHILD) {
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/* Try to reuse the register previously allocated for splited interval */
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reg = ctx->live_intervals[ival->vreg]->reg;
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if (reg >= 0 && IR_REGSET_IN(available, reg)) {
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ival->reg = reg;
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IR_LOG_LSRA_ASSIGN(" ---- Assign", ival, " (available without spilling)");
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if (*unhandled && ival->end > (*unhandled)->range.start) {
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ival->list_next = *active;
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*active = ival;
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}
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return reg;
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}
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}
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scratch = IR_REGSET_INTERSECTION(available, IR_REGSET_SCRATCH);
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if (scratch != IR_REGSET_EMPTY) {
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/* prefer caller-saved registers to avoid save/restore in prologue/epilogue */
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reg = IR_REGSET_FIRST(scratch);
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} else {
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reg = IR_REGSET_FIRST(available);
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}
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ival->reg = reg;
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IR_LOG_LSRA_ASSIGN(" ---- Assign", ival, " (available without spilling)");
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if (*unhandled && ival->end > (*unhandled)->range.start) {
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ival->list_next = *active;
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*active = ival;
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return reg;
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}
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return reg;
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}
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/* reg = register with highest freeUntilPos */
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reg = IR_REG_NONE;
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pos = 0;
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IR_REGSET_FOREACH(available, i) {
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IR_REGSET_FOREACH(overlapped, i) {
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if (freeUntilPos[i] > pos) {
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pos = freeUntilPos[i];
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reg = i;
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@ -2645,17 +2669,7 @@ static ir_reg ir_try_allocate_free_reg(ir_ctx *ctx, ir_live_interval *ival, ir_l
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}
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} IR_REGSET_FOREACH_END();
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if (!pos) {
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/* no register available without spilling */
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return IR_REG_NONE;
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} else if (ival->end <= pos) {
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/* register available for the whole interval */
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ival->reg = reg;
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IR_LOG_LSRA_ASSIGN(" ---- Assign", ival, " (available without spilling)");
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ival->list_next = *active;
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*active = ival;
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return reg;
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} else if (pos > ival->range.start) {
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if (pos > ival->range.start) {
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/* register available for the first part of the interval */
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/* split current before freeUntilPos[reg] */
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ir_live_pos split_pos = ir_last_use_pos_before(ival, pos,
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@ -2664,7 +2678,7 @@ static ir_reg ir_try_allocate_free_reg(ir_ctx *ctx, ir_live_interval *ival, ir_l
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split_pos = ir_find_optimal_split_position(ctx, ival, split_pos, pos, 0);
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other = ir_split_interval_at(ctx, ival, split_pos);
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if (ival->flags & (IR_LIVE_INTERVAL_HAS_HINT_REGS|IR_LIVE_INTERVAL_HAS_HINT_REFS)) {
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ir_reg pref_reg = ir_try_allocate_preferred_reg(ctx, ival, available, freeUntilPos);
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ir_reg pref_reg = ir_try_allocate_preferred_reg(ctx, ival, IR_REGSET_UNION(available, overlapped), freeUntilPos);
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if (pref_reg != IR_REG_NONE) {
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ival->reg = pref_reg;
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@ -2675,8 +2689,10 @@ static ir_reg ir_try_allocate_free_reg(ir_ctx *ctx, ir_live_interval *ival, ir_l
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ival->reg = reg;
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}
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IR_LOG_LSRA_ASSIGN(" ---- Assign", ival, " (available without spilling for the first part)");
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ival->list_next = *active;
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*active = ival;
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if (*unhandled && ival->end > (*unhandled)->range.start) {
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ival->list_next = *active;
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*active = ival;
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}
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ir_add_to_unhandled(unhandled, other);
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IR_LOG_LSRA(" ---- Queue", other, "");
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return reg;
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@ -2994,9 +3010,11 @@ spill_current:
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/* current.reg = reg */
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ival->reg = reg;
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IR_LOG_LSRA_ASSIGN(" ---- Assign", ival, " (after splitting others)");
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ival->list_next = *active;
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*active = ival;
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if (*unhandled && ival->end > (*unhandled)->range.start) {
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ival->list_next = *active;
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*active = ival;
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}
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return reg;
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}
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@ -3275,7 +3293,7 @@ static int ir_linear_scan(ir_ctx *ctx)
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other->current_range = r;
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}
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if (position >= r->start) {
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/* move i from active to inactive */
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/* move i from inactive to active */
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if (prev) {
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prev->list_next = other->list_next;
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} else {
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@ -3380,8 +3398,10 @@ static int ir_linear_scan(ir_ctx *ctx)
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} else {
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ival->stack_spill_pos = ir_allocate_spill_slot(ctx, ival->type, &data);
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}
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ival->list_next = active;
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active = ival;
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if (unhandled && ival->end > unhandled->range.start) {
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ival->list_next = active;
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active = ival;
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}
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}
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}
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}
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