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More accurate spill loads optimization for instructions that reuse op1 register for result

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This also fixes possbile incorrect register-allocation/code-generation
for SHIFT instuction on x86[_64]
This commit is contained in:
Dmitry Stogov 2023-06-29 12:42:44 +03:00
parent 865daeb988
commit 7058c41411
23 changed files with 148 additions and 159 deletions
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83
ir_ra.c
View File

@ -1366,7 +1366,11 @@ int ir_compute_live_ranges(ir_ctx *ctx)
if (!IR_IS_CONST_REF(insn->op1) && ctx->vregs[insn->op1]) {
hint_ref = insn->op1;
}
def_pos = IR_LOAD_LIVE_POS_FROM_REF(ref);
if (def_flags & IR_DEF_CONFLICTS_WITH_INPUT_REGS) {
def_pos = IR_USE_LIVE_POS_FROM_REF(ref);
} else {
def_pos = IR_LOAD_LIVE_POS_FROM_REF(ref);
}
} else if (def_flags & IR_DEF_CONFLICTS_WITH_INPUT_REGS) {
def_pos = IR_LOAD_LIVE_POS_FROM_REF(ref);
} else {
@ -1418,7 +1422,11 @@ int ir_compute_live_ranges(ir_ctx *ctx)
ir_add_fixed_live_range(ctx, reg, use_pos, use_pos + IR_USE_SUB_REF);
} else if (def_flags & IR_DEF_REUSES_OP1_REG) {
if (j == 1) {
use_pos = IR_LOAD_LIVE_POS_FROM_REF(ref);
if (def_flags & IR_DEF_CONFLICTS_WITH_INPUT_REGS) {
use_pos = IR_USE_LIVE_POS_FROM_REF(ref);
} else {
use_pos = IR_LOAD_LIVE_POS_FROM_REF(ref);
}
IR_ASSERT(ctx->vregs[ref]);
hint_ref = ref;
} else if (input == insn->op1) {
@ -3594,6 +3602,18 @@ static bool needs_spill_reload(ir_ctx *ctx, ir_live_interval *ival, uint32_t b0,
return 0;
}
static bool needs_spill_load(ir_ctx *ctx, ir_live_interval *ival, ir_use_pos *use_pos)
{
if (use_pos->next
&& use_pos->op_num == 1
&& use_pos->next->pos == use_pos->pos
&& !(use_pos->next->flags & IR_USE_MUST_BE_IN_REG)) {
/* Support for R2 = ADD(R1, R1) */
use_pos = use_pos->next;
}
return use_pos->next && use_pos->next->op_num != 0;
}
static void assign_regs(ir_ctx *ctx)
{
ir_ref i;
@ -3641,28 +3661,6 @@ static void assign_regs(ir_ctx *ctx)
while (use_pos) {
reg = ival->reg;
ref = IR_LIVE_POS_TO_REF(use_pos->pos);
if (use_pos->op_num == 0
&& (use_pos->flags & IR_DEF_REUSES_OP1_REG)
&& ctx->regs[ref][1] != IR_REG_NONE
&& IR_REG_SPILLED(ctx->regs[ref][1])
&& IR_REG_NUM(ctx->regs[ref][1]) != reg
&& IR_REG_NUM(ctx->regs[ref][2]) != reg
&& IR_REG_NUM(ctx->regs[ref][3]) != reg) {
/* load op1 directly into result (valid only when op1 register is not reused) */
ir_reg old_reg = IR_REG_NUM(ctx->regs[ref][1]);
if (ctx->live_intervals[ctx->vregs[ctx->ir_base[ref].op1]]->flags & IR_LIVE_INTERVAL_SPILL_SPECIAL) {
ctx->regs[ref][1] = reg | IR_REG_SPILL_SPECIAL;
} else {
ctx->regs[ref][1] = reg | IR_REG_SPILL_LOAD;
}
if (IR_REG_NUM(ctx->regs[ref][2]) == old_reg) {
ctx->regs[ref][2] = reg;
}
if (IR_REG_NUM(ctx->regs[ref][3]) == old_reg) {
ctx->regs[ref][3] = reg;
}
}
if (use_pos->hint_ref < 0) {
ref = -use_pos->hint_ref;
}
@ -3684,29 +3682,6 @@ static void assign_regs(ir_ctx *ctx)
while (use_pos) {
reg = ival->reg;
ref = IR_LIVE_POS_TO_REF(use_pos->pos);
if (use_pos->op_num == 0
&& (use_pos->flags & IR_DEF_REUSES_OP1_REG)
&& ctx->regs[ref][1] != IR_REG_NONE
&& IR_REG_SPILLED(ctx->regs[ref][1])
&& IR_REG_NUM(ctx->regs[ref][1]) != reg
&& IR_REG_NUM(ctx->regs[ref][2]) != reg
&& IR_REG_NUM(ctx->regs[ref][3]) != reg) {
/* load op1 directly into result (valid only when op1 register is not reused) */
ir_reg old_reg = IR_REG_NUM(ctx->regs[ref][1]);
if (ctx->live_intervals[ctx->vregs[ctx->ir_base[ref].op1]]->flags & IR_LIVE_INTERVAL_SPILL_SPECIAL) {
ctx->regs[ref][1] = reg | IR_REG_SPILL_SPECIAL;
} else {
ctx->regs[ref][1] = reg | IR_REG_SPILL_LOAD;
}
if (IR_REG_NUM(ctx->regs[ref][2]) == old_reg) {
ctx->regs[ref][2] = reg;
}
if (IR_REG_NUM(ctx->regs[ref][3]) == old_reg) {
ctx->regs[ref][3] = reg;
}
}
// TODO: Insert spill loads and stotres in optimal positons (resolution)
if (use_pos->op_num == 0) {
if (ctx->ir_base[ref].op == IR_PHI) {
@ -3731,9 +3706,21 @@ static void assign_regs(ir_ctx *ctx)
&& use_pos->hint != reg
// && ctx->ir_base[ref].op != IR_CALL
// && ctx->ir_base[ref].op != IR_TAILCALL) {
&& ctx->ir_base[ref].op != IR_SNAPSHOT) {
&& ctx->ir_base[ref].op != IR_SNAPSHOT
&& !needs_spill_load(ctx, ival, use_pos)) {
/* fuse spill load (valid only when register is not reused) */
reg = IR_REG_NONE;
if (use_pos->next
&& use_pos->op_num == 1
&& use_pos->next->pos == use_pos->pos
&& !(use_pos->next->flags & IR_USE_MUST_BE_IN_REG)) {
/* Support for R2 = BINOP(R1, R1) */
if (use_pos->hint_ref < 0) {
ref = -use_pos->hint_ref;
}
ir_set_alocated_reg(ctx, ref, use_pos->op_num, reg);
use_pos = use_pos->next;
}
} else {
if (top_ival->flags & IR_LIVE_INTERVAL_SPILL_SPECIAL) {
reg |= IR_REG_SPILL_SPECIAL;

14
ir_x86.dasc
View File

@ -541,7 +541,7 @@ int ir_get_target_constraints(const ir_ctx *ctx, ir_ref ref, ir_target_constrain
flags = IR_OP2_MUST_BE_IN_REG;
}
} else {
flags = IR_DEF_REUSES_OP1_REG | IR_USE_MUST_BE_IN_REG | IR_OP1_MUST_BE_IN_REG | IR_OP2_SHOULD_BE_IN_REG;
flags = IR_DEF_REUSES_OP1_REG | IR_USE_MUST_BE_IN_REG | IR_OP1_SHOULD_BE_IN_REG | IR_OP2_SHOULD_BE_IN_REG;
}
if (IR_IS_CONST_REF(insn->op2) && insn->op1 != insn->op2) {
insn = &ctx->ir_base[insn->op2];
@ -558,7 +558,7 @@ int ir_get_target_constraints(const ir_ctx *ctx, ir_ref ref, ir_target_constrain
if (rule & IR_FUSED) {
flags = IR_OP2_MUST_BE_IN_REG;
} else {
flags = IR_DEF_REUSES_OP1_REG | IR_USE_MUST_BE_IN_REG | IR_OP1_MUST_BE_IN_REG | IR_OP2_SHOULD_BE_IN_REG;
flags = IR_DEF_REUSES_OP1_REG | IR_DEF_CONFLICTS_WITH_INPUT_REGS | IR_USE_MUST_BE_IN_REG | IR_OP1_SHOULD_BE_IN_REG | IR_OP2_SHOULD_BE_IN_REG;
}
constraints->hints[1] = IR_REG_NONE;
constraints->hints[2] = IR_REG_RCX;
@ -749,7 +749,7 @@ op2_const:
flags = IR_USE_SHOULD_BE_IN_REG | IR_OP2_SHOULD_BE_IN_REG | IR_OP3_SHOULD_BE_IN_REG;
break;
case IR_BINOP_SSE2:
flags = IR_DEF_REUSES_OP1_REG | IR_USE_MUST_BE_IN_REG | IR_OP1_MUST_BE_IN_REG | IR_OP2_SHOULD_BE_IN_REG;
flags = IR_DEF_REUSES_OP1_REG | IR_USE_MUST_BE_IN_REG | IR_OP1_SHOULD_BE_IN_REG | IR_OP2_SHOULD_BE_IN_REG;
break;
case IR_SHIFT_CONST:
case IR_INC:
@ -759,7 +759,7 @@ op2_const:
case IR_MOD_PWR2:
case IR_OP_INT:
case IR_OP_FP:
flags = IR_DEF_REUSES_OP1_REG | IR_USE_MUST_BE_IN_REG | IR_OP1_MUST_BE_IN_REG;
flags = IR_DEF_REUSES_OP1_REG | IR_USE_MUST_BE_IN_REG | IR_OP1_SHOULD_BE_IN_REG;
break;
case IR_COPY_INT:
case IR_COPY_FP:
@ -2238,6 +2238,9 @@ static void ir_emit_binop_int(ir_ctx *ctx, ir_ref def, ir_insn *insn)
} else {
ir_emit_load(ctx, type, def_reg, op1);
}
if (op1 == op2) {
op2_reg = def_reg;
}
}
if (op2_reg != IR_REG_NONE) {
@ -3468,6 +3471,9 @@ static void ir_emit_binop_sse2(ir_ctx *ctx, ir_ref def, ir_insn *insn)
} else {
ir_emit_load(ctx, type, def_reg, op1);
}
if (op1 == op2) {
op2_reg = def_reg;
}
}
if (op2_reg != IR_REG_NONE) {
if (IR_REG_SPILLED(op2_reg) || IR_IS_CONST_REF(op2)) {

2
tests/Windows-x86_64/mul_005.irt
View File

@ -15,5 +15,5 @@ Windows-x86_64
--EXPECT--
test:
movw %cx, %ax
addw %cx, %ax
addw %ax, %ax
retq

2
tests/debug.Windows-x86_64/regset-fib.irt
View File

@ -63,7 +63,7 @@ TMP
[%xmm0]: [13.2-13.3)/1
R1 (d_4) [%xmm0]: [3.0-10.1), DEF(4.2), USE(9.1/2), USE(10.1/2)
R2 (d_5, d_9) [SPILL=0x0]
[%xmm1]: [3.0-10.0), DEF(5.2), USE(7.1/6.1)!, USE(9.0/1)!, DEF(9.0)!, USE(10.0/1, hint=%xmm1, hint=R3)!
[%xmm1]: [3.0-10.0), DEF(5.2), USE(7.1/6.1)!, USE(9.0/1), DEF(9.0)!, USE(10.0/1, hint=%xmm1, hint=R3)
: [10.0-14.0), PHI_USE(13.2, phi=d_5/3)
R3 (d_10) [SPILL=0x8]
[%xmm1]: [10.0-11.0), DEF(10.0, hint=R2)!, USE(11.0/4, hint=%xmm1)

2
tests/debug.Windows-x86_64/regset-fib2.irt
View File

@ -63,7 +63,7 @@ TMP
[%xmm0]: [15.2-15.3)/1
R1 (d_4) [%xmm0]: [3.0-10.1), DEF(4.2), USE(9.1/2), USE(10.1/2)
R2 (d_5, d_9) [SPILL=0x0]
[%xmm1]: [3.0-10.0), DEF(5.2), USE(7.1/6.1)!, USE(9.0/1)!, DEF(9.0)!, USE(10.0/1, hint=%xmm1, hint=R3)!
[%xmm1]: [3.0-10.0), DEF(5.2), USE(7.1/6.1)!, USE(9.0/1), DEF(9.0)!, USE(10.0/1, hint=%xmm1, hint=R3)
: [10.0-16.0), PHI_USE(15.2, phi=d_5/3)
R3 (d_10) [SPILL=0x8]
[%xmm1]: [10.0-11.0), DEF(10.0, hint=R2)!, USE(11.0/4, hint=%xmm1)

53
tests/debug.Windows-x86_64/regset-test.irt
View File

@ -110,30 +110,29 @@ R1 (d_2) [SPILL=0x0]
[%xmm0]: [2.3-10.2), DEF(2.3, hint=%xmm0)
: [10.2-24.0), [26.0-29.0), [31.0-36.0)
: [36.0-38.0), USE(36.1/2)
R2 (d_3) [%xmm1]: [3.3-5.0), DEF(3.3, hint=%xmm1), USE(5.0/1, hint=R3)!
R2 (d_3) [%xmm1]: [3.3-5.0), DEF(3.3, hint=%xmm1), USE(5.0/1, hint=R3)
R3 (d_5) [SPILL=0x8]
[%xmm1]: [5.0-10.2), DEF(5.0, hint=R2)!
: [10.2-24.0), [26.0-29.0), [31.0-34.0)
: [34.0-38.0), USE(34.1/2)
R4 (d_12, d_36) [SPILL=0x10]
[%xmm1]: [11.0-20.0), DEF(12.2), USE(20.0/1, hint=R8)!, USE(20.0/2)
: [20.0-24.0), [26.0-29.0), [31.0-31.3)
[%xmm1]: [31.3-32.0), [36.0-38.0), USE(32.0/1)!, DEF(36.0, hint=R12)!, PHI_USE(37.2, phi=d_12/3)
: [11.0-24.0), [26.0-29.0), [31.0-32.0), DEF(12.2), USE(20.0/1, hint=R8), USE(20.0/2), USE(32.0/1)
[%xmm0]: [36.0-38.0), DEF(36.0, hint=R12)!, PHI_USE(37.2, phi=d_12/3)
R5 (d_13, d_34) [SPILL=0x18]
[%xmm0]: [11.0-18.0), DEF(13.2), USE(18.0/1, hint=R7)!, USE(18.0/2)
: [18.0-24.0), [26.0-29.0), [31.0-32.0)
[%xmm0]: [11.0-20.0), DEF(13.2), USE(18.0/1, hint=R7), USE(18.0/2)
: [20.0-24.0), [26.0-29.0), [31.0-32.0)
: [32.0-32.1), USE(32.1/2, hint=R10)
[%xmm0]: [34.0-38.0), DEF(34.0, hint=R11)!, PHI_USE(37.2, phi=d_13/3)
[%xmm1]: [34.0-38.0), DEF(34.0, hint=R11)!, PHI_USE(37.2, phi=d_13/3)
R6 (d_14, d_15) [%eax]: [11.0-15.1), [15.2-25.0), [26.0-29.0), [31.0-38.0), DEF(14.2), USE(15.1/1)!, DEF(15.2)!, USE(25.0/2, hint=%eax), USE(28.1/27.1), PHI_USE(37.2, phi=d_14/3)
R7 (d_18) [%xmm0]: [18.0-24.0), [26.0-29.0), [31.0-33.0), DEF(18.0, hint=R5)!, USE(21.1/2), USE(33.0/1, hint=R11)!
R7 (d_18) [%xmm1]: [18.0-24.0), [26.0-29.0), [31.0-33.0), DEF(18.0, hint=R5)!, USE(21.1/2), USE(33.0/1, hint=R11)
R8 (d_20) [SPILL=0x20]
[%xmm1]: [20.0-21.0), DEF(20.0, hint=R4)!, USE(21.0/1, hint=R9)!
[%xmm0]: [20.0-21.0), DEF(20.0, hint=R4)!, USE(21.0/1, hint=R9)
: [21.0-24.0), [26.0-29.0), [31.0-33.0)
: [33.0-33.1), USE(33.1/2)
R9 (d_21) [%xmm1]: [21.0-23.1), DEF(21.0, hint=R8)!, USE(23.1/22.1)!
R10 (d_32) [%xmm1]: [32.0-35.0), DEF(32.0, hint=R4)!, USE(35.0/1, hint=R12)!, USE(35.0/2)
R11 (d_33) [%xmm0]: [33.0-34.0), DEF(33.0, hint=R7)!, USE(34.0/1, hint=R5)!
R12 (d_35) [%xmm1]: [35.0-36.0), DEF(35.0, hint=R10)!, USE(36.0/1, hint=R4)!
R9 (d_21) [%xmm0]: [21.0-23.1), DEF(21.0, hint=R8)!, USE(23.1/22.1)!
R10 (d_32) [%xmm0]: [32.0-35.0), DEF(32.0, hint=R4)!, USE(35.0/1, hint=R12), USE(35.0/2)
R11 (d_33) [%xmm1]: [33.0-34.0), DEF(33.0, hint=R7)!, USE(34.0/1, hint=R5)
R12 (d_35) [%xmm0]: [35.0-36.0), DEF(35.0, hint=R10)!, USE(36.0/1, hint=R4)
[%rax] : [25.0-25.1), [30.0-30.1)
[%xmm0] : [1.0-2.3)
[%xmm1] : [1.0-3.3)
@ -150,24 +149,24 @@ test:
xorl %eax, %eax
.L1:
leal 1(%rax), %eax
movsd 0x18(%rsp), %xmm0
mulsd %xmm0, %xmm0
movsd 0x10(%rsp), %xmm1
movsd 0x18(%rsp), %xmm1
mulsd %xmm1, %xmm1
movsd %xmm1, 0x20(%rsp)
addsd %xmm0, %xmm1
ucomisd .L5(%rip), %xmm1
movsd 0x10(%rsp), %xmm0
mulsd %xmm0, %xmm0
movsd %xmm0, 0x20(%rsp)
addsd %xmm1, %xmm0
ucomisd .L5(%rip), %xmm0
ja .L2
cmpl $0x3e8, %eax
jg .L3
movsd 0x10(%rsp), %xmm1
mulsd 0x18(%rsp), %xmm1
subsd 0x20(%rsp), %xmm0
addsd 8(%rsp), %xmm0
movsd %xmm0, 0x18(%rsp)
addsd %xmm1, %xmm1
addsd (%rsp), %xmm1
movsd %xmm1, 0x10(%rsp)
movsd 0x10(%rsp), %xmm0
mulsd 0x18(%rsp), %xmm0
subsd 0x20(%rsp), %xmm1
addsd 8(%rsp), %xmm1
movsd %xmm1, 0x18(%rsp)
addsd %xmm0, %xmm0
addsd (%rsp), %xmm0
movsd %xmm0, 0x10(%rsp)
jmp .L1
.L2:
addq $0x28, %rsp

4
tests/debug.Windows-x86_64/test.irt
View File

@ -64,9 +64,9 @@ test:
.L1:
leal 1(%rax), %eax
movapd %xmm2, %xmm4
mulsd %xmm2, %xmm4
mulsd %xmm4, %xmm4
movapd %xmm3, %xmm5
mulsd %xmm3, %xmm5
mulsd %xmm5, %xmm5
movapd %xmm5, %xmm6
addsd %xmm4, %xmm6
ucomisd .L5(%rip), %xmm6

4
tests/debug.Windows-x86_64/test64.irt
View File

@ -64,9 +64,9 @@ test:
.L1:
leaq 1(%rax), %rax
movapd %xmm2, %xmm4
mulsd %xmm2, %xmm4
mulsd %xmm4, %xmm4
movapd %xmm3, %xmm5
mulsd %xmm3, %xmm5
mulsd %xmm5, %xmm5
movapd %xmm5, %xmm6
addsd %xmm4, %xmm6
ucomisd .L5(%rip), %xmm6

2
tests/debug.x86/regset-fib.irt
View File

@ -63,7 +63,7 @@ TMP
[%xmm0]: [13.2-13.3)/1
R1 (d_4) [%xmm1]: [3.0-10.1), DEF(4.2), USE(9.1/2), USE(10.1/2)
R2 (d_5, d_9) [SPILL=0x0]
[%xmm0]: [3.0-10.0), DEF(5.2), USE(7.1/6.1)!, USE(9.0/1)!, DEF(9.0)!, USE(10.0/1, hint=R3)!
[%xmm0]: [3.0-10.0), DEF(5.2), USE(7.1/6.1)!, USE(9.0/1), DEF(9.0)!, USE(10.0/1, hint=R3)
: [10.0-14.0), PHI_USE(13.2, phi=d_5/3)
R3 (d_10) [SPILL=0x8]
[%xmm0]: [10.0-11.1), DEF(10.0, hint=R2)!, USE(11.1/4)

2
tests/debug.x86/regset-fib2.irt
View File

@ -63,7 +63,7 @@ TMP
[%xmm0]: [15.2-15.3)/1
R1 (d_4) [%xmm1]: [3.0-10.1), DEF(4.2), USE(9.1/2), USE(10.1/2)
R2 (d_5, d_9) [SPILL=0x0]
[%xmm0]: [3.0-10.0), DEF(5.2), USE(7.1/6.1)!, USE(9.0/1)!, DEF(9.0)!, USE(10.0/1, hint=R3)!
[%xmm0]: [3.0-10.0), DEF(5.2), USE(7.1/6.1)!, USE(9.0/1), DEF(9.0)!, USE(10.0/1, hint=R3)
: [10.0-16.0), PHI_USE(15.2, phi=d_5/3)
R3 (d_10) [SPILL=0x8]
[%xmm0]: [10.0-11.1), DEF(10.0, hint=R2)!, USE(11.1/4)

53
tests/debug.x86/regset-test.irt
View File

@ -110,30 +110,29 @@ R1 (d_2) [SPILL=0x24]
[%xmm0]: [2.2-10.2), DEF(2.2)
: [10.2-24.0), [26.0-29.0), [31.0-36.0)
: [36.0-38.0), USE(36.1/2)
R2 (d_3) [%xmm1]: [3.2-5.0), DEF(3.2), USE(5.0/1, hint=R3)!
R2 (d_3) [SPILL=0x2c]: [3.2-5.0), DEF(3.2), USE(5.0/1, hint=R3)
R3 (d_5) [SPILL=0x0]
[%xmm1]: [5.0-10.2), DEF(5.0, hint=R2)!
: [10.2-24.0), [26.0-29.0), [31.0-34.0)
: [34.0-38.0), USE(34.1/2)
R4 (d_12, d_36) [SPILL=0x8]
[%xmm1]: [11.0-20.0), DEF(12.2), USE(20.0/1, hint=R8)!, USE(20.0/2)
: [20.0-24.0), [26.0-29.0), [31.0-31.3)
[%xmm1]: [31.3-32.0), [36.0-38.0), USE(32.0/1)!, DEF(36.0, hint=R12)!, PHI_USE(37.2, phi=d_12/3)
: [11.0-24.0), [26.0-29.0), [31.0-32.0), DEF(12.2), USE(20.0/1, hint=R8), USE(20.0/2), USE(32.0/1)
[%xmm0]: [36.0-38.0), DEF(36.0, hint=R12)!, PHI_USE(37.2, phi=d_12/3)
R5 (d_13, d_34) [SPILL=0x10]
[%xmm0]: [11.0-18.0), DEF(13.2), USE(18.0/1, hint=R7)!, USE(18.0/2)
: [18.0-24.0), [26.0-29.0), [31.0-32.0)
[%xmm0]: [11.0-20.0), DEF(13.2), USE(18.0/1, hint=R7), USE(18.0/2)
: [20.0-24.0), [26.0-29.0), [31.0-32.0)
: [32.0-32.1), USE(32.1/2, hint=R10)
[%xmm0]: [34.0-38.0), DEF(34.0, hint=R11)!, PHI_USE(37.2, phi=d_13/3)
[%xmm1]: [34.0-38.0), DEF(34.0, hint=R11)!, PHI_USE(37.2, phi=d_13/3)
R6 (d_14, d_15) [%eax]: [11.0-15.1), [15.2-25.0), [26.0-29.0), [31.0-38.0), DEF(14.2), USE(15.1/1)!, DEF(15.2)!, USE(25.0/2, hint=%eax), USE(28.1/27.1), PHI_USE(37.2, phi=d_14/3)
R7 (d_18) [%xmm0]: [18.0-24.0), [26.0-29.0), [31.0-33.0), DEF(18.0, hint=R5)!, USE(21.1/2), USE(33.0/1, hint=R11)!
R7 (d_18) [%xmm1]: [18.0-24.0), [26.0-29.0), [31.0-33.0), DEF(18.0, hint=R5)!, USE(21.1/2), USE(33.0/1, hint=R11)
R8 (d_20) [SPILL=0x18]
[%xmm1]: [20.0-21.0), DEF(20.0, hint=R4)!, USE(21.0/1, hint=R9)!
[%xmm0]: [20.0-21.0), DEF(20.0, hint=R4)!, USE(21.0/1, hint=R9)
: [21.0-24.0), [26.0-29.0), [31.0-33.0)
: [33.0-33.1), USE(33.1/2)
R9 (d_21) [%xmm1]: [21.0-23.1), DEF(21.0, hint=R8)!, USE(23.1/22.1)!
R10 (d_32) [%xmm1]: [32.0-35.0), DEF(32.0, hint=R4)!, USE(35.0/1, hint=R12)!, USE(35.0/2)
R11 (d_33) [%xmm0]: [33.0-34.0), DEF(33.0, hint=R7)!, USE(34.0/1, hint=R5)!
R12 (d_35) [%xmm1]: [35.0-36.0), DEF(35.0, hint=R10)!, USE(36.0/1, hint=R4)!
R9 (d_21) [%xmm0]: [21.0-23.1), DEF(21.0, hint=R8)!, USE(23.1/22.1)!
R10 (d_32) [%xmm0]: [32.0-35.0), DEF(32.0, hint=R4)!, USE(35.0/1, hint=R12), USE(35.0/2)
R11 (d_33) [%xmm1]: [33.0-34.0), DEF(33.0, hint=R7)!, USE(34.0/1, hint=R5)
R12 (d_35) [%xmm0]: [35.0-36.0), DEF(35.0, hint=R10)!, USE(36.0/1, hint=R4)
[%eax] : [25.0-25.1), [30.0-30.1)
}
test:
@ -148,24 +147,24 @@ test:
xorl %eax, %eax
.L1:
leal 1(%eax), %eax
movsd 0x10(%esp), %xmm0
mulsd %xmm0, %xmm0
movsd 8(%esp), %xmm1
movsd 0x10(%esp), %xmm1
mulsd %xmm1, %xmm1
movsd %xmm1, 0x18(%esp)
addsd %xmm0, %xmm1
ucomisd .L5, %xmm1
movsd 8(%esp), %xmm0
mulsd %xmm0, %xmm0
movsd %xmm0, 0x18(%esp)
addsd %xmm1, %xmm0
ucomisd .L5, %xmm0
ja .L2
cmpl $0x3e8, %eax
jg .L3
movsd 8(%esp), %xmm1
mulsd 0x10(%esp), %xmm1
subsd 0x18(%esp), %xmm0
addsd (%esp), %xmm0
movsd %xmm0, 0x10(%esp)
addsd %xmm1, %xmm1
addsd 0x24(%esp), %xmm1
movsd %xmm1, 8(%esp)
movsd 8(%esp), %xmm0
mulsd 0x10(%esp), %xmm0
subsd 0x18(%esp), %xmm1
addsd (%esp), %xmm1
movsd %xmm1, 0x10(%esp)
addsd %xmm0, %xmm0
addsd 0x24(%esp), %xmm0
movsd %xmm0, 8(%esp)
jmp .L1
.L2:
addl $0x20, %esp

4
tests/debug.x86/swap_001.irt
View File

@ -19,9 +19,9 @@ x86
--EXPECT--
test:
subl $8, %esp
movsd 0x14(%esp), %xmm0
movsd %xmm0, (%esp)
movsd 0xc(%esp), %xmm0
movsd 0x14(%esp), %xmm1
movsd %xmm1, (%esp)
addsd (%esp), %xmm0
movsd %xmm0, (%esp)
addl $8, %esp

4
tests/debug.x86/swap_002.irt
View File

@ -20,9 +20,9 @@ x86
--EXPECT--
test:
subl $4, %esp
movl 0xc(%esp), %eax
movl %eax, (%esp)
movl 8(%esp), %eax
movl 0xc(%esp), %ecx
movl %ecx, (%esp)
andl (%esp), %eax
addl %eax, %eax
movl %eax, (%esp)

4
tests/debug.x86/test.irt
View File

@ -64,9 +64,9 @@ test:
.L1:
leal 1(%eax), %eax
movapd %xmm2, %xmm4
mulsd %xmm2, %xmm4
mulsd %xmm4, %xmm4
movapd %xmm3, %xmm5
mulsd %xmm3, %xmm5
mulsd %xmm5, %xmm5
movapd %xmm5, %xmm6
addsd %xmm4, %xmm6
ucomisd .L5, %xmm6

2
tests/debug/regset-fib.irt
View File

@ -63,7 +63,7 @@ TMP
[%xmm0]: [13.2-13.3)/1
R1 (d_4) [%xmm1]: [3.0-10.1), DEF(4.2), USE(9.1/2), USE(10.1/2)
R2 (d_5, d_9) [SPILL=0x0]
[%xmm0]: [3.0-10.0), DEF(5.2), USE(7.1/6.1)!, USE(9.0/1)!, DEF(9.0)!, USE(10.0/1, hint=%xmm0, hint=R3)!
[%xmm0]: [3.0-10.0), DEF(5.2), USE(7.1/6.1)!, USE(9.0/1), DEF(9.0)!, USE(10.0/1, hint=%xmm0, hint=R3)
: [10.0-14.0), PHI_USE(13.2, phi=d_5/3)
R3 (d_10) [SPILL=0x8]
[%xmm0]: [10.0-11.0), DEF(10.0, hint=R2)!, USE(11.0/4, hint=%xmm0)

2
tests/debug/regset-fib2.irt
View File

@ -63,7 +63,7 @@ TMP
[%xmm0]: [15.2-15.3)/1
R1 (d_4) [%xmm1]: [3.0-10.1), DEF(4.2), USE(9.1/2), USE(10.1/2)
R2 (d_5, d_9) [SPILL=0x0]
[%xmm0]: [3.0-10.0), DEF(5.2), USE(7.1/6.1)!, USE(9.0/1)!, DEF(9.0)!, USE(10.0/1, hint=%xmm0, hint=R3)!
[%xmm0]: [3.0-10.0), DEF(5.2), USE(7.1/6.1)!, USE(9.0/1), DEF(9.0)!, USE(10.0/1, hint=%xmm0, hint=R3)
: [10.0-16.0), PHI_USE(15.2, phi=d_5/3)
R3 (d_10) [SPILL=0x8]
[%xmm0]: [10.0-11.0), DEF(10.0, hint=R2)!, USE(11.0/4, hint=%xmm0)

53
tests/debug/regset-test.irt
View File

@ -110,30 +110,29 @@ R1 (d_2) [SPILL=0x0]
[%xmm0]: [2.3-10.2), DEF(2.3, hint=%xmm0)
: [10.2-24.0), [26.0-29.0), [31.0-36.0)
: [36.0-38.0), USE(36.1/2)
R2 (d_3) [%xmm1]: [3.3-5.0), DEF(3.3, hint=%xmm1), USE(5.0/1, hint=R3)!
R2 (d_3) [%xmm1]: [3.3-5.0), DEF(3.3, hint=%xmm1), USE(5.0/1, hint=R3)
R3 (d_5) [SPILL=0x8]
[%xmm1]: [5.0-10.2), DEF(5.0, hint=R2)!
: [10.2-24.0), [26.0-29.0), [31.0-34.0)
: [34.0-38.0), USE(34.1/2)
R4 (d_12, d_36) [SPILL=0x10]
[%xmm1]: [11.0-20.0), DEF(12.2), USE(20.0/1, hint=R8)!, USE(20.0/2)
: [20.0-24.0), [26.0-29.0), [31.0-31.3)
[%xmm1]: [31.3-32.0), [36.0-38.0), USE(32.0/1)!, DEF(36.0, hint=R12)!, PHI_USE(37.2, phi=d_12/3)
: [11.0-24.0), [26.0-29.0), [31.0-32.0), DEF(12.2), USE(20.0/1, hint=R8), USE(20.0/2), USE(32.0/1)
[%xmm0]: [36.0-38.0), DEF(36.0, hint=R12)!, PHI_USE(37.2, phi=d_12/3)
R5 (d_13, d_34) [SPILL=0x18]
[%xmm0]: [11.0-18.0), DEF(13.2), USE(18.0/1, hint=R7)!, USE(18.0/2)
: [18.0-24.0), [26.0-29.0), [31.0-32.0)
[%xmm0]: [11.0-20.0), DEF(13.2), USE(18.0/1, hint=R7), USE(18.0/2)
: [20.0-24.0), [26.0-29.0), [31.0-32.0)
: [32.0-32.1), USE(32.1/2, hint=R10)
[%xmm0]: [34.0-38.0), DEF(34.0, hint=R11)!, PHI_USE(37.2, phi=d_13/3)
[%xmm1]: [34.0-38.0), DEF(34.0, hint=R11)!, PHI_USE(37.2, phi=d_13/3)
R6 (d_14, d_15) [%eax]: [11.0-15.1), [15.2-25.0), [26.0-29.0), [31.0-38.0), DEF(14.2), USE(15.1/1)!, DEF(15.2)!, USE(25.0/2, hint=%eax), USE(28.1/27.1), PHI_USE(37.2, phi=d_14/3)
R7 (d_18) [%xmm0]: [18.0-24.0), [26.0-29.0), [31.0-33.0), DEF(18.0, hint=R5)!, USE(21.1/2), USE(33.0/1, hint=R11)!
R7 (d_18) [%xmm1]: [18.0-24.0), [26.0-29.0), [31.0-33.0), DEF(18.0, hint=R5)!, USE(21.1/2), USE(33.0/1, hint=R11)
R8 (d_20) [SPILL=0x20]
[%xmm1]: [20.0-21.0), DEF(20.0, hint=R4)!, USE(21.0/1, hint=R9)!
[%xmm0]: [20.0-21.0), DEF(20.0, hint=R4)!, USE(21.0/1, hint=R9)
: [21.0-24.0), [26.0-29.0), [31.0-33.0)
: [33.0-33.1), USE(33.1/2)
R9 (d_21) [%xmm1]: [21.0-23.1), DEF(21.0, hint=R8)!, USE(23.1/22.1)!
R10 (d_32) [%xmm1]: [32.0-35.0), DEF(32.0, hint=R4)!, USE(35.0/1, hint=R12)!, USE(35.0/2)
R11 (d_33) [%xmm0]: [33.0-34.0), DEF(33.0, hint=R7)!, USE(34.0/1, hint=R5)!
R12 (d_35) [%xmm1]: [35.0-36.0), DEF(35.0, hint=R10)!, USE(36.0/1, hint=R4)!
R9 (d_21) [%xmm0]: [21.0-23.1), DEF(21.0, hint=R8)!, USE(23.1/22.1)!
R10 (d_32) [%xmm0]: [32.0-35.0), DEF(32.0, hint=R4)!, USE(35.0/1, hint=R12), USE(35.0/2)
R11 (d_33) [%xmm1]: [33.0-34.0), DEF(33.0, hint=R7)!, USE(34.0/1, hint=R5)
R12 (d_35) [%xmm0]: [35.0-36.0), DEF(35.0, hint=R10)!, USE(36.0/1, hint=R4)
[%rax] : [25.0-25.1), [30.0-30.1)
[%xmm0] : [1.0-2.3)
[%xmm1] : [1.0-3.3)
@ -150,24 +149,24 @@ test:
xorl %eax, %eax
.L1:
leal 1(%rax), %eax
movsd 0x18(%rsp), %xmm0
mulsd %xmm0, %xmm0
movsd 0x10(%rsp), %xmm1
movsd 0x18(%rsp), %xmm1
mulsd %xmm1, %xmm1
movsd %xmm1, 0x20(%rsp)
addsd %xmm0, %xmm1
ucomisd .L5(%rip), %xmm1
movsd 0x10(%rsp), %xmm0
mulsd %xmm0, %xmm0
movsd %xmm0, 0x20(%rsp)
addsd %xmm1, %xmm0
ucomisd .L5(%rip), %xmm0
ja .L2
cmpl $0x3e8, %eax
jg .L3
movsd 0x10(%rsp), %xmm1
mulsd 0x18(%rsp), %xmm1
subsd 0x20(%rsp), %xmm0
addsd 8(%rsp), %xmm0
movsd %xmm0, 0x18(%rsp)
addsd %xmm1, %xmm1
addsd (%rsp), %xmm1
movsd %xmm1, 0x10(%rsp)
movsd 0x10(%rsp), %xmm0
mulsd 0x18(%rsp), %xmm0
subsd 0x20(%rsp), %xmm1
addsd 8(%rsp), %xmm1
movsd %xmm1, 0x18(%rsp)
addsd %xmm0, %xmm0
addsd (%rsp), %xmm0
movsd %xmm0, 0x10(%rsp)
jmp .L1
.L2:
addq $0x28, %rsp

4
tests/debug/test.irt
View File

@ -62,9 +62,9 @@ test:
.L1:
leal 1(%rax), %eax
movapd %xmm2, %xmm4
mulsd %xmm2, %xmm4
mulsd %xmm4, %xmm4
movapd %xmm3, %xmm5
mulsd %xmm3, %xmm5
mulsd %xmm5, %xmm5
movapd %xmm5, %xmm6
addsd %xmm4, %xmm6
ucomisd .L5(%rip), %xmm6

4
tests/debug/test64.irt
View File

@ -62,9 +62,9 @@ test:
.L1:
leaq 1(%rax), %rax
movapd %xmm2, %xmm4
mulsd %xmm2, %xmm4
mulsd %xmm4, %xmm4
movapd %xmm3, %xmm5
mulsd %xmm3, %xmm5
mulsd %xmm5, %xmm5
movapd %xmm5, %xmm6
addsd %xmm4, %xmm6
ucomisd .L5(%rip), %xmm6

3
tests/x86/ra_015.irt
View File

@ -15,10 +15,9 @@ x86
}
--EXPECT--
test:
movl 4(%esp), %ecx
movl 8(%esp), %eax
movl %ecx, %edx
movl %eax, %ecx
movl 4(%esp), %edx
shll %cl, %edx
movl %edx, %ecx
shll %cl, %eax

2
tests/x86/shl_001.irt
View File

@ -14,7 +14,7 @@ x86
}
--EXPECT--
test:
movl 4(%esp), %eax
movl 8(%esp), %ecx
movl 4(%esp), %eax
shll %cl, %eax
retl

2
tests/x86/shl_003.irt
View File

@ -14,7 +14,7 @@ x86
}
--EXPECT--
test:
movl 8(%esp), %eax
movl 4(%esp), %ecx
movl 8(%esp), %eax
shll %cl, %eax
retl

2
tests/x86_64/mul_005.irt
View File

@ -15,5 +15,5 @@ x86_64
--EXPECT--
test:
movw %di, %ax
addw %di, %ax
addw %ax, %ax
retq