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Avoid check for PHI, PI, PARAM and VAR nodes in BB started by a node with a single use-def edge (control edge)
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parent
3f009c2d5a
commit
70da8bef54
42
ir_gcm.c
42
ir_gcm.c
@ -316,28 +316,30 @@ int ir_gcm(ir_ctx *ctx)
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use_list = &ctx->use_lists[ref];
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use_list = &ctx->use_lists[ref];
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n = use_list->count;
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n = use_list->count;
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for (p = &ctx->use_edges[use_list->refs]; n > 0; n--, p++) {
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if (n > 1) {
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ref = *p;
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for (p = &ctx->use_edges[use_list->refs]; n > 0; n--, p++) {
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use_insn = &ctx->ir_base[ref];
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ref = *p;
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if (use_insn->op == IR_PHI || use_insn->op == IR_PI) {
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use_insn = &ctx->ir_base[ref];
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bb->flags |= (use_insn->op == IR_PHI) ? IR_BB_HAS_PHI : IR_BB_HAS_PI;
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if (use_insn->op == IR_PHI || use_insn->op == IR_PI) {
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ir_bitset_incl(visited, ref);
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bb->flags |= (use_insn->op == IR_PHI) ? IR_BB_HAS_PHI : IR_BB_HAS_PI;
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if (EXPECTED(ctx->use_lists[ref].count != 0)) {
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ir_bitset_incl(visited, ref);
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if (EXPECTED(ctx->use_lists[ref].count != 0)) {
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_blocks[ref] = b; /* pin to block */
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ir_list_push_unchecked(&queue_early, ref);
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ir_list_push_unchecked(&queue_late, ref);
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}
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} else if (use_insn->op == IR_PARAM) {
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bb->flags |= IR_BB_HAS_PARAM;
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_blocks[ref] = b; /* pin to block */
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_blocks[ref] = b; /* pin to block */
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ir_list_push_unchecked(&queue_early, ref);
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ir_bitset_incl(visited, ref);
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ir_list_push_unchecked(&queue_late, ref);
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if (EXPECTED(ctx->use_lists[ref].count != 0)) {
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ir_list_push_unchecked(&queue_late, ref);
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}
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} else if (use_insn->op == IR_VAR) {
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bb->flags |= IR_BB_HAS_VAR;
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_blocks[ref] = b; /* pin to block */
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ir_bitset_incl(visited, ref);
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}
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}
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} else if (use_insn->op == IR_PARAM) {
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bb->flags |= IR_BB_HAS_PARAM;
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_blocks[ref] = b; /* pin to block */
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ir_bitset_incl(visited, ref);
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if (EXPECTED(ctx->use_lists[ref].count != 0)) {
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ir_list_push_unchecked(&queue_late, ref);
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}
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} else if (use_insn->op == IR_VAR) {
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bb->flags |= IR_BB_HAS_VAR;
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_blocks[ref] = b; /* pin to block */
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ir_bitset_incl(visited, ref);
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}
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}
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}
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}
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}
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}
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