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Fix incorrect spill load inside a fuse load

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This commit is contained in:
Dmitry Stogov 2022-12-06 23:37:10 +03:00
parent 0f9d525157
commit 83d3480391
1 changed files with 6 additions and 6 deletions
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12
ir_x86.dasc
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@ -3587,11 +3587,11 @@ static void ir_emit_cmp_int(ir_ctx *ctx, ir_ref def, ir_insn *insn)
ir_reg op2_reg = ctx->regs[def][2]; ir_reg op2_reg = ctx->regs[def][2];
IR_ASSERT(def_reg != IR_REG_NONE); IR_ASSERT(def_reg != IR_REG_NONE);
if (op1_reg != IR_REG_NONE && ((op1_reg & IR_REG_SPILL_LOAD) || IR_IS_CONST_REF(op1))) { if (op1_reg != IR_REG_NONE && (IR_IS_CONST_REF(op1) || ((op1_reg & IR_REG_SPILL_LOAD) && ir_rule(ctx, op1) != IR_SKIP_MEM))) {
op1_reg &= ~IR_REG_SPILL_LOAD; op1_reg &= ~IR_REG_SPILL_LOAD;
ir_emit_load(ctx, type, op1_reg, op1); ir_emit_load(ctx, type, op1_reg, op1);
} }
if (op2_reg != IR_REG_NONE && ((op2_reg & IR_REG_SPILL_LOAD) || IR_IS_CONST_REF(op2))) { if (op2_reg != IR_REG_NONE && (IR_IS_CONST_REF(op2) || ((op2_reg & IR_REG_SPILL_LOAD) && ir_rule(ctx, op2) != IR_SKIP_MEM))) {
op2_reg &= ~IR_REG_SPILL_LOAD; op2_reg &= ~IR_REG_SPILL_LOAD;
if (op1 != op2) { if (op1 != op2) {
ir_emit_load(ctx, type, op2_reg, op2); ir_emit_load(ctx, type, op2_reg, op2);
@ -4005,11 +4005,11 @@ static void ir_emit_cmp_and_branch_int(ir_ctx *ctx, uint32_t b, ir_ref def, ir_i
ir_reg op1_reg = ctx->regs[insn->op2][1]; ir_reg op1_reg = ctx->regs[insn->op2][1];
ir_reg op2_reg = ctx->regs[insn->op2][2]; ir_reg op2_reg = ctx->regs[insn->op2][2];
if (op1_reg != IR_REG_NONE && ((op1_reg & IR_REG_SPILL_LOAD) || IR_IS_CONST_REF(op1))) { if (op1_reg != IR_REG_NONE && (IR_IS_CONST_REF(op1) || ((op1_reg & IR_REG_SPILL_LOAD) && ir_rule(ctx, op1) != IR_SKIP_MEM))) {
op1_reg &= ~IR_REG_SPILL_LOAD; op1_reg &= ~IR_REG_SPILL_LOAD;
ir_emit_load(ctx, type, op1_reg, op1); ir_emit_load(ctx, type, op1_reg, op1);
} }
if (op2_reg != IR_REG_NONE && ((op2_reg & IR_REG_SPILL_LOAD) || IR_IS_CONST_REF(op2))) { if (op2_reg != IR_REG_NONE && (IR_IS_CONST_REF(op2) || ((op2_reg & IR_REG_SPILL_LOAD) && ir_rule(ctx, op2) != IR_SKIP_MEM))) {
op2_reg &= ~IR_REG_SPILL_LOAD; op2_reg &= ~IR_REG_SPILL_LOAD;
if (op1 != op2) { if (op1 != op2) {
ir_emit_load(ctx, type, op2_reg, op2); ir_emit_load(ctx, type, op2_reg, op2);
@ -6206,11 +6206,11 @@ static void ir_emit_guard_cmp_int(ir_ctx *ctx, uint32_t b, ir_ref def, ir_insn *
ir_reg op2_reg = ctx->regs[insn->op2][2]; ir_reg op2_reg = ctx->regs[insn->op2][2];
void *addr; void *addr;
if (op1_reg != IR_REG_NONE && ((op1_reg & IR_REG_SPILL_LOAD) || IR_IS_CONST_REF(op1))) { if (op1_reg != IR_REG_NONE && (IR_IS_CONST_REF(op1) || ((op1_reg & IR_REG_SPILL_LOAD) && ir_rule(ctx, op1) != IR_SKIP_MEM))) {
op1_reg &= ~IR_REG_SPILL_LOAD; op1_reg &= ~IR_REG_SPILL_LOAD;
ir_emit_load(ctx, type, op1_reg, op1); ir_emit_load(ctx, type, op1_reg, op1);
} }
if (op2_reg != IR_REG_NONE && ((op2_reg & IR_REG_SPILL_LOAD) || IR_IS_CONST_REF(op2))) { if (op2_reg != IR_REG_NONE && (IR_IS_CONST_REF(op2) || ((op2_reg & IR_REG_SPILL_LOAD) && ir_rule(ctx, op2) != IR_SKIP_MEM))) {
op2_reg &= ~IR_REG_SPILL_LOAD; op2_reg &= ~IR_REG_SPILL_LOAD;
if (op1 != op2) { if (op1 != op2) {
ir_emit_load(ctx, type, op2_reg, op2); ir_emit_load(ctx, type, op2_reg, op2);