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Dmitry Stogov 2022-05-13 09:06:43 +03:00
parent cd6eb1354a
commit 8895b18c0c
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TODO
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@ -64,6 +64,7 @@
+ temporary register for swap (dessa3.ir)
+ temporary register for spill loads and stores
- temporary register for swap during parallel parameter pssing
- IR_CMP_AND_BRANCH_FP invalid position of tmp variables (fib.ir)
- stack arguments and parameters
- return merge/split
? binary code emission without DynAsm