From a1366ebd9229ec312d8cad8e912950be44d23f81 Mon Sep 17 00:00:00 2001
From: Dmitry Stogov <dmitry@zend.com>
Date: Tue, 19 Apr 2022 14:18:39 +0300
Subject: [PATCH] Use zero-extended load if possible

---
 TODO        | 3 ---
 ir_x86.dasc | 8 ++++++--
 2 files changed, 6 insertions(+), 5 deletions(-)

diff --git a/TODO b/TODO
index b95855f..13f992c 100644
--- a/TODO
+++ b/TODO
@@ -29,9 +29,6 @@
 	- xor, btsl=INCL, btrl=EXCL, btl=IN, bsr, maxss, maxsd, minss, minsd
     - MOVZX to avoid a SHIFT and AND instruction
     - Using CMOVcc to remove branches
-    - mov rax, 123456789abcdef0h ; 10 bytes (64-bit constant)
-    - mov rax, -100 ; 7 bytes (32-bit sign-extended)
-    - mov eax, 100 ; 5 bytes (32-bit zero-extended)
 
 ?  register allocation
 	+  linear scan
diff --git a/ir_x86.dasc b/ir_x86.dasc
index d827592..57fd491 100644
--- a/ir_x86.dasc
+++ b/ir_x86.dasc
@@ -187,11 +187,15 @@
 |			lea Ra(dst), aword [=>label]
 ||			_insn->emit_const = 1;
 ||		} else if (ir_type_size[type] == 8 && !IR_IS_SIGNED_32BIT(_insn->val.i64)) {
-|			mov64 Ra(dst), _insn->val.i64
+||			if (IR_IS_UNSIGNED_32BIT(_insn->val.u64)) {
+|				mov Rd(dst), _insn->val.u32 // zero extended load
+||          } else {
+|				mov64 Ra(dst), _insn->val.i64
+||			}
 ||		} else if (_insn->val.i64 == 0) {
 |			ASM_REG_REG_OP xor, type, dst, dst
 ||		} else {
-|			ASM_REG_IMM_OP mov, type, dst, _insn->val.i32
+|			ASM_REG_IMM_OP mov, type, dst, _insn->val.i32 // sign extended load
 ||		}
 ||	} else {
 ||		ir_reg _reg = ir_ref_reg(ctx, src);