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RLOAD and VAR don't have inputs
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parent
3471060709
commit
baa9f44ca2
8
ir_ra.c
8
ir_ra.c
@ -490,6 +490,9 @@ int ir_compute_live_ranges(ir_ctx *ctx)
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IR_START_LIVE_POS_FROM_REF(bb->start), IR_DEF_LIVE_POS_FROM_REF(ref));
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IR_START_LIVE_POS_FROM_REF(bb->start), IR_DEF_LIVE_POS_FROM_REF(ref));
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ctx->live_intervals[ctx->vregs[ref]]->flags = IR_LIVE_INTERVAL_REG_LOAD;
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ctx->live_intervals[ctx->vregs[ref]]->flags = IR_LIVE_INTERVAL_REG_LOAD;
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ctx->live_intervals[ctx->vregs[ref]]->reg = insn->op2;
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ctx->live_intervals[ctx->vregs[ref]]->reg = insn->op2;
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/* live.remove(opd) */
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ir_bitset_excl(live, ctx->vregs[ref]);
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continue;
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} else if (insn->op != IR_PHI) {
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} else if (insn->op != IR_PHI) {
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ir_live_pos def_pos;
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ir_live_pos def_pos;
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ir_ref hint_ref = 0;
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ir_ref hint_ref = 0;
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@ -533,6 +536,8 @@ int ir_compute_live_ranges(ir_ctx *ctx)
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ir_fix_live_range(ctx, ctx->vregs[ref],
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ir_fix_live_range(ctx, ctx->vregs[ref],
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IR_START_LIVE_POS_FROM_REF(bb->start), def_pos);
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IR_START_LIVE_POS_FROM_REF(bb->start), def_pos);
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ir_add_use(ctx, ctx->vregs[ref], 0, def_pos, reg, def_flags, hint_ref);
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ir_add_use(ctx, ctx->vregs[ref], 0, def_pos, reg, def_flags, hint_ref);
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/* live.remove(opd) */
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ir_bitset_excl(live, ctx->vregs[ref]);
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} else {
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} else {
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ir_add_use(ctx, ctx->vregs[ref], 0, IR_DEF_LIVE_POS_FROM_REF(ref), IR_REG_NONE, IR_USE_SHOULD_BE_IN_REG, 0);
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ir_add_use(ctx, ctx->vregs[ref], 0, IR_DEF_LIVE_POS_FROM_REF(ref), IR_REG_NONE, IR_USE_SHOULD_BE_IN_REG, 0);
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/* live.remove(opd) */
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/* live.remove(opd) */
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@ -540,12 +545,11 @@ int ir_compute_live_ranges(ir_ctx *ctx)
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/* PHIs inputs must not be processed */
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/* PHIs inputs must not be processed */
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continue;
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continue;
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}
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}
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/* live.remove(opd) */
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ir_bitset_excl(live, ctx->vregs[ref]);
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} else {
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} else {
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IR_ASSERT(insn->op == IR_VAR);
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IR_ASSERT(insn->op == IR_VAR);
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IR_ASSERT(ctx->use_lists[ref].count > 0);
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IR_ASSERT(ctx->use_lists[ref].count > 0);
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ir_add_local_var(ctx, ctx->vregs[ref], insn->type);
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ir_add_local_var(ctx, ctx->vregs[ref], insn->type);
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continue;
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}
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}
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}
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}
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