From bbfcb3e8c81194d14b1f354a7cf4fce79e2a94a9 Mon Sep 17 00:00:00 2001
From: Dmitry Stogov <dmitry@zend.com>
Date: Thu, 26 Jan 2023 13:20:08 +0300
Subject: [PATCH] Fix register allocation for MUL_OV in a different way

---
 ir_aarch64.dasc | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/ir_aarch64.dasc b/ir_aarch64.dasc
index 223838e..d86937b 100644
--- a/ir_aarch64.dasc
+++ b/ir_aarch64.dasc
@@ -325,7 +325,6 @@ int ir_get_target_constraints(ir_ctx *ctx, ir_ref ref, ir_target_constraints *co
 						}
 						break;
 					case IR_MUL_OV:
-						flags |= IR_DEF_CONFLICTS_WITH_INPUT_REGS;
 						constraints->tmp_regs[n] = IR_TMP_REG(2, insn->type, IR_LOAD_SUB_REF, IR_SAVE_SUB_REF);
 						n++;
 						break;
@@ -1376,8 +1375,8 @@ static void ir_emit_binop_int(ir_ctx *ctx, ir_ref def, ir_insn *insn)
 					if (IR_IS_TYPE_SIGNED(type)) {
 						tmp_reg = ctx->regs[def][3];
 						IR_ASSERT(tmp_reg != IR_REG_NONE);
-						|	mul Rx(def_reg), Rx(op1_reg), Rx(op2_reg)
 						|	smulh Rx(tmp_reg), Rx(op1_reg), Rx(op2_reg)
+						|	mul Rx(def_reg), Rx(op1_reg), Rx(op2_reg)
 						|	cmp Rx(tmp_reg), Rx(def_reg), asr #63
 					} else {
 						tmp_reg = ctx->regs[def][3];