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Set ir_ctx.prev_ref[] elements for inner BB traversing
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@ -270,11 +270,11 @@ int ir_match(ir_ctx *ctx)
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if (!ctx->prev_ref) {
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if (!ctx->prev_ref) {
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ctx->prev_ref = ir_mem_malloc(ctx->insns_count * sizeof(ir_ref));
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ctx->prev_ref = ir_mem_malloc(ctx->insns_count * sizeof(ir_ref));
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prev = 0;
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for (b = 1, bb = ctx->cfg_blocks + b; b <= ctx->cfg_blocks_count; b++, bb++) {
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for (b = 1, bb = ctx->cfg_blocks + b; b <= ctx->cfg_blocks_count; b++, bb++) {
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if (bb->flags & IR_BB_UNREACHABLE) {
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if (bb->flags & IR_BB_UNREACHABLE) {
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continue;
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continue;
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}
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}
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prev = 0;
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for (i = bb->start, insn = ctx->ir_base + i; i < bb->end;) {
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for (i = bb->start, insn = ctx->ir_base + i; i < bb->end;) {
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ctx->prev_ref[i] = prev;
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ctx->prev_ref[i] = prev;
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n = ir_operands_count(ctx, insn);
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n = ir_operands_count(ctx, insn);
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3
ir_ra.c
3
ir_ra.c
@ -57,6 +57,7 @@ int ir_assign_virtual_registers(ir_ctx *ctx)
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}
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}
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vregs = ir_mem_calloc(ctx->insns_count, sizeof(ir_ref));
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vregs = ir_mem_calloc(ctx->insns_count, sizeof(ir_ref));
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n = 1;
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n = 1;
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prev = 0;
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for (b = 1, bb = ctx->cfg_blocks + b; b <= ctx->cfg_blocks_count; b++, bb++) {
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for (b = 1, bb = ctx->cfg_blocks + b; b <= ctx->cfg_blocks_count; b++, bb++) {
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if (bb->flags & IR_BB_UNREACHABLE) {
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if (bb->flags & IR_BB_UNREACHABLE) {
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continue;
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continue;
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@ -65,7 +66,7 @@ int ir_assign_virtual_registers(ir_ctx *ctx)
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/* skip first instruction */
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/* skip first instruction */
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insn = ctx->ir_base + i;
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insn = ctx->ir_base + i;
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ctx->prev_ref[i] = 0;
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ctx->prev_ref[i] = prev;
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prev = i;
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prev = i;
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n = ir_operands_count(ctx, insn);
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n = ir_operands_count(ctx, insn);
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n = 1 + (n >> 2); // support for multi-word instructions like MERGE and PHI
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n = 1 + (n >> 2); // support for multi-word instructions like MERGE and PHI
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