mirror of
https://github.com/danog/ir.git
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Swap operands for better load fusion
This commit is contained in:
Dmitry Stogov
parent
58063dd470
commit
bf369d0eac
1
TODO
1
TODO
@ -39,7 +39,6 @@
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- OVERFLOW
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- MIN, MAX, COND
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- CAST
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? operands swap (binop_int, binop_sse, binop_avx, cmp_int, cmp_fp, cmp_br_int)
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- return merge/split
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? binary code emission without DynAsm
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- 32-bit x86 code
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54
ir_x86.dasc
54
ir_x86.dasc
@ -1161,11 +1161,45 @@ static uint32_t ir_match_insn(ir_ctx *ctx, ir_ref ref, ir_block *bb)
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}
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return IR_LEA_IB; // lea ret, [op1.reg+op2.reg]
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}
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binop_int:
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if ((ctx->flags & IR_OPT_CODEGEN)
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&& (ir_op_flags[insn->op] & IR_OP_FLAG_COMMUTATIVE)
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&& !IR_IS_CONST_REF(insn->op2)
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&& !IR_IS_CONST_REF(insn->op1)) {
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ir_insn *op1_insn = &ctx->ir_base[insn->op1];
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ir_insn *op2_insn = &ctx->ir_base[insn->op2];
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if ((op1_insn->op == IR_VLOAD || op1_insn->op == IR_LOAD)
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&& (op2_insn->op != IR_VLOAD && op2_insn->op != IR_LOAD)) {
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/* swap for better load fusion */
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ir_ref tmp = insn->op1;
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insn->op1 = insn->op2;
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insn->op2 = tmp;
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}
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}
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return IR_BINOP_INT;
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} else if (ctx->flags & IR_AVX) {
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return IR_BINOP_AVX;
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} else {
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return IR_BINOP_SSE2;
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binop_fp:
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if ((ctx->flags & IR_OPT_CODEGEN)
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&& (ir_op_flags[insn->op] & IR_OP_FLAG_COMMUTATIVE)
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&& !IR_IS_CONST_REF(insn->op2)
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&& !IR_IS_CONST_REF(insn->op1)) {
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ir_insn *op1_insn = &ctx->ir_base[insn->op1];
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ir_insn *op2_insn = &ctx->ir_base[insn->op2];
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if ((op1_insn->op == IR_VLOAD || op1_insn->op == IR_LOAD)
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&& (op2_insn->op != IR_VLOAD && op2_insn->op != IR_LOAD)) {
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/* swap for better load fusion */
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ir_ref tmp = insn->op1;
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insn->op1 = insn->op2;
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insn->op2 = tmp;
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}
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}
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if (ctx->flags & IR_AVX) {
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return IR_BINOP_AVX;
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} else {
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return IR_BINOP_SSE2;
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}
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}
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break;
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case IR_MUL:
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@ -1191,10 +1225,8 @@ static uint32_t ir_match_insn(ir_ctx *ctx, ir_ref ref, ir_block *bb)
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}
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}
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return (IR_IS_TYPE_SIGNED(insn->type) && ir_type_size[insn->type] != 1) ? IR_BINOP_INT : IR_MUL_INT;
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} else if (ctx->flags & IR_AVX) {
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return IR_BINOP_AVX;
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} else {
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return IR_BINOP_SSE2;
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goto binop_fp;
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}
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break;
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case IR_DIV:
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@ -1210,10 +1242,8 @@ static uint32_t ir_match_insn(ir_ctx *ctx, ir_ref ref, ir_block *bb)
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}
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}
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return IR_DIV_INT;
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} else if (ctx->flags & IR_AVX) {
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return IR_BINOP_AVX;
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} else {
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return IR_BINOP_SSE2;
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goto binop_fp;
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}
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break;
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case IR_MOD:
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@ -1268,7 +1298,7 @@ static uint32_t ir_match_insn(ir_ctx *ctx, ir_ref ref, ir_block *bb)
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// -1
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}
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}
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return IR_BINOP_INT;
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goto binop_int;
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case IR_AND:
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if ((ctx->flags & IR_OPT_CODEGEN) && IR_IS_CONST_REF(insn->op2)) {
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op2_insn = &ctx->ir_base[insn->op2];
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@ -1280,7 +1310,7 @@ static uint32_t ir_match_insn(ir_ctx *ctx, ir_ref ref, ir_block *bb)
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return IR_COPY_INT;
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}
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}
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return IR_BINOP_INT;
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goto binop_int;
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case IR_XOR:
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if ((ctx->flags & IR_OPT_CODEGEN) && IR_IS_CONST_REF(insn->op2)) {
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op2_insn = &ctx->ir_base[insn->op2];
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@ -1288,7 +1318,7 @@ static uint32_t ir_match_insn(ir_ctx *ctx, ir_ref ref, ir_block *bb)
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// const
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}
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}
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return IR_BINOP_INT;
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goto binop_int;
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case IR_SHL:
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if (IR_IS_CONST_REF(insn->op2)) {
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if (ctx->flags & IR_OPT_CODEGEN) {
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45
tests/debug/params_003.irt
Normal file
45
tests/debug/params_003.irt
Normal file
@ -0,0 +1,45 @@
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--TEST--
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003: Parameter Loading and argument passing
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--ARGS--
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-S
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--CODE--
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{
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uintptr_t f = func(printf);
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uintptr_t fmt = "%d %d %d %d %d %d %d %d %d %d\n";
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l_1 = START(l_3);
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int32_t p_1 = PARAM(l_1, "p_1", 1);
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int32_t p_2 = PARAM(l_1, "p_2", 2);
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int32_t p_3 = PARAM(l_1, "p_3", 3);
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int32_t p_4 = PARAM(l_1, "p_4", 4);
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int32_t p_5 = PARAM(l_1, "p_5", 5);
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int32_t p_6 = PARAM(l_1, "p_6", 6);
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int32_t p_7 = PARAM(l_1, "p_7", 7);
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int32_t p_8 = PARAM(l_1, "p_8", 8);
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int32_t p_9 = PARAM(l_1, "p_9", 9);
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int32_t p_10 = PARAM(l_1, "p_10", 10);
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int32_t ret, l_2 = CALL/11(l_1, f, fmt, p_1, p_2, p_3, p_4, p_5, p_6, p_7, p_8, p_9, p_10);
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l_3 = RETURN(l_2, ret);
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}
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--EXPECT--
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test:
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subq $0x28, %rsp
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movl %r9d, %eax
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movl %eax, (%rsp)
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movl 0x30(%rsp), %r10d
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movl %r10d, 8(%rsp)
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movl 0x38(%rsp), %r10d
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movl %r10d, 0x10(%rsp)
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movl 0x40(%rsp), %r10d
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movl %r10d, 0x18(%rsp)
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movl 0x48(%rsp), %r10d
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movl %r10d, 0x20(%rsp)
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movl %r8d, %r9d
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movl %ecx, %r8d
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movl %edx, %ecx
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movl %esi, %edx
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movl %edi, %esi
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leaq 0x13(%rip), %rdi
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movabsq $_IO_printf, %rax
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callq *%rax
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addq $0x28, %rsp
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retq
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@ -1,5 +1,5 @@
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--TEST--
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Swap operands of commutative instruction
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001: Swap operands of commutative instruction
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--ARGS--
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-S
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--CODE--
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26
tests/debug/swap_002.irt
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26
tests/debug/swap_002.irt
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@ -0,0 +1,26 @@
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--TEST--
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002: Swap operands of commutative instruction
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--ARGS--
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-S
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--CODE--
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{
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l_1 = START(l_5);
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int32_t x = PARAM(l_1, "x", 1);
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int32_t y = PARAM(l_1, "y", 2);
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int32_t v = VAR(l_1, "_spill_");
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l_2 = VSTORE(l_1, v, y);
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int32_t z, l_3 = VLOAD(l_2, v);
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int32_t ret = AND(z, x);
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int32_t ret2 = ADD(ret, ret);
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l_4 = VSTORE(l_3, v, ret2);
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l_5 = RETURN(l_4);
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}
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--EXPECT--
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test:
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subq $8, %rsp
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movl %esi, (%rsp)
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andl (%rsp), %edi
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leal (%rdi, %rdi), %eax
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movl %eax, (%rsp)
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addq $8, %rsp
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retq
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@ -81,7 +81,7 @@ test:
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pushq %rbp
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movq %rsp, %rbp
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subq $0x38, %rsp
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subsd 0xc0(%rip), %xmm1
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subsd 0xb8(%rip), %xmm1
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movsd %xmm1, -0x38(%rbp)
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movsd %xmm0, -0x30(%rbp)
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xorpd %xmm0, %xmm0
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@ -106,14 +106,12 @@ test:
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movsd %xmm1, -8(%rbp)
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movsd -0x10(%rbp), %xmm0
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subsd -8(%rbp), %xmm0
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movsd -0x38(%rbp), %xmm1
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addsd %xmm0, %xmm1
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movsd %xmm1, -0x20(%rbp)
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addsd -0x38(%rbp), %xmm0
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movsd %xmm0, -0x20(%rbp)
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movsd -0x18(%rbp), %xmm0
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addsd %xmm0, %xmm0
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movsd -0x30(%rbp), %xmm1
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addsd %xmm0, %xmm1
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movsd %xmm1, -0x28(%rbp)
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addsd -0x30(%rbp), %xmm0
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movsd %xmm0, -0x28(%rbp)
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movsd -0x10(%rbp), %xmm0
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addsd -8(%rbp), %xmm0
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ucomisd 0x2e(%rip), %xmm0
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@ -74,7 +74,7 @@ Mandelbrot Test (var)
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--EXPECT--
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test:
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subq $0x40, %rsp
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subsd 0xcc(%rip), %xmm1
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subsd 0xc4(%rip), %xmm1
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movsd %xmm1, (%rsp)
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movsd %xmm0, 8(%rsp)
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xorpd %xmm0, %xmm0
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@ -97,14 +97,12 @@ test:
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movsd %xmm1, 0x38(%rsp)
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movsd 0x30(%rsp), %xmm0
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subsd 0x38(%rsp), %xmm0
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movsd (%rsp), %xmm1
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addsd %xmm0, %xmm1
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movsd %xmm1, 0x18(%rsp)
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addsd (%rsp), %xmm0
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movsd %xmm0, 0x18(%rsp)
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movsd 0x28(%rsp), %xmm0
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addsd %xmm0, %xmm0
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movsd 8(%rsp), %xmm1
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addsd %xmm0, %xmm1
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movsd %xmm1, 0x10(%rsp)
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addsd 8(%rsp), %xmm0
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movsd %xmm0, 0x10(%rsp)
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movsd 0x30(%rsp), %xmm0
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addsd 0x38(%rsp), %xmm0
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ucomisd 0x2b(%rip), %xmm0
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