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Reduce number of useless spill loads

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This commit is contained in:
Dmitry Stogov 2023-09-12 23:32:25 +03:00
parent 7650500a7c
commit d032f87b4d
1 changed files with 6 additions and 2 deletions
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8
ir_ra.c
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@ -3653,7 +3653,7 @@ static void assign_regs(ir_ctx *ctx)
ir_ref i; ir_ref i;
ir_live_interval *ival, *top_ival; ir_live_interval *ival, *top_ival;
ir_use_pos *use_pos; ir_use_pos *use_pos;
int8_t reg; int8_t reg, old_reg;
ir_ref ref; ir_ref ref;
ir_regset used_regs = 0; ir_regset used_regs = 0;
@ -3778,7 +3778,10 @@ static void assign_regs(ir_ctx *ctx)
/* Spilled PHI var is passed through memory */ /* Spilled PHI var is passed through memory */
reg = IR_REG_NONE; reg = IR_REG_NONE;
} }
} else if (use_pos->hint_ref < 0) { } else if (use_pos->hint_ref < 0
&& ctx->use_lists[-use_pos->hint_ref].count > 1
&& (old_reg = ir_get_alocated_reg(ctx, -use_pos->hint_ref, use_pos->op_num)) != IR_REG_NONE
&& (old_reg & (IR_REG_SPILL_SPECIAL|IR_REG_SPILL_LOAD))) {
/* Force spill load */ /* Force spill load */
// TODO: Find a better solution ??? // TODO: Find a better solution ???
if (top_ival->flags & IR_LIVE_INTERVAL_SPILL_SPECIAL) { if (top_ival->flags & IR_LIVE_INTERVAL_SPILL_SPECIAL) {
@ -3786,6 +3789,7 @@ static void assign_regs(ir_ctx *ctx)
} else { } else {
reg |= IR_REG_SPILL_LOAD; reg |= IR_REG_SPILL_LOAD;
} }
IR_ASSERT(reg == old_reg);
} else { } else {
/* reuse register without spill load */ /* reuse register without spill load */
} }