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Merge pull request #21 from weltling/cpuid
[RFC] cpu: Add framework for CPU feature handling
This commit is contained in:
commit
d26099c5ac
3
Makefile
3
Makefile
@ -41,7 +41,8 @@ endif
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OBJS_COMMON = $(BUILD_DIR)/ir.o $(BUILD_DIR)/ir_strtab.o $(BUILD_DIR)/ir_cfg.o \
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$(BUILD_DIR)/ir_sccp.o $(BUILD_DIR)/ir_gcm.o $(BUILD_DIR)/ir_ra.o $(BUILD_DIR)/ir_emit.o \
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$(BUILD_DIR)/ir_load.o $(BUILD_DIR)/ir_save.o $(BUILD_DIR)/ir_emit_c.o $(BUILD_DIR)/ir_dump.o \
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$(BUILD_DIR)/ir_disasm.o $(BUILD_DIR)/ir_gdb.o $(BUILD_DIR)/ir_perf.o $(BUILD_DIR)/ir_check.o
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$(BUILD_DIR)/ir_disasm.o $(BUILD_DIR)/ir_gdb.o $(BUILD_DIR)/ir_perf.o $(BUILD_DIR)/ir_check.o \
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$(BUILD_DIR)/ir_cpuinfo.o
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OBJS_IR = $(BUILD_DIR)/ir_main.o
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OBJS_IR_TEST = $(BUILD_DIR)/ir_test.o
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2
ir.h
2
ir.h
@ -768,6 +768,8 @@ int ir_mem_protect(void *ptr, size_t size);
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int ir_mem_unprotect(void *ptr, size_t size);
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int ir_mem_flush(void *ptr, size_t size);
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uint32_t ir_cpuinfo(void);
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#ifdef __cplusplus
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} /* extern "C" */
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#endif
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61
ir_cpuinfo.c
Normal file
61
ir_cpuinfo.c
Normal file
@ -0,0 +1,61 @@
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/*
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* IR - Lightweight JIT Compilation Framework
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* (CPU framework for x86)
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* Copyright (C) 2023 by IR project.
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* Authors: Anatol Belski <anbelski@linux.microsoft.com>
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*/
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#include "ir.h"
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#if defined(IR_TARGET_X86) || defined(IR_TARGET_X64)
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#include "ir_x86.h"
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#ifndef _WIN32
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IR_ALWAYS_INLINE void ir_cpuid_ex(uint32_t info[4], uint32_t function, uint32_t index)
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{
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asm volatile("cpuid"
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: "=a" (info[0]),
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"=b" (info[1]),
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"=c" (info[2]),
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"=d" (info[3])
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: "0" (function), "2" (index)
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: "memory");
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}
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IR_ALWAYS_INLINE void ir_cpuid(uint32_t info[4], uint32_t function)
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{
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ir_cpuid_ex(info, function, 0);
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}
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#else
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#define ir_cpuid_ex __cpuidex
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#define ir_cpuid __cpuid
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#endif
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/* Intel SDM Vol. 2A */
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uint32_t ir_cpuinfo(void)
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{
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uint32_t ret = 0;
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uint32_t info_0x1[4] = {0}, info_0x7_0[4] = {0};
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#define bit(mask, pos) (((mask) >> (pos)) & 1U)
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ir_cpuid(info_0x1, 0x1);
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if (bit(info_0x1[3], 26U)) ret |= IR_X86_SSE2;
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if (bit(info_0x1[2], 0U)) ret |= IR_X86_SSE3;
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if (bit(info_0x1[2], 9U)) ret |= IR_X86_SSSE3;
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if (bit(info_0x1[2], 19U)) ret |= IR_X86_SSE41;
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if (bit(info_0x1[2], 20U)) ret |= IR_X86_SSE42;
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if (bit(info_0x1[2], 28U)) ret |= IR_X86_AVX;
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ir_cpuid_ex(info_0x7_0, 0x7, 0);
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if (bit(info_0x7_0[1], 5U)) ret |= IR_X86_AVX2;
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#undef bit
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return ret;
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}
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#else
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uint32_t ir_cpuinfo(void)
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{
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return 0;
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}
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#endif /* IR_TARGET_X86 || IR_TARGET_X64 */
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12
ir_test.c
12
ir_test.c
@ -7,6 +7,9 @@
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#include "ir.h"
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#include "ir_builder.h"
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#if defined(IR_TARGET_X86) || defined(IR_TARGET_X64)
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# include "ir_x86.h"
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#endif
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#include <stdlib.h>
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#include <string.h>
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#ifndef _WIN32
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@ -94,6 +97,9 @@ int main(int argc, char **argv)
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int opt_level = 2;
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uint32_t mflags = 0;
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uint64_t debug_regset = 0xffffffffffffffff;
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#if defined(IR_TARGET_X86) || defined(IR_TARGET_X64)
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uint32_t cpuinfo = ir_cpuinfo();
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#endif
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ir_consistency_check();
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@ -109,6 +115,12 @@ int main(int argc, char **argv)
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/* pass */
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}
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} else if (strcmp(argv[i], "-mavx") == 0) {
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#if defined(IR_TARGET_X86) || defined(IR_TARGET_X64)
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if (!(cpuinfo & IR_X86_AVX)) {
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fprintf(stderr, "ERROR: CPU doesn't support AVX instruction set)\n");
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return 1;
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}
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#endif
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mflags |= IR_AVX;
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} else if (strcmp(argv[i], "-muse-fp") == 0) {
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mflags |= IR_USE_FRAME_POINTER;
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8
ir_x86.h
8
ir_x86.h
@ -221,4 +221,12 @@ struct _ir_target_constraints {
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int8_t hints[IR_MAX_REG_ARGS + 3];
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};
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#define IR_X86_SSE2 (1<<0)
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#define IR_X86_SSE3 (1<<1)
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#define IR_X86_SSSE3 (1<<2)
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#define IR_X86_SSE41 (1<<3)
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#define IR_X86_SSE42 (1<<4)
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#define IR_X86_AVX (1<<5)
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#define IR_X86_AVX2 (1<<6)
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#endif /* IR_X86_H */
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@ -65,7 +65,7 @@ LIBS=psapi.lib capstone.lib
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OBJS_COMMON=$(BUILD_DIR)\ir.obj $(BUILD_DIR)\ir_strtab.obj $(BUILD_DIR)\ir_cfg.obj \
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$(BUILD_DIR)\ir_sccp.obj $(BUILD_DIR)\ir_gcm.obj $(BUILD_DIR)\ir_ra.obj $(BUILD_DIR)\ir_emit.obj \
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$(BUILD_DIR)\ir_load.obj $(BUILD_DIR)\ir_save.obj $(BUILD_DIR)\ir_emit_c.obj $(BUILD_DIR)\ir_dump.obj \
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$(BUILD_DIR)\ir_disasm.obj $(BUILD_DIR)\ir_check.obj
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$(BUILD_DIR)\ir_disasm.obj $(BUILD_DIR)\ir_check.obj $(BUILD_DIR)\ir_cpuinfo.obj
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OBJS_IR = $(BUILD_DIR)\ir_main.obj
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OBJS_IR_TEST = $(BUILD_DIR)\ir_test.obj
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