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Always build ir_ctx.cfg_map during scheduling (it's used for spill code placement)
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parent
19e08d42e9
commit
da9c406cf5
4
ir_gcm.c
4
ir_gcm.c
@ -746,9 +746,7 @@ restart:
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ir_mem_free(used);
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#ifndef IR_BITSET_LIVENESS
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new_ctx.cfg_map = ir_mem_calloc(ctx->insns_count, sizeof(uint32_t));
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#endif
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/* Copy instructions and count use edges */
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edges_count = 0;
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@ -758,9 +756,7 @@ restart:
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new_ref = _xlat[i];
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new_insn = &new_ctx.ir_base[new_ref];
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*new_insn = *insn;
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#ifndef IR_BITSET_LIVENESS
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new_ctx.cfg_map[new_ref] = _blocks[i];
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#endif
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n = ir_input_edges_count(ctx, insn);
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for (j = n, p = insn->ops + 1, q = new_insn->ops + 1; j > 0; p++, q++, j--) {
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15
ir_ra.c
15
ir_ra.c
@ -2217,20 +2217,6 @@ static ir_live_pos ir_first_use_pos(ir_live_interval *ival, uint8_t flags)
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static ir_block *ir_block_from_live_pos(ir_ctx *ctx, ir_live_pos pos)
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{
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ir_ref ref = IR_LIVE_POS_TO_REF(pos);
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#ifdef IR_BITSET_LIVENESS
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uint32_t b;
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ir_block *bb;
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// TODO: use binary search or map
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for (b = 1, bb = ctx->cfg_blocks + 1; b <= ctx->cfg_blocks_count; b++, bb++) {
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if (ref >= bb->start && ref <= bb->end) {
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return bb;
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}
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}
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IR_ASSERT(0);
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return NULL;
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#else
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uint32_t b = ctx->cfg_map[ref];
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while (!b) {
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@ -2240,7 +2226,6 @@ static ir_block *ir_block_from_live_pos(ir_ctx *ctx, ir_live_pos pos)
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}
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IR_ASSERT(b <= ctx->cfg_blocks_count);
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return &ctx->cfg_blocks[b];
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#endif
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}
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static ir_live_pos ir_find_optimal_split_position(ir_ctx *ctx, ir_live_interval *ival, ir_live_pos min_pos, ir_live_pos max_pos, bool prefer_max)
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