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Store proper %sp register value
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@ -4230,7 +4230,8 @@ static void ir_emit_exitcall(ir_ctx *ctx, ir_ref def, ir_insn *insn)
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| stp x0, x1, [sp, #-16]!
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| mov Rx(IR_REG_INT_ARG2), sp
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| str Rx(IR_REG_INT_ARG2), [sp, #(31*8)]
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| add Rx(IR_REG_INT_ARG1), Rx(IR_REG_INT_ARG2), #(32*8+32*8)
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| str Rx(IR_REG_INT_ARG1), [sp, #(31*8)]
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| mov Rx(IR_REG_INT_ARG1), Rx(IR_REG_INT_TMP)
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if (IR_IS_CONST_REF(insn->op2)) {
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@ -7210,7 +7210,8 @@ static void ir_emit_exitcall(ir_ctx *ctx, ir_ref def, ir_insn *insn)
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| movsd qword [rsp+16*8+15*8], xmm15
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| mov Ra(IR_REG_INT_ARG2), rsp
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| mov aword [rsp+4*8], Ra(IR_REG_INT_ARG2)
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| lea Ra(IR_REG_INT_ARG1), [rsp+16*8+16*8+16]
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| mov aword [rsp+4*8], Ra(IR_REG_INT_ARG1)
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| mov Ra(IR_REG_INT_ARG1), [rsp+16*8+16*8+8]
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|.if X64WIN
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| sub rsp, 32 /* shadow space */
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@ -7234,7 +7235,8 @@ static void ir_emit_exitcall(ir_ctx *ctx, ir_ref def, ir_insn *insn)
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| movsd qword [esp+8*4+7*8], xmm7
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| mov Ra(IR_REG_INT_FCARG2), esp
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| mov aword [esp+4*4], Ra(IR_REG_INT_FCARG2)
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| lea Ra(IR_REG_INT_FCARG1), [esp+8*4+8*8+16]
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| mov aword [esp+4*4], Ra(IR_REG_INT_FCARG1)
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| mov Ra(IR_REG_INT_FCARG1), [esp+8*4+8*8+12]
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|.endif
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