From f058ecfc935a25a287e7123554f9e8b6a90dcffa Mon Sep 17 00:00:00 2001
From: Dmitry Stogov <dmitry@zend.com>
Date: Tue, 28 Mar 2023 13:40:44 +0300
Subject: [PATCH] Prefer IR_TARGET_* checks instead of system specific macros

---
 ir_disasm.c |  2 +-
 ir_gdb.c    | 20 ++++++++++----------
 ir_patch.c  |  6 +++---
 ir_x86.dasc |  8 ++++----
 ir_x86.h    | 12 ++++++++----
 5 files changed, 26 insertions(+), 22 deletions(-)

diff --git a/ir_disasm.c b/ir_disasm.c
index 54afb02..0e16dba 100644
--- a/ir_disasm.c
+++ b/ir_disasm.c
@@ -341,7 +341,7 @@ int ir_disasm(const char    *name,
 	cs_err ret;
 
 # if defined(IR_TARGET_X86) || defined(IR_TARGET_X64)
-#  if defined(__x86_64__) || defined(_WIN64)
+#  ifdef IR_TARGET_X64
 	ret = cs_open(CS_ARCH_X86, CS_MODE_64, &cs);
 	if (ret != CS_ERR_OK) {
 		fprintf(stderr, "cs_open(CS_ARCH_X86, CS_MODE_64, ...) failed; [%d] %s\n", ret, cs_strerror(ret));
diff --git a/ir_gdb.c b/ir_gdb.c
index 7272bc8..bc5b07f 100644
--- a/ir_gdb.c
+++ b/ir_gdb.c
@@ -70,18 +70,18 @@ enum {
 };
 
 enum {
-#if defined(__i386__)
+#if defined(IR_TARGET_X86)
 	DW_REG_AX, DW_REG_CX, DW_REG_DX, DW_REG_BX,
 	DW_REG_SP, DW_REG_BP, DW_REG_SI, DW_REG_DI,
 	DW_REG_RA,
-#elif defined(__x86_64__)
+#elif defined(IR_TARGET_X64)
 	/* Yes, the order is strange, but correct. */
 	DW_REG_AX, DW_REG_DX, DW_REG_CX, DW_REG_BX,
 	DW_REG_SI, DW_REG_DI, DW_REG_BP, DW_REG_SP,
 	DW_REG_8, DW_REG_9, DW_REG_10, DW_REG_11,
 	DW_REG_12, DW_REG_13, DW_REG_14, DW_REG_15,
 	DW_REG_RA,
-#elif defined(__aarch64__)
+#elif defined(IR_TARGET_AARCH64)
 	DW_REG_SP = 31,
 	DW_REG_RA = 30,
 	DW_REG_X29 = 29,
@@ -148,11 +148,11 @@ static const ir_elf_header ir_elfhdr_template = {
 	.eabiversion = 0,
 	.epad        = { 0, 0, 0, 0, 0, 0, 0 },
 	.type        = 1,
-#if defined(__i386__)
+#if defined(IR_TARGET_X86)
 	.machine     = 3,
-#elif defined(__x86_64__)
+#elif defined(IR_TARGET_X64)
 	.machine     = 62,
-#elif defined(__aarch64__)
+#elif defined(IR_TARGET_AARCH64)
 	.machine     = 183,
 #else
 # error "Unsupported target architecture"
@@ -307,10 +307,10 @@ static void ir_gdbjit_ehframe(ir_gdbjit_ctx *ctx, uint32_t sp_offset, uint32_t s
 		DSV(-(int32_t)sizeof(uintptr_t));              /* Data alignment factor. */
 		DB(DW_REG_RA);                                 /* Return address register. */
 		DB(1); DB(DW_EH_PE_textrel|DW_EH_PE_udata4);   /* Augmentation data. */
-#if defined(__x86_64__) || defined(i386)
+#if defined(IR_TARGET_X86) || defined(IR_TARGET_X64)
 		DB(DW_CFA_def_cfa); DUV(DW_REG_SP); DUV(sizeof(uintptr_t));
 		DB(DW_CFA_offset|DW_REG_RA); DUV(1);
-#elif defined(__aarch64__)
+#elif defined(IR_TARGET_AARCH64)
 		DB(DW_CFA_def_cfa); DUV(DW_REG_SP); DUV(0);
 #endif
 		DALIGNNOP(sizeof(uintptr_t));
@@ -323,7 +323,7 @@ static void ir_gdbjit_ehframe(ir_gdbjit_ctx *ctx, uint32_t sp_offset, uint32_t s
 		DU32(ctx->szmcode);         /* Machine code length. */
 		DB(0);                      /* Augmentation data. */
 		DB(DW_CFA_def_cfa_offset); DUV(sp_offset);
-#if defined(__aarch64__)
+#if defined(IR_TARGET_AARCH64)
 		if (sp_offset) {
 			if (sp_adjustment && sp_adjustment < sp_offset) {
 				DB(DW_CFA_offset|DW_REG_X29); DUV(sp_adjustment / sizeof(uintptr_t));
@@ -336,7 +336,7 @@ static void ir_gdbjit_ehframe(ir_gdbjit_ctx *ctx, uint32_t sp_offset, uint32_t s
 #endif
 		if (sp_adjustment && sp_adjustment > sp_offset) {
 			DB(DW_CFA_advance_loc|1); DB(DW_CFA_def_cfa_offset); DUV(sp_adjustment);
-#if defined(__aarch64__)
+#if defined(IR_TARGET_AARCH64)
 			if (!sp_offset) {
 				DB(DW_CFA_offset|DW_REG_X29); DUV(sp_adjustment / sizeof(uintptr_t));
 				DB(DW_CFA_offset|DW_REG_RA); DUV((sp_adjustment / sizeof(uintptr_t)) - 1);
diff --git a/ir_patch.c b/ir_patch.c
index aacda06..51ee3e4 100644
--- a/ir_patch.c
+++ b/ir_patch.c
@@ -18,7 +18,7 @@ static uint32_t _asm_x86_inslen(const uint8_t* p)
 		0x92,0x92,0x92,0x92,0x52,0x45,0x51,0x51,0x92,0x92,0x92,0x92,0x52,0x45,0x51,0x51,
 		0x92,0x92,0x92,0x92,0x52,0x45,0x10,0x51,0x92,0x92,0x92,0x92,0x52,0x45,0x10,0x51,
 		0x92,0x92,0x92,0x92,0x52,0x45,0x10,0x51,0x92,0x92,0x92,0x92,0x52,0x45,0x10,0x51,
-#if defined(__x86_64__) || defined(_M_X64)
+#ifdef IR_TARGET_X64
 		0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x14,0x14,0x14,0x14,0x14,0x14,0x14,0x14,
 #else
 		0x51,0x51,0x51,0x51,0x51,0x51,0x51,0x51,0x51,0x51,0x51,0x51,0x51,0x51,0x51,0x51,
@@ -28,7 +28,7 @@ static uint32_t _asm_x86_inslen(const uint8_t* p)
 		0x52,0x52,0x52,0x52,0x52,0x52,0x52,0x52,0x52,0x52,0x52,0x52,0x52,0x52,0x52,0x52,
 		0x93,0x86,0x93,0x93,0x92,0x92,0x92,0x92,0x92,0x92,0x92,0x92,0x92,0x92,0x92,0x92,
 		0x51,0x51,0x51,0x51,0x51,0x51,0x51,0x51,0x51,0x51,0x47,0x51,0x51,0x51,0x51,0x51,
-#if defined(__x86_64__) || defined(_M_X64)
+#ifdef IR_TARGET_X64
 		0x59,0x59,0x59,0x59,0x51,0x51,0x51,0x51,0x52,0x45,0x51,0x51,0x51,0x51,0x51,0x51,
 #else
 		0x55,0x55,0x55,0x55,0x51,0x51,0x51,0x51,0x52,0x45,0x51,0x51,0x51,0x51,0x51,0x51,
@@ -89,7 +89,7 @@ static uint32_t _asm_x86_inslen(const uint8_t* p)
 				}
 				goto mrm;
 			case 7: /* VEX c4/c5. */
-#if !defined(__x86_64__) && !defined(_M_X64)
+#ifdef IR_TARGET_X86
 				if (p[1] < 0xc0) {
 					x = 2;
 					goto mrm;
diff --git a/ir_x86.dasc b/ir_x86.dasc
index b2604d1..d650e49 100644
--- a/ir_x86.dasc
+++ b/ir_x86.dasc
@@ -382,7 +382,7 @@ static const int8_t _ir_fp_reg_params[IR_REG_FP_ARGS] = {
 	IR_REG_FP_ARG4,
 };
 
-#elif defined(__x86_64__)
+#elif defined(IR_TARGET_X64)
 
 static const int8_t _ir_int_reg_params[IR_REG_INT_ARGS] = {
 	IR_REG_INT_ARG1,
@@ -4216,7 +4216,7 @@ static void ir_emit_return_void(ir_ctx *ctx)
 
 	ir_emit_epilogue(ctx);
 
-#if !defined(_WIN64) && !defined(__x86_64__)
+#ifdef IR_TARGET_X86
 	if (sizeof(void*) == 4 && (ctx->flags & IR_FASTCALL_FUNC) && data->param_stack_size) {
 		|	ret data->param_stack_size
 		return;
@@ -7289,7 +7289,7 @@ static void ir_emit_load_params(ir_ctx *ctx)
 	const int8_t *fp_reg_params = _ir_fp_reg_params;
 	int32_t stack_offset = 0;
 
-#if !defined(_WIN64) && !defined(__x86_64__)
+#ifdef IR_TARGET_X86
 	if (sizeof(void*) == 4 && (ctx->flags & IR_FASTCALL_FUNC)) {
 		int_reg_params_count = IR_REG_INT_FCARGS;
 		fp_reg_params_count = IR_REG_FP_FCARGS;
@@ -7418,7 +7418,7 @@ static void ir_fix_param_spills(ir_ctx *ctx)
 	int32_t stack_start = 0;
 	int32_t stack_offset = 0;
 
-#if !defined(_WIN64) && !defined(__x86_64__)
+#ifdef IR_TARGET_X86
 	if (sizeof(void*) == 4 && (ctx->flags & IR_FASTCALL_FUNC)) {
 		int_reg_params_count = IR_REG_INT_FCARGS;
 		fp_reg_params_count = IR_REG_FP_FCARGS;
diff --git a/ir_x86.h b/ir_x86.h
index ee642ce..e88d311 100644
--- a/ir_x86.h
+++ b/ir_x86.h
@@ -8,7 +8,7 @@
 #ifndef IR_X86_H
 #define IR_X86_H
 
-#if defined(__x86_64__) || defined(_WIN64)
+#if defined(IR_TARGET_X64)
 # define IR_GP_REGS(_) \
 	_(R0,   rax,   eax,   ax,   al, ah) \
 	_(R1,   rcx,   ecx,   cx,   cl, ch) \
@@ -45,7 +45,7 @@
 	_(XMM14, xmm14) \
 	_(XMM15, xmm15) \
 
-#else
+#elif defined(IR_TARGET_X86)
 
 # define IR_GP_REGS(_) \
 	_(R0,   ___,   eax,   ax,   al, ah) \
@@ -67,6 +67,8 @@
 	_(XMM6,  xmm6) \
 	_(XMM7,  xmm7) \
 
+#else
+# error "Unsupported target architecture"
 #endif
 
 #define IR_GP_REG_ENUM(code, name64, name32, name16, name8, name8h) \
@@ -140,7 +142,7 @@ enum _ir_reg {
 	| IR_REGSET_INTERVAL(IR_REG_R12, IR_REG_R15) \
 	| IR_REGSET_INTERVAL(IR_REG_XMM6, IR_REG_XMM15))
 
-#elif defined(__x86_64__)
+#elif defined(IR_TARGET_X64)
 
 # define IR_REG_INT_RET1 IR_REG_RAX
 # define IR_REG_FP_RET1  IR_REG_XMM0
@@ -174,7 +176,7 @@ enum _ir_reg {
 	| IR_REGSET(IR_REG_RBP) \
 	| IR_REGSET_INTERVAL(IR_REG_R12, IR_REG_R15))
 
-#else
+#elif defined(IR_TARGET_X86)
 
 # define IR_REG_INT_RET1   IR_REG_RAX
 # define IR_REG_INT_RET2   IR_REG_RDX
@@ -197,6 +199,8 @@ enum _ir_reg {
 	| IR_REGSET(IR_REG_RBP) \
 	| IR_REGSET_INTERVAL(IR_REG_RSI, IR_REG_RDI))
 
+#else
+# error "Unsupported target architecture"
 #endif
 
 typedef struct _ir_tmp_reg {