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https://github.com/danog/ir.git
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Added tests for unary integer instructions
This commit is contained in:
Dmitry Stogov
parent
fa7a34c629
commit
f1cc9a4ddb
4
Makefile
4
Makefile
@ -79,4 +79,6 @@ clean:
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minilua ir_$(DASM_ARCH).c \
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ir_fold_hash.h gen_ir_fold_hash \
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ir.dot ir.pdf 2.log \
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b perf.data perf.data.old perf.data.jitted
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b perf.data perf.data.old perf.data.jitted \
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tests/*.diff tests/*.out tests/*.exp tests/*.ir \
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tests/x86_64/*.diff tests/x86_64/*.out tests/x86_64/*.exp tests/x86_64/*.ir
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93
TODO
Normal file
93
TODO
Normal file
@ -0,0 +1,93 @@
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- type casting nodes
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- overflow detection nodes
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- va_arg nodes
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- BSTART, BEND nodes (to free data allocated by ALLOCA)
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- ENTRY node for multy-entry units
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- IJMP
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- guards
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- variable name binding
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- VLOAD, VSTORE -> SSA
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? reassociation folding rules
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- folding engine improvement (one rule for few patterns)
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- irreducable loops detection
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- irreducable loops support
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- range inference and PI node
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- SCCP edge cases
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- Folding after SCCP
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- local scheduling according to data dependencies, register presure and pipeline stalls
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- basic block trace scheduling
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? C code generation
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- VLOAD, VSTORE
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? instruction selection
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- xor, btsl=INCL, btrl=EXCL, btl=IN, bsr, maxss, maxsd, minss, minsd
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- MOVZX to avoid a SHIFT and AND instruction
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- Using CMOVcc to remove branches
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- mov rax, 123456789abcdef0h ; 10 bytes (64-bit constant)
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- mov rax, -100 ; 7 bytes (32-bit sign-extended)
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- mov eax, 100 ; 5 bytes (32-bit zero-extended)
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? register allocation
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+ linear scan
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- separate INT and FP allocation phases
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+ use positions
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? fixed registers constraints
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+ fixed input
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+ fixed output
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+ fixed tmp
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+ fixed intervals for parameters
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- accurate fixed interval construction
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- constraints
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- kill
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- restricted regset
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- temporary registers
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? spills
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+ spill slot allocation ( uniqe for each VREG)
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- uniqe for each VREG
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- SpillRange ???
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- splitting
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- SplitAt
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- splinting
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- spill only at cold path if possible
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? hints
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+ hints for fixed input/outpu registers
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+ hints for parameter nodes
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- hints for call arguments
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- hints propagation
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- hints and low priority
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? code generation
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- POW, NEG (fp), ABS, OVERFLOW, MIN, MAX, COND, TAILCALL, ALLOCA, VLOAD, VSTORE, LOAD, STORE
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- SWITCH
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- ir_last_use
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- 64-bit constant (ir_emit_ref, ir_emit_dssa_move)
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- binop_int $imm, mem
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- commutative insns and swap (binop_int, mul, binop_sse, binop_avx, cmp_int, cmp_fp, cmp_br_int)
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- dessa_move (push, pop)
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- param_move
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- temporary register (e.g. for unsupported immediate operand in mul, div)
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- temporary register for swap (dessa3.ir)
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- temporary register for spill loads and stores
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- parallel parameter loading
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- parallel argument passing
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- return merge/split
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? binary code emission
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+ DynAsm
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- BinAsm
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? disassembler
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- .rodata section and relative data labels
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- modules (functions, data objecs, import, export, prototypes, forward declarations, memory segments, ref data, expr data)
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- C compiler
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- interpreter
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- alias analyzes
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- PHP support
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25
ir_x86.dasc
25
ir_x86.dasc
@ -1071,19 +1071,26 @@ static uint32_t ir_match_insn(ir_ctx *ctx, ir_ref ref, ir_block *bb)
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// case IR_SUB_OV:
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// case IR_MUL_OV:
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// case IR_OVERFLOW:
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case IR_BSWAP:
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case IR_NOT:
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return IR_OP_INT;
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case IR_NEG:
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if (IR_IS_TYPE_INT(insn->type)) {
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return IR_OP_INT;
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} else {
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IR_ASSERT(0); return IR_SKIP; // xorps
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IR_ASSERT(0); return IR_SKIP; // xorpd .LC0(%rip), %xmm0; 0 0x80000000 0 0
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// vxorpd .LC0(%rip), %xmm0, %xmm0
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// xorps .LC0(%rip), %xmm0; 0x80000000 0 0 0
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// vxorps .LC0(%rip), %xmm0, %xmm0
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}
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case IR_ABS:
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if (IR_IS_TYPE_INT(insn->type)) {
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IR_ASSERT(0); return IR_SKIP; // TODO: ???
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IR_ASSERT(0); return IR_SKIP; // movl %edi, %eax; negl %eax; cmovs %edi, %eax
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} else {
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IR_ASSERT(0); return IR_SKIP; // andps
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IR_ASSERT(0); return IR_SKIP; // andpd .LC0(%rip), %xmm0; 0xffffffff 0x7fffffff 0 0
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// vandpd .LC0(%rip), %xmm0, %xmm0
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// andps .LC0(%rip), %xmm0; 0x7fffffff 0 0 0
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// vandps .LC0(%rip), %xmm0, %xmm0
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}
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case IR_OR:
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if (IR_IS_CONST_REF(insn->op2)) {
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@ -1164,7 +1171,6 @@ static uint32_t ir_match_insn(ir_ctx *ctx, ir_ref ref, ir_block *bb)
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return IR_SHIFT_CONST;
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}
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return IR_SHIFT;
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// case IR_BSWAP:
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// case IR_MIN:
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// case IR_MAX:
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// case IR_COND:
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@ -1743,6 +1749,17 @@ void ir_emit_op_int(ir_ctx *ctx, ir_ref def, ir_insn *insn)
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| ASM_REG_OP not, insn->type, reg
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} else if (insn->op == IR_NEG) {
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| ASM_REG_OP neg, insn->type, reg
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} else if (insn->op == IR_BSWAP) {
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switch (ir_type_size[insn->type]) {
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case 4:
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| bswap Rd(reg)
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break;
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case 8:
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| bswap Rq(reg)
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break;
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default:
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IR_ASSERT(0);
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}
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} else {
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IR_ASSERT(0);
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}
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16
tests/x86_64/bswap_001.irt
Normal file
16
tests/x86_64/bswap_001.irt
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@ -0,0 +1,16 @@
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--TEST--
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001: bswap function
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--ARGS--
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-S
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--CODE--
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{
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l_1 = START(l_4);
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int32_t x = PARAM(l_1, "x", 1);
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int32_t ret = BSWAP(x);
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l_4 = RETURN(l_1, ret);
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}
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--EXPECT--
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test:
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movl %edi, %eax
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bswapl %eax
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retq
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16
tests/x86_64/neg_001.irt
Normal file
16
tests/x86_64/neg_001.irt
Normal file
@ -0,0 +1,16 @@
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--TEST--
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001: neg function
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--ARGS--
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-S
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--CODE--
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{
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l_1 = START(l_4);
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int32_t x = PARAM(l_1, "x", 1);
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int32_t ret = NEG(x);
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l_4 = RETURN(l_1, ret);
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}
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--EXPECT--
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test:
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movl %edi, %eax
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negl %eax
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retq
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16
tests/x86_64/not_001.irt
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16
tests/x86_64/not_001.irt
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@ -0,0 +1,16 @@
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--TEST--
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001: nit function
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--ARGS--
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-S
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--CODE--
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{
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l_1 = START(l_4);
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int32_t x = PARAM(l_1, "x", 1);
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int32_t ret = NOT(x);
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l_4 = RETURN(l_1, ret);
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}
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--EXPECT--
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test:
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movl %edi, %eax
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notl %eax
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retq
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