7 Commits

Author	SHA1	Message	Date
Daniil Gentili	bfbbc25062	Fix	2023-06-08 22:28:01 +02:00
Daniil Gentili	b060d1c214	Implement vreg	2023-06-08 21:42:38 +02:00
Daniil Gentili	b7a4ad8b0e	Riscv64 dynasm	2023-06-01 22:04:27 +02:00
Dmitry Stogov	66330273b1	Add "endbr" instruction	2022-10-27 11:13:50 +03:00
Dmitry Stogov	2af3f0569d	Merge last changes from LuaJIT repo	2022-06-02 15:26:58 +03:00
Dmitry Stogov	77e5e4a62c	DynAsm/ARM64: Temporary fix for "LSL Rx(dst), Rd(src), #imm" encoding	2022-06-02 13:40:50 +03:00
Dmitry Stogov	2937993190	Initial import	2022-04-06 00:19:23 +03:00