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168 Commits 2 Branches 0 Tags 3.2 MiB
09cee45fd0
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97 Commits

Author SHA1 Message Date
Dmitry Stogov
09cee45fd0 Fix compilation warnings 2022-05-19 14:40:57 +03:00
Dmitry Stogov
113b76c867 Add support for instructions that modify result directly in memory for LOAD/STORE 2022-05-19 14:04:29 +03:00
Dmitry Stogov
bf369d0eac Swap operands for better load fusion 2022-05-19 13:17:50 +03:00
Dmitry Stogov
c9bb858e50 Fuse loads without register allocation when this makes sense. 
Make oarameters passed through stack to reuse the same stack slot for spilling.
 2022-05-19 10:53:08 +03:00
Dmitry Stogov
b77f722cb9 cleanup 2022-05-19 09:11:51 +03:00
Dmitry Stogov
177e556754 Fix spill slot comparison 2022-05-18 23:44:59 +03:00
Dmitry Stogov
cdd39f22b0 Merge spills for VSTORE with -O0 2022-05-18 23:12:20 +03:00
Dmitry Stogov
c5a24ff734 Add support for instructions that modify result directly in memory 2022-05-18 21:49:08 +03:00
Dmitry Stogov
2507dde1ad Fix stack alignment 2022-05-18 14:42:03 +03:00
Dmitry Stogov
438c7801cf Fix param offset calculation 2022-05-18 14:36:49 +03:00
Dmitry Stogov
96fc0fb520 Allow passing arguments from MEM to MEM 2022-05-18 10:07:48 +03:00
Dmitry Stogov
efd9ab9a83 cleanup 2022-05-18 00:20:02 +03:00
Dmitry Stogov
5319951060 Align stack once 2022-05-17 23:01:37 +03:00
Dmitry Stogov
e794451451 Preallocate call stack 2022-05-17 22:37:13 +03:00
Dmitry Stogov
445dd65c78 Improve argument passing 2022-05-17 17:30:04 +03:00
Dmitry Stogov
4e917faaba Fix stack parameters loading 2022-05-17 15:00:58 +03:00
Dmitry Stogov
da5de8a390 Introduce IR_PREALLOCATED_STACK flag 2022-05-17 13:15:41 +03:00
Dmitry Stogov
1e7059d7e0 Pass arguments through stack in reverse order 2022-05-17 12:34:31 +03:00
Dmitry Stogov
92ba2fb534 Add support for passing arguments throug stack 
This may be improved by preallocating stack area and
better register allocation.
 2022-05-17 11:20:28 +03:00
Dmitry Stogov
55f21706c9 clenup 2022-05-17 09:09:45 +03:00
Dmitry Stogov
106f201171 Fix support for fixed registers in -O0 register allocator 2022-05-17 08:38:45 +03:00
Dmitry Stogov
fd457e3590 Fix -O0 register allocator 2022-05-17 01:47:44 +03:00
Dmitry Stogov
0189eb28d0 Use a kind of "Buddy Allocaor" to pack spill slots of different sizes 2022-05-17 00:17:59 +03:00
Dmitry Stogov
6fb5380906 Take into account spill slot size and alignment 2022-05-16 22:16:29 +03:00
Dmitry Stogov
8496780ece Fix temporary register usage for parralel arguments passing 2022-05-16 15:34:36 +03:00
Dmitry Stogov
f086da2550 Clenaup (remove unnecessary SHIFT case) 2022-05-16 14:36:27 +03:00
Dmitry Stogov
cebcde2143 Only arguments passed on stack must be in regisers (to avoid mem->mem copy) 2022-05-16 10:50:50 +03:00
Dmitry Stogov
a3b597feef Use different interval for registers clobbered by CALL 2022-05-13 15:53:54 +03:00
Dmitry Stogov
896ddb9e77 Flexable scratch register constraints (allow MUL %edx) 2022-05-13 15:10:15 +03:00
Dmitry Stogov
814d2b4b69 Initial support for indirect calls 
incomplete: live ranges should be adjusted
 2022-05-13 14:38:58 +03:00
Dmitry Stogov
f040444746 Fix incorrect temporary registers intervals for IR_CMP_AND_BRANCH_* 2022-05-13 13:16:31 +03:00
Dmitry Stogov
1f673ebfda Better temporary register usage for SSA deconstruction 2022-05-13 00:32:37 +03:00
Dmitry Stogov
cd00ae6099 Allow spill slot fusing when swap operands of fp comparison 2022-05-12 21:58:58 +03:00
Dmitry Stogov
386b140265 Refactor Linear Scan Register Allocator to use linked lists instead of bitsets 
This fixes allocation of several temporary variables for single instruction
 2022-05-12 17:43:08 +03:00
Dmitry Stogov
d3c4844da7 Fix reading behind array range 2022-05-12 10:57:38 +03:00
Dmitry Stogov
f8edcb9762 Fix possible crash 2022-05-11 18:18:28 +03:00
Dmitry Stogov
2580813c48 cleanup 2022-05-06 19:05:39 +03:00
Dmitry Stogov
69b5a852e5 Make DESSA API use "ir_ref" instead of "virtual register number" 
(0 - is still a temporary register)
 2022-05-06 16:19:57 +03:00
Dmitry Stogov
b2033ebaf9 Fixed parallel copy 2022-05-06 13:32:20 +03:00
Dmitry Stogov
b6ce5055e1 Fix register usage in CALL 2022-05-06 13:12:19 +03:00
Dmitry Stogov
2403fa1edc Fix spill loads during argument passing 2022-05-06 12:55:07 +03:00
Dmitry Stogov
b580c926e6 Avoid need for temporary register for parameters loading 2022-05-06 11:27:24 +03:00
Dmitry Stogov
e434c0a8aa Cleanup and add asserion for unimplemented case 2022-05-06 11:10:09 +03:00
Dmitry Stogov
9d51134813 cleanup 2022-05-06 10:37:25 +03:00
Dmitry Stogov
89f320d7b7 Add SWITCH support for temporary registers 2022-05-06 10:00:19 +03:00
Dmitry Stogov
048ff19133 cleanup 2022-05-05 23:43:16 +03:00
Dmitry Stogov
dd5a3a3b72 Add flexible support for temporary registers. 
Get rid of hardcoded temporary registers (incomplete)
 2022-05-05 22:35:39 +03:00
Dmitry Stogov
4f294109e8 Result of PARAM may be stored into a spill slot without register 2022-05-04 09:50:23 +03:00
Dmitry Stogov
a5b676b590 Fix incorrect operands order 2022-05-04 09:11:05 +03:00
Dmitry Stogov
3e6f84eef4 Add "must be in reg" constraint 2022-04-28 14:48:43 +03:00