Dmitry Stogov
09829a9e69
Fixed x86_64 calling convention for vararg functions
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%al is used as a hidden register to specify the number of passed vector registers
2023-09-27 10:23:34 +03:00
Dmitry Stogov
56b0dbccde
Use ir_ctx.mflags for CPU specific code-generation options
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'mflags' and ir_cpuinfo() return value have the same meaning.
2023-04-18 09:54:35 +03:00
Anatol Belski
f8ca41119c
cpu: Add framework for CPU feature handling
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This comes with the initial feature to query CPUID on x86. Supported are
both GCC based build and MSVC builds targeting Windows.
Signed-off-by: Anatol Belski <anbelski@linux.microsoft.com>
2023-04-15 01:08:36 +02:00
Dmitry Stogov
f058ecfc93
Prefer IR_TARGET_* checks instead of system specific macros
2023-03-28 13:40:44 +03:00
Dmitry Stogov
87dbdcea0d
Add necessary compensation loads for bounded nodes when enter into function through OSR entry-point
2023-03-21 13:45:37 +03:00
Dmitry Stogov
5a48805c81
Add support for Windows-64 ABI ("home space")
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Fix parameter passing code to perform sign or zero extension when pass a regiser or a constant
TODO: ARM code maight need similar changes
2023-03-02 13:27:01 +03:00
Dmitry Stogov
6b19fdb94f
Fix WIN64 ABI (floating point non-volatiole registers)
2023-02-28 17:46:42 +03:00
Dmitry Stogov
677c6cb2cb
Move declaration of some register alloation related macros to public API
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Use RLOAD.op3 as a flag to avoid spill store
2023-01-30 16:33:57 +03:00
Dmitry Stogov
3e3746d5cb
Refactor API that expose target CPU register constraints for register allocator
2022-11-17 23:30:35 +03:00
Dmitry Stogov
bac5fc340a
typo
2022-11-08 16:24:53 +03:00
Dmitry Stogov
cc56f12f13
Add LICENSE and copyright notices
2022-11-08 11:32:46 +03:00
Dmitry Stogov
00c300fc9f
Start Aarch64 back-end
2022-05-31 11:22:31 +03:00
Dmitry Stogov
41f3e43cf7
cleanup
2022-05-27 13:18:04 +03:00
Dmitry Stogov
3e1816a71f
Fix register allocation for ABS_INT
2022-05-27 00:11:31 +03:00
Dmitry Stogov
ead2b69fc6
x86_32 backend (incomplete)
2022-05-25 22:00:18 +03:00
Dmitry Stogov
341e3b8083
Initial support for x86_32 backend (incomplete)
2022-05-25 14:58:39 +03:00
Dmitry Stogov
896ddb9e77
Flexable scratch register constraints (allow MUL %edx)
2022-05-13 15:10:15 +03:00
Dmitry Stogov
dd5a3a3b72
Add flexible support for temporary registers.
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Get rid of hardcoded temporary registers (incomplete)
2022-05-05 22:35:39 +03:00
Dmitry Stogov
3e6f84eef4
Add "must be in reg" constraint
2022-04-28 14:48:43 +03:00
Dmitry Stogov
3f6a6aa3ea
Better CPU constraint model and initial support for live interval splitting (incomplete)
2022-04-14 22:40:13 +03:00
Dmitry Stogov
23bd7fb272
Add hints and fixed intrvals for parameters
2022-04-07 14:18:59 +03:00
Dmitry Stogov
5b34386f62
Register Allocator suppor for fixed registers, use positions and register hints (incomplete).
2022-04-07 11:11:57 +03:00
Dmitry Stogov
2937993190
Initial import
2022-04-06 00:19:23 +03:00
