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0b78a322f8
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159 Commits

Author SHA1 Message Date
Dmitry Stogov
0b78a322f8 Cache deleted live ranges in ir_ctx.unused_ranges 2023-04-13 11:42:47 +03:00
Dmitry Stogov
7d395532d9 Simplify ir_assign_virtual_registers() 2023-04-13 03:01:08 +03:00
Dmitry Stogov
f85f5fd2a8 Remove data dependency between TAILCALL and UNREACHABLE 2023-04-13 02:41:28 +03:00
Dmitry Stogov
d71cbd47d5 Disable LICM across an OSR ENTRY if the value can't be restored at OSR ENTRY point 2023-04-07 16:36:27 +03:00
Dmitry Stogov
efa8a83153 Fix spilling code for arguments passed theought stack and change RA to 
prefer reusing the same register for splitted intervals
i#	utils/
 2023-04-06 00:16:49 +03:00
Dmitry Stogov
1e5e9e08ce Re-implement instruction fusion and live-range construction 2023-04-05 19:20:43 +03:00
Dmitry Stogov
ee827ee983 Don't create two DEF UsePos 2023-03-29 17:22:49 +03:00
Dmitry Stogov
2392f546bf Improve merging of sorted lists 2023-03-24 12:42:41 +03:00
Dmitry Stogov
87dbdcea0d Add necessary compensation loads for bounded nodes when enter into function through OSR entry-point 2023-03-21 13:45:37 +03:00
Dmitry Stogov
f5b7065b10 Refactor the ENTRY nodes 
Now all ENTRY nodes have a "fake" input control edge.
Through this edge all of them are dominated by START node.
 2023-03-17 09:02:37 +03:00
Dmitry Stogov
300665700f Adopt IR test engine for Windows (this requires php and diff installed) 2023-03-01 20:31:14 +03:00
Dmitry Stogov
9b34731d16 Fix most MSVC compilation warnings 2023-02-28 02:11:09 +03:00
Anatol Belski
964f5a0191 build: MSVC compatibility 
Signed-off-by: Anatol Belski <ab@php.net>
 2023-02-25 00:04:57 +01:00
Dmitry Stogov
31ea3153f3 Add (commeted) code that could eliminate register move for RSTORE 2023-02-16 17:49:30 +03:00
Dmitry Stogov
c7e2cca534 Add hint to reuse register in ZEXT/SEXT 2023-02-15 18:33:02 +03:00
Dmitry Stogov
0eff9e0516 Registers %r4b - %r7b are not available in 32-bit mode 2023-01-24 15:31:31 +03:00
Dmitry Stogov
32ad3d1052 Use inline functions to avoid false positive address sanitaizer warnings 2023-01-20 15:35:02 +03:00
Dmitry Stogov
3ac58893f2 Fix address sanitizer warnings 2023-01-20 11:30:22 +03:00
Dmitry Stogov
5103c18269 Fix load fusion in combination with depended register spill load 2023-01-19 13:39:29 +03:00
Dmitry Stogov
397ed1696b Split at "max_pos" if "min_bb" is in a deeper loop than "max_bb" 2022-12-29 01:39:24 +03:00
Dmitry Stogov
cc8f3fe987 Fix register allocation for intervals started by RLOAD of non-fixed register. 
These intervals may be split and spilled.
 2022-12-27 22:34:52 +03:00
Dmitry Stogov
862e25d96c Try allocationg another blocked register in case of unresolvable conflicts 2022-12-22 22:09:04 +03:00
Dmitry Stogov
9e54343a62 Fix iteration through loop pre-headers 2022-12-15 23:28:09 +03:00
Dmitry Stogov
5959f5375b Fix missed register allocation for the rest of splitted inactive interval 2022-12-09 15:07:36 +03:00
Dmitry Stogov
6a4e239773 Create a sparate pass to remove unreachableble CFG blocks. 
SCCP pass removes unreachable blocks before CFG construction.
In case of -O0 or -O1 pipeline (without SCCP) it's simpler and faster
to unlink unreachable CFG blocks once, then check for reachability
in almost any compilation pass.
-O2 pipeline (with SCCP) don't need this pass.
 2022-11-29 20:02:07 +03:00
Dmitry Stogov
a137adfdf9 Separate ir_build_prev_refs(). It's necessary only for -O0 pipeline. 2022-11-24 12:55:16 +03:00
Dmitry Stogov
bdb8e6a1da Set ir_ctx.prev_ref[] elements for inner BB traversing 2022-11-23 16:16:08 +03:00
Dmitry Stogov
bce0114bab Traverse instruction backward (it's cheaper) 2022-11-23 15:48:22 +03:00
Dmitry Stogov
dde8309108 Use reference to previous instruction instead of its length 2022-11-18 13:59:49 +03:00
Dmitry Stogov
ae19ad7c79 Eliminate unnecessary loops 2022-11-18 12:47:15 +03:00
Dmitry Stogov
00395f0a23 Cleanup: separate ir_phi_input_number() function 2022-11-18 10:11:16 +03:00
Dmitry Stogov
3e3746d5cb Refactor API that expose target CPU register constraints for register allocator 2022-11-17 23:30:35 +03:00
Dmitry Stogov
baa9f44ca2 RLOAD and VAR don't have inputs 2022-11-16 19:21:52 +03:00
Dmitry Stogov
3471060709 Skip END and LOOP_END 2022-11-16 19:06:09 +03:00
Dmitry Stogov
c0e1216361 Improve ir_assign_virtual_registers() 2022-11-16 18:43:34 +03:00
Dmitry Stogov
ba97919e9e Improve ir_assign_virtual_registers() 2022-11-16 18:09:49 +03:00
Dmitry Stogov
9fc66b37c9 Improve ir_assign_virtual_registers() 2022-11-16 00:40:14 +03:00
Dmitry Stogov
bd80dd4700 ir_compute_live_ranges() micro-optimizations 2022-11-16 00:40:14 +03:00
Dmitry Stogov
f72e6dc388 Avoid bitset clearing and copying 2022-11-16 00:40:14 +03:00
Dmitry Stogov
f72bb45e07 Remove useless condition and keep "visited" bitset only for debug build 2022-11-16 00:40:14 +03:00
Dmitry Stogov
9f777661b5 Improve DESSA 
Instead o clearing a huge array use an additional loop to clear only the necessary entries.
 2022-11-16 00:40:14 +03:00
Dmitry Stogov
7e710d5e91 Speedup coalescing 2022-11-16 00:40:14 +03:00
Dmitry Stogov
c8dc4e9e74 Move ir_input_edges_count(phi) out of the loop, because all PHIs inherit their arity from MERGE/LOOP_BEGIN 2022-11-09 21:54:01 +03:00
Dmitry Stogov
3535fd2fc4 Fix compilation warnings and signed/unsigned mess 2022-11-08 23:09:35 +03:00
Dmitry Stogov
cc73788981 Fix compilation warnings 2022-11-08 18:17:29 +03:00
Dmitry Stogov
cc56f12f13 Add LICENSE and copyright notices 2022-11-08 11:32:46 +03:00
Dmitry Stogov
22385c1528 Allocate and reuse spill slots using simple linear-scan (without holes) 2022-11-02 21:53:05 +03:00
Dmitry Stogov
0a5bb4a571 Better condition 2022-11-02 21:28:56 +03:00
Dmitry Stogov
802ec945ad Reorder conditions for the most common case 2022-11-02 16:27:26 +03:00
Dmitry Stogov
3af9e1a062 Move some common code into ir_emit.c 2022-10-26 22:52:19 +03:00