Dmitry Stogov
0eff9e0516
Registers %r4b - %r7b are not available in 32-bit mode
2023-01-24 15:31:31 +03:00
Dmitry Stogov
32ad3d1052
Use inline functions to avoid false positive address sanitaizer warnings
2023-01-20 15:35:02 +03:00
Dmitry Stogov
3ac58893f2
Fix address sanitizer warnings
2023-01-20 11:30:22 +03:00
Dmitry Stogov
5103c18269
Fix load fusion in combination with depended register spill load
2023-01-19 13:39:29 +03:00
Dmitry Stogov
397ed1696b
Split at "max_pos" if "min_bb" is in a deeper loop than "max_bb"
2022-12-29 01:39:24 +03:00
Dmitry Stogov
cc8f3fe987
Fix register allocation for intervals started by RLOAD of non-fixed register.
...
These intervals may be split and spilled.
2022-12-27 22:34:52 +03:00
Dmitry Stogov
862e25d96c
Try allocationg another blocked register in case of unresolvable conflicts
2022-12-22 22:09:04 +03:00
Dmitry Stogov
9e54343a62
Fix iteration through loop pre-headers
2022-12-15 23:28:09 +03:00
Dmitry Stogov
5959f5375b
Fix missed register allocation for the rest of splitted inactive interval
2022-12-09 15:07:36 +03:00
Dmitry Stogov
6a4e239773
Create a sparate pass to remove unreachableble CFG blocks.
...
SCCP pass removes unreachable blocks before CFG construction.
In case of -O0 or -O1 pipeline (without SCCP) it's simpler and faster
to unlink unreachable CFG blocks once, then check for reachability
in almost any compilation pass.
-O2 pipeline (with SCCP) don't need this pass.
2022-11-29 20:02:07 +03:00
Dmitry Stogov
a137adfdf9
Separate ir_build_prev_refs(). It's necessary only for -O0 pipeline.
2022-11-24 12:55:16 +03:00
Dmitry Stogov
bdb8e6a1da
Set ir_ctx.prev_ref[] elements for inner BB traversing
2022-11-23 16:16:08 +03:00
Dmitry Stogov
bce0114bab
Traverse instruction backward (it's cheaper)
2022-11-23 15:48:22 +03:00
Dmitry Stogov
dde8309108
Use reference to previous instruction instead of its length
2022-11-18 13:59:49 +03:00
Dmitry Stogov
ae19ad7c79
Eliminate unnecessary loops
2022-11-18 12:47:15 +03:00
Dmitry Stogov
00395f0a23
Cleanup: separate ir_phi_input_number() function
2022-11-18 10:11:16 +03:00
Dmitry Stogov
3e3746d5cb
Refactor API that expose target CPU register constraints for register allocator
2022-11-17 23:30:35 +03:00
Dmitry Stogov
baa9f44ca2
RLOAD and VAR don't have inputs
2022-11-16 19:21:52 +03:00
Dmitry Stogov
3471060709
Skip END and LOOP_END
2022-11-16 19:06:09 +03:00
Dmitry Stogov
c0e1216361
Improve ir_assign_virtual_registers()
2022-11-16 18:43:34 +03:00
Dmitry Stogov
ba97919e9e
Improve ir_assign_virtual_registers()
2022-11-16 18:09:49 +03:00
Dmitry Stogov
9fc66b37c9
Improve ir_assign_virtual_registers()
2022-11-16 00:40:14 +03:00
Dmitry Stogov
bd80dd4700
ir_compute_live_ranges() micro-optimizations
2022-11-16 00:40:14 +03:00
Dmitry Stogov
f72e6dc388
Avoid bitset clearing and copying
2022-11-16 00:40:14 +03:00
Dmitry Stogov
f72bb45e07
Remove useless condition and keep "visited" bitset only for debug build
2022-11-16 00:40:14 +03:00
Dmitry Stogov
9f777661b5
Improve DESSA
...
Instead o clearing a huge array use an additional loop to clear only the necessary entries.
2022-11-16 00:40:14 +03:00
Dmitry Stogov
7e710d5e91
Speedup coalescing
2022-11-16 00:40:14 +03:00
Dmitry Stogov
c8dc4e9e74
Move ir_input_edges_count(phi) out of the loop, because all PHIs inherit their arity from MERGE/LOOP_BEGIN
2022-11-09 21:54:01 +03:00
Dmitry Stogov
3535fd2fc4
Fix compilation warnings and signed/unsigned mess
2022-11-08 23:09:35 +03:00
Dmitry Stogov
cc73788981
Fix compilation warnings
2022-11-08 18:17:29 +03:00
Dmitry Stogov
cc56f12f13
Add LICENSE and copyright notices
2022-11-08 11:32:46 +03:00
Dmitry Stogov
22385c1528
Allocate and reuse spill slots using simple linear-scan (without holes)
2022-11-02 21:53:05 +03:00
Dmitry Stogov
0a5bb4a571
Better condition
2022-11-02 21:28:56 +03:00
Dmitry Stogov
802ec945ad
Reorder conditions for the most common case
2022-11-02 16:27:26 +03:00
Dmitry Stogov
3af9e1a062
Move some common code into ir_emit.c
2022-10-26 22:52:19 +03:00
Dmitry Stogov
4b114914dc
Prevent register clobbering
2022-10-25 12:24:05 +03:00
Dmitry Stogov
265ebc1000
Fix two LSRA edge cases
2022-10-24 21:55:59 +03:00
Dmitry Stogov
9f472c1c91
Add support for deoptimization and binding to multiple slots
2022-10-21 17:16:25 +03:00
Dmitry Stogov
22cd9265d3
Check if the register is necessary at all
2022-10-18 22:02:09 +03:00
Dmitry Stogov
3ef58e5c2e
Take into account RLOADs for non fixed registers
2022-10-11 22:23:09 +03:00
Dmitry Stogov
f5c0151740
Remove hints to the same virtual register
2022-10-05 20:31:20 +03:00
Dmitry Stogov
e9402c8436
Add hint for "op1" if result reuses "op1" register.
...
This improves register allocation if regiter for result was coalesced and allocated before the register for operand.
2022-10-05 17:58:37 +03:00
Dmitry Stogov
45fff1fe5f
Implement binding IR node to VAR (assign spill slot)
2022-09-20 11:03:25 +03:00
Dmitry Stogov
9aac7e76af
Requre opearnad to be in register
2022-09-15 22:18:35 +03:00
Dmitry Stogov
a0c9405ae7
Fixed memory leak
2022-09-15 20:32:20 +03:00
Dmitry Stogov
e6f6e92d66
Improve spill code fusion
2022-09-15 17:52:28 +03:00
Dmitry Stogov
ad59556d85
Add support for binding IR nodes to "external" spill slots (e.g. PHP VM stack slots)
2022-09-15 15:26:43 +03:00
Dmitry Stogov
d4cd0d6eba
Better interval splitting
2022-09-15 01:50:25 +03:00
Dmitry Stogov
cdc34ae22b
Prohibit swapping of operands when the first operand is constant
2022-09-14 14:28:57 +03:00
Dmitry Stogov
76028e8855
Fix compilation warnings
2022-09-05 22:43:27 +03:00
