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1,039 Commits 2 Branches 0 Tags 3.2 MiB
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159 Commits

Author SHA1 Message Date
Dmitry Stogov
51daf5556c Initial support for ALLOCA, LOAD and STORE (incomplete) 2022-04-19 23:42:05 +03:00
Dmitry Stogov
6b60d8fba9 Code generation for VLOAD and VSTORE 2022-04-19 22:35:29 +03:00
Dmitry Stogov
155c9572c8 Add ability to run "ir_test" with different optimization levels 
Fix JIT for "cmp mem, imm"
 2022-04-19 11:03:01 +03:00
Dmitry Stogov
0922b7cd7f Add vreg hints 2022-04-15 16:02:23 +03:00
Dmitry Stogov
3f6a6aa3ea Better CPU constraint model and initial support for live interval splitting (incomplete) 2022-04-14 22:40:13 +03:00
Dmitry Stogov
15b0f10a87 ws 2022-04-11 22:39:52 +03:00
Dmitry Stogov
e2601c8e06 Improve JIT support for IR_CALL 2022-04-07 23:41:38 +03:00
Dmitry Stogov
5b34386f62 Register Allocator suppor for fixed registers, use positions and register hints (incomplete). 2022-04-07 11:11:57 +03:00
Dmitry Stogov
2937993190 Initial import 2022-04-06 00:19:23 +03:00