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215 Commits

Author SHA1 Message Date
Dmitry Stogov
740cac8e2f Move ir_ctx.unused_live_ranges to local variable 2022-05-25 10:57:21 +03:00
Dmitry Stogov
c9bb858e50 Fuse loads without register allocation when this makes sense. 
Make oarameters passed through stack to reuse the same stack slot for spilling.
 2022-05-19 10:53:08 +03:00
Dmitry Stogov
1af065058b Use better name 2022-05-19 09:15:45 +03:00
Dmitry Stogov
e9e214d7d9 Remove special support for "_spill_" variable 2022-05-18 17:32:32 +03:00
Dmitry Stogov
0189eb28d0 Use a kind of "Buddy Allocaor" to pack spill slots of different sizes 2022-05-17 00:17:59 +03:00
Dmitry Stogov
6fb5380906 Take into account spill slot size and alignment 2022-05-16 22:16:29 +03:00
Dmitry Stogov
5f529a9d67 Hint propagation 2022-05-16 11:53:10 +03:00
Dmitry Stogov
e8dd422167 Cleanup "top" usage 2022-05-16 10:19:30 +03:00
Dmitry Stogov
e4e3336b2b Take into account registers used to pass constants 2022-05-13 15:26:11 +03:00
Dmitry Stogov
896ddb9e77 Flexable scratch register constraints (allow MUL %edx) 2022-05-13 15:10:15 +03:00
Dmitry Stogov
3dac541928 LSRA cleanup 2022-05-13 12:14:21 +03:00
Dmitry Stogov
4eaca331b9 Allow using debug_regset in RELEASE build 2022-05-13 09:22:31 +03:00
Dmitry Stogov
cd6eb1354a Renumber virtual registers 2022-05-13 01:15:24 +03:00
Dmitry Stogov
1f673ebfda Better temporary register usage for SSA deconstruction 2022-05-13 00:32:37 +03:00
Dmitry Stogov
386b140265 Refactor Linear Scan Register Allocator to use linked lists instead of bitsets 
This fixes allocation of several temporary variables for single instruction
 2022-05-12 17:43:08 +03:00
Dmitry Stogov
1028d7d330 Fix reading behind array range 2022-05-12 11:04:20 +03:00
Dmitry Stogov
c2d224148b Use prefered register if possible 2022-05-11 21:10:35 +03:00
Dmitry Stogov
69b5a852e5 Make DESSA API use "ir_ref" instead of "virtual register number" 
(0 - is still a temporary register)
 2022-05-06 16:19:57 +03:00
Dmitry Stogov
9f1ca6b82c Add IR_LIVE_INTERVAL_TEMP and IR_LIVE_INTERVAL_VAR flags 2022-05-06 09:23:14 +03:00
Dmitry Stogov
dd5a3a3b72 Add flexible support for temporary registers. 
Get rid of hardcoded temporary registers (incomplete)
 2022-05-05 22:35:39 +03:00
Dmitry Stogov
1130c256ae Find optimal split position 2022-05-04 11:59:35 +03:00
Dmitry Stogov
4f294109e8 Result of PARAM may be stored into a spill slot without register 2022-05-04 09:50:23 +03:00
Dmitry Stogov
1b156c49e8 Use "hint" regiser only if it's not disabled by "--debug-regset" 2022-05-04 09:08:23 +03:00
Dmitry Stogov
27540fd43a Use optimal split position (incompete) 2022-04-29 19:24:15 +03:00
Dmitry Stogov
b3c61507a4 Fixed possible incorrect splitting 2022-04-29 18:50:57 +03:00
Dmitry Stogov
102b367d64 cleanup 2022-04-29 15:24:41 +03:00
Dmitry Stogov
f5f9614854 cleanup 2022-04-29 14:19:53 +03:00
Dmitry Stogov
23945c4bdc Better debug logging 2022-04-29 12:14:26 +03:00
Dmitry Stogov
2e3ba321f8 Swap UsePos flags and prefer to reload registers that SHOULD be in a CPU register 2022-04-29 03:39:32 +03:00
Dmitry Stogov
3e6f84eef4 Add "must be in reg" constraint 2022-04-28 14:48:43 +03:00
Dmitry Stogov
ea46798aeb Fix live interval splitting and second chance binpacking (it seems to work, but may be icomplete) 2022-04-28 13:09:55 +03:00
Dmitry Stogov
acffada3b1 Fix interval processing order 2022-04-28 10:27:01 +03:00
Dmitry Stogov
fffc0ad2ef Delay spill slot allocation 2022-04-28 10:16:02 +03:00
Dmitry Stogov
53532fcb39 Select better register 2022-04-28 01:25:10 +03:00
Dmitry Stogov
5b7a7decd0 Fix splitting of use positions 2022-04-28 00:12:01 +03:00
Dmitry Stogov
9287830a77 Process remaining splits after all unhandled intervals 2022-04-27 23:31:20 +03:00
Dmitry Stogov
59b63cbb91 Sort oputput UsePos after inputs 2022-04-27 21:24:51 +03:00
Dmitry Stogov
7f8f186abd Fix the way as linera-scan walks through splitted intervals 2022-04-27 18:18:53 +03:00
Dmitry Stogov
6e77f886cb LSRA tweaks 2022-04-27 15:02:51 +03:00
Dmitry Stogov
2b9e793b4e Add debug options 2022-04-27 14:47:52 +03:00
Dmitry Stogov
c89246f35a Replace asserts with checks 2022-04-27 01:34:29 +03:00
Dmitry Stogov
329e1f5a44 Fix splitting (incomplete) 2022-04-27 01:04:03 +03:00
Dmitry Stogov
beaa2744e1 Keep fixed live intervals after coalescing 2022-04-26 21:16:22 +03:00
Dmitry Stogov
1370629b47 Fixed interval sorting 2022-04-26 11:51:48 +03:00
Dmitry Stogov
6548818887 Improve interval splitting (incomplete) 2022-04-26 00:54:07 +03:00
Dmitry Stogov
648d7084bc Fix intrval reconstruction after operand swapping 2022-04-25 21:00:01 +03:00
Dmitry Stogov
034ef95e07 Allow memory update instructions (without loading into register) 2022-04-22 01:40:10 +03:00
Dmitry Stogov
84b2bac02c Add more tests 2022-04-22 00:11:34 +03:00
Dmitry Stogov
c36efda8a5 Improve register allocation for commutative instructions 
- swap operands f this make sense
- fix coalescing bug
 2022-04-21 16:38:18 +03:00
Dmitry Stogov
20c9f2e92a Add comment 2022-04-20 19:30:28 +03:00