Dmitry Stogov
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211884cf29
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Introduce API to load modules
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2023-10-11 22:55:25 +03:00 |
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Dmitry Stogov
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09829a9e69
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Fixed x86_64 calling convention for vararg functions
%al is used as a hidden register to specify the number of passed vector registers
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2023-09-27 10:23:34 +03:00 |
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Dmitry Stogov
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0dbb794399
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CI tests for MACOS build (#46)
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2023-08-30 15:24:12 +03:00 |
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Dmitry Stogov
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8a5a81c03e
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Improve live interval splitting and eliminate more redundand spill loads
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2023-06-27 11:29:26 +03:00 |
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Dmitry Stogov
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678a6af863
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Eliminate duplicate spill loads at the same basic block
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2023-06-22 14:41:01 +03:00 |
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Dmitry Stogov
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35f94d570f
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Revert "Eliminate duplicate spill loads at the same basic block"
This reverts commit 5d05d78462.
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2023-06-22 01:58:26 +03:00 |
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Dmitry Stogov
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5d05d78462
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Eliminate duplicate spill loads at the same basic block
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2023-06-22 01:24:50 +03:00 |
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Dmitry Stogov
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c9fa8dfebd
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Fixed SSA deconstruction
Previously we performed parallel copy for virtual registers, now we do
the same for the target CPU registers.
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2023-05-17 22:37:45 +03:00 |
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Dmitry Stogov
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9eb366698d
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Avoid reservaton of temporary resiser for argument passing
We may use any scratch register that is not used for parameters
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2023-04-26 12:16:05 +03:00 |
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Dmitry Stogov
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1e5e9e08ce
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Re-implement instruction fusion and live-range construction
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2023-04-05 19:20:43 +03:00 |
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Dmitry Stogov
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24e8e216a1
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Remove a "reference" edge from LOOP_END to LOOP_BEGIN node.
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2023-03-23 00:47:27 +03:00 |
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Dmitry Stogov
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37dececa71
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Add more tests (8 tests ara failed on 32-bit x86)
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2022-11-08 11:56:22 +03:00 |
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