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182 Commits

Author SHA1 Message Date
Dmitry Stogov
ac4ea33c24 Link with undefined functions through "thunks" 2023-12-20 21:06:53 +03:00
Dmitry Stogov
3dd4146097
Allow using "thunks" to call "far" functions (#57) 
* Allow using "thunks" to call "far" functions

* Fix Windows tests

* Fix identation
 2023-12-19 22:22:49 +03:00
Dmitry Stogov
624dd3b828 Don't optimize signed division by power of two 2023-12-15 14:09:26 +03:00
Dmitry Stogov
eeed93083e Restore ability to reach "local" exit table base address 2023-12-11 15:06:52 +03:00
Dmitry Stogov
1e8ff8078a Cleanup symbolic constants usage 2023-12-08 17:35:41 +03:00
Dmitry Stogov
b7e7de5821 Simplify JIT code buffer management 2023-12-08 01:58:45 +03:00
Dmitry Stogov
6898d26e80 Allow code generation for functions with unesolved symbols 2023-12-06 16:30:44 +03:00
Pengfei Li
384e1aa926 AArch64: Fix incorrect value of "ctx->code_size" 
There is a typo in `ir_aarch64.dasc` that may set `ctx->code_size` to an
invalid value (-2). We don't find any test failure with the typo because
currently `ctx->code_size` is only used in `zend_jit_get_veneer()`. This
patch fixes the typo to avoid potential issues in the future.
 2023-12-05 17:22:11 +03:00
Dmitry Stogov
81fab9a2cb Fixed TAILCALL to CALL conversion 2023-12-04 11:32:26 +03:00
Dmitry Stogov
c5bf8003c0 On MacOS/AArch64 varargs must be passed on stack 2023-11-30 23:50:53 +03:00
Dmitry Stogov
76e6418cae Support for function prototypes 2023-11-30 21:10:41 +03:00
Dmitry Stogov
81047af575 Cleanup code-generation for VA_ARG 2023-11-23 22:52:08 +03:00
Dmitry Stogov
25bd3024da Codegeneration for VA_ARG nodes (Windows and MacOS are not supported yet) 2023-11-23 19:38:33 +03:00
Dmitry Stogov
18a3192604 JIT/AArch64: Add code-generation for IR_TRAP 2023-11-22 11:43:33 +03:00
Dmitry Stogov
68068c4f58 Split ir_ctx->flags into public and private (ir_ctx->flags2) 2023-11-17 14:24:33 +03:00
Dmitry Stogov
688f876928 mplemented code-generation for bit counting instructions 2023-11-16 22:48:05 +03:00
Dmitry Stogov
92ef948caf Implemented code-generation for CTPOP 2023-11-16 19:28:12 +03:00
Dmitry Stogov
5e9d41f6b4 AArch64: Remove redundant memory unmap #12688 2023-11-16 11:50:57 +03:00
Dmitry Stogov
90b6f34db2 Add FRAME_ADDR node 2023-11-16 01:59:26 +03:00
Dmitry Stogov
6edb011548 Fixed code generation for unordered floating point comparison 
- Fixed COND on AArch64
- Fixed SYM support on AArch64
 2023-10-24 10:22:04 +03:00
Dmitry Stogov
9b1ce974cb Improve loader interface (incomplete) 2023-10-20 01:09:46 +03:00
Dmitry Stogov
613fca0327 Implemented code generation for COND (not optimized) 2023-10-13 20:50:23 +03:00
Javier Eguiluz
2f4f8504d4
Fix some typos (#51) 2023-10-03 08:34:02 +03:00
Dmitry Stogov
8977307f4e Improve error handling 2023-09-14 20:15:30 +03:00
Dmitry Stogov
5953d17f5f Don't miss spill loads when the register valuses are reused 2023-09-12 16:12:12 +03:00
Dmitry Stogov
474a8a8d5a Fixed incorrect constant truncation 2023-08-30 12:07:52 +03:00
Dmitry Stogov
dd2ecad299 Allow reuse of spill slots for objecs of smaller size 2023-08-02 13:20:13 +03:00
Dmitry Stogov
1d49fe6cc4 Reduce cost of disabled IR_ASSERT() 2023-07-27 11:16:00 +03:00
Dmitry Stogov
f6cf9140da Update ir_insn.inputs_count and use it after ir_build_def_use_lists() 2023-07-06 01:15:08 +03:00
Dmitry Stogov
ce2d6ceba6 Fixed non-boolean constant GUARD condition checks 2023-06-29 23:49:20 +03:00
Dmitry Stogov
9cec28c188 Fixed compilation warnings 2023-06-22 14:50:14 +03:00
Dmitry Stogov
85beed7901 Fixed incorrect oredering of moves during de-SSA 
Temporary de-SSA registers may conflict with outpot registers, therefore these output resisters should be assigned last.
 2023-06-22 12:07:19 +03:00
Dmitry Stogov
99bcde9e1e Cleanup spill related code 2023-06-21 23:20:58 +03:00
Dmitry Stogov
d67c212916 Separate codegen info output into ir_dump_codegen() 2023-06-21 22:36:36 +03:00
Dmitry Stogov
ebaefd376a Fix stack frame and assign all spill slots before code genearatin 2023-06-21 19:04:22 +03:00
Dmitry Stogov
4124ef5150 Allow printing IR annotated with register-allocation, spill-code-placement, de-SSA and code-generation information 2023-06-21 13:28:15 +03:00
Dmitry Stogov
25656607ba Variabls with a register constraint may be loaed/stored directly from/to a spill slot (without an additional register) 2023-06-21 01:14:31 +03:00
Dmitry Stogov
b37d4e0443 Allow usage of CPU stack slots for deoptimization 2023-06-16 02:14:02 +03:00
Dmitry Stogov
6a98514bdc Move stack size related metricks to ir_ctx 2023-06-15 19:28:54 +03:00
Dmitry Stogov
311267714e Use macros insted of bit ops 2023-06-14 20:23:32 +03:00
Dmitry Stogov
defd58cec3 Store proper %sp register value 2023-06-13 18:22:21 +03:00
Dmitry Stogov
257bdff21a Fix compilation warnings 2023-06-09 10:58:58 +03:00
Dmitry Stogov
b8be0b9dd9 Avoid loading of stack parameter to register if this is not necessary 2023-06-09 00:35:15 +03:00
Dmitry Stogov
ae4daf223e Replace assertion with a non-fatal error 2023-06-07 18:39:51 +03:00
Dmitry Stogov
3de6c5126a Avoid code generation for useless loads and stores 2023-06-07 14:43:16 +03:00
Dmitry Stogov
186dc6b0a6 Fixed GH issue #33: IR program failed to compile with "-O0" "-S" options 2023-06-05 18:22:12 +03:00
Dmitry Stogov
4e01e7251e Implemented support for veneers on AArch64 2023-06-02 00:49:32 +03:00
Dmitry Stogov
87f2fc7f69 Fixed typo 2023-05-29 15:52:17 +03:00
Dmitry Stogov
20b9a7513c Fixed missing label 2023-05-26 09:08:57 +03:00
Dmitry Stogov
2a80257535 Support for more C escape sequences 2023-05-22 19:51:19 +03:00