8 Commits

Author	SHA1	Message	Date
Javier Eguiluz	2f4f8504d4	Fix some typos (#51)	2023-10-03 08:34:02 +03:00
Dmitry Stogov	24e8e216a1	Remove a "reference" edge from LOOP_END to LOOP_BEGIN node.	2023-03-23 00:47:27 +03:00
Dmitry Stogov	5fb115ab11	Remove LOOP_EXIT	2022-06-15 17:27:31 +03:00
Dmitry Stogov	1f673ebfda	Better temporary register usage for SSA deconstruction	2022-05-13 00:32:37 +03:00
Dmitry Stogov	ffdb53821d	Refactor constraint model ... Each instruction consist from 4 sub positions LOAD, USE, DEF, SAVE. Hardware constraints are modeled conectiong live intervals and fixed intervals to different sub-positions.	2022-04-20 18:53:15 +03:00
Dmitry Stogov	3f6a6aa3ea	Better CPU constraint model and initial support for live interval splitting (incomplete)	2022-04-14 22:40:13 +03:00
Dmitry Stogov	5b34386f62	Register Allocator suppor for fixed registers, use positions and register hints (incomplete).	2022-04-07 11:11:57 +03:00
Dmitry Stogov	2937993190	Initial import	2022-04-06 00:19:23 +03:00