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1,055 Commits 2 Branches 0 Tags 3.2 MiB
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Author SHA1 Message Date
Dmitry Stogov
a8e514266f Add support for some LLVM intrinsic 2023-11-15 15:17:36 +03:00
Dmitry Stogov
3f14ac4252 Fixed address constant duplication 2023-11-14 17:58:05 +03:00
Dmitry Stogov
fab41058d4 Properly save UNREACHABLE instruction eith third operand 2023-11-14 17:12:20 +03:00
Dmitry Stogov
a2c6f98e75 Improve LLVM loader support (incomplete) 2023-11-10 18:09:48 +03:00
Dmitry Stogov
1eaf5531e5 Fixed test 2023-11-08 10:20:55 +03:00
Dmitry Stogov
d2353ddfc1 Fixed typos in register definition 2023-11-08 10:13:57 +03:00
Dmitry Stogov
ec58853788 Validate opcode 2023-11-07 11:33:35 +03:00
Dmitry Stogov
091907f4a4 Fixed typo 2023-10-25 08:40:26 +03:00
Dmitry Stogov
dfd22749ac Fixed typo in folding rule 2023-10-25 08:28:05 +03:00
Dmitry Stogov
400fa2805d An attempt to fix tests on Windows 2023-10-24 11:12:37 +03:00
Dmitry Stogov
6edb011548 Fixed code generation for unordered floating point comparison 
- Fixed COND on AArch64
- Fixed SYM support on AArch64
 2023-10-24 10:22:04 +03:00
Dmitry Stogov
d60d92516d Fixed tests 2023-10-20 17:50:31 +03:00
Dmitry Stogov
49316643e7 Initial support for modules (incomplete) 2023-10-20 17:44:45 +03:00
Dmitry Stogov
9b1ce974cb Improve loader interface (incomplete) 2023-10-20 01:09:46 +03:00
Dmitry Stogov
d72ae866e0 Fixed SYM/FUNC mess 2023-10-18 12:19:43 +03:00
Dmitry Stogov
d0686408e2 Initial support for SYM constants (incomplete) 2023-10-18 11:45:57 +03:00
Dmitry Stogov
a94dddd671 Improve cross-compilation (use separate CFLAGS and BUILD_CFLAGS) 2023-10-17 11:46:42 +03:00
Dmitry Stogov
4f9724a7fb Fix tests 2023-10-13 21:04:38 +03:00
Dmitry Stogov
66e9693019 Fix tests 2023-10-13 20:57:42 +03:00
Dmitry Stogov
613fca0327 Implemented code generation for COND (not optimized) 2023-10-13 20:50:23 +03:00
Dmitry Stogov
2984f34fe7 Fix zext(bool)->i8 2023-10-13 15:41:54 +03:00
Dmitry Stogov
9c4cabd19d Fix inerval flags reseting after coalescing 2023-10-13 13:57:48 +03:00
Dmitry Stogov
62b6ddf149 Fixed code generation for rare address mode 2023-10-13 13:29:59 +03:00
Dmitry Stogov
d641c7949a Support for unordered FP comparison (x86[_64] yet, needs tests) 2023-10-13 12:52:56 +03:00
Dmitry Stogov
e884c6b84c Reset interfal flags that become wrong after coalescing 2023-10-13 12:51:14 +03:00
Dmitry Stogov
1b978f67ce Fix codegeneration for negative 8 and 16-bit immediate values 2023-10-13 11:15:19 +03:00
Dmitry Stogov
daa31b3200 Properly remove interval from active list 2023-10-13 11:12:15 +03:00
Dmitry Stogov
dd227dfa25 New tests 2023-10-12 15:01:27 +03:00
Dmitry Stogov
1970a16496 Fixed crash on dead PHI 2023-10-12 14:54:23 +03:00
Dmitry Stogov
3f728b61b9 Allow forward references for any PHI operans before scheduling 2023-10-12 12:43:51 +03:00
Dmitry Stogov
78e95131b4 Proper VADDR insertion 2023-10-12 12:37:34 +03:00
Dmitry Stogov
180e9dd626 Fix scheduling for VADDR 2023-10-12 10:17:51 +03:00
Dmitry Stogov
d51efd33d4 Fix incorrect SSA construction 2023-10-12 10:17:04 +03:00
Dmitry Stogov
1fbb2ac2ed Skip some intrinsic 2023-10-12 08:18:18 +03:00
Dmitry Stogov
4fce67fcb7 Restore accedently removed ir_free() 2023-10-11 23:01:15 +03:00
Dmitry Stogov
211884cf29 Introduce API to load modules 2023-10-11 22:55:25 +03:00
Dmitry Stogov
8668550427
Initial support for LLVM loader (incomplete) (#53) 
Currently we may just load LLVM module and convert all functions into IR (print it).
For better LLVM support IR framework needs support for modules.
Some LLVM features are not supported yet (see TODOs in ir_load_llvm.c) .
 2023-10-11 12:46:31 +03:00
Dmitry Stogov
cad27ab17a
typo 2023-10-05 21:14:18 +03:00
Dmitry Stogov
569e971625
typo 2023-10-05 21:13:22 +03:00
Dmitry Stogov
c9d796555d
typo 2023-10-05 21:12:53 +03:00
Dmitry Stogov
0b5254b769
Update README.md 2023-10-05 21:04:28 +03:00
Niels Dossche
d435e7c404
Fix typo in AVX if condition (#52) 2023-10-04 08:41:43 +03:00
Dmitry Stogov
827b8ebd9c Fix typo in the first place 2023-10-03 08:35:35 +03:00
Javier Eguiluz
2f4f8504d4
Fix some typos (#51) 2023-10-03 08:34:02 +03:00
Dmitry Stogov
70ed0a7d96 Support for GUARD 2023-09-29 12:27:34 +03:00
Dmitry Stogov
9ea551a34f LLVM support for fastcall and vararg 2023-09-29 11:30:53 +03:00
Dmitry Stogov
85b2ea6e16 clenup 2023-09-29 09:42:31 +03:00
Dmitry Stogov
56bb320b81 Fixed compilation error 2023-09-28 20:49:03 +03:00
Dmitry Stogov
51a37f159b Initial implementation of LLVM export 2023-09-28 20:44:45 +03:00
Dmitry Stogov
09829a9e69 Fixed x86_64 calling convention for vararg functions 
%al is used as a hidden register to specify the number of passed vector registers
 2023-09-27 10:23:34 +03:00