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209 Commits 2 Branches 0 Tags 3.2 MiB
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5 Commits

Author SHA1 Message Date
Dmitry Stogov
1f673ebfda Better temporary register usage for SSA deconstruction 2022-05-13 00:32:37 +03:00
Dmitry Stogov
ffdb53821d Refactor constraint model 
Each instruction consist from 4 sub positions LOAD, USE, DEF, SAVE.
Hardware constraints are modeled conectiong live intervals and fixed
intervals to different sub-positions.
 2022-04-20 18:53:15 +03:00
Dmitry Stogov
3f6a6aa3ea Better CPU constraint model and initial support for live interval splitting (incomplete) 2022-04-14 22:40:13 +03:00
Dmitry Stogov
5b34386f62 Register Allocator suppor for fixed registers, use positions and register hints (incomplete). 2022-04-07 11:11:57 +03:00
Dmitry Stogov
2937993190 Initial import 2022-04-06 00:19:23 +03:00