Dmitry Stogov
009e9c4a53
Split assign_regs() loop into two versions (with and without spilling).
2023-06-20 08:34:54 +03:00
Dmitry Stogov
b37d4e0443
Allow usage of CPU stack slots for deoptimization
2023-06-16 02:14:02 +03:00
Dmitry Stogov
6a98514bdc
Move stack size related metricks to ir_ctx
2023-06-15 19:28:54 +03:00
Dmitry Stogov
311267714e
Use macros insted of bit ops
2023-06-14 20:23:32 +03:00
Dmitry Stogov
6a8830c1dc
Better usage of the register hints
2023-06-09 16:26:15 +03:00
Dmitry Stogov
b8be0b9dd9
Avoid loading of stack parameter to register if this is not necessary
2023-06-09 00:35:15 +03:00
Dmitry Stogov
c599cfbdf3
Fixed spill slot allocation
2023-06-07 18:37:37 +03:00
Dmitry Stogov
186dc6b0a6
Fixed GH issue #33 : IR program failed to compile with "-O0" "-S" options
2023-06-05 18:22:12 +03:00
Dmitry Stogov
3b0de17cdd
Added missing fixed interval
2023-06-01 11:00:39 +03:00
Dmitry Stogov
6009e376b7
Speed-up liner scan
...
- Don't add allocated interval into "active" list, if it doesn't overlap
with next unhandled
- More efficient selection of registers available for the whole range
2023-06-01 00:48:21 +03:00
Dmitry Stogov
d3640495a2
Ceanup ir_compute_live_ranges() implementation
2023-05-19 12:34:54 +03:00
Dmitry Stogov
5c2023fd7f
Avoid live range constrction for VARs
2023-05-18 21:00:57 +03:00
Dmitry Stogov
ef31712f26
Remove usused IR_LIVE_INTERVAL_REG_LOAD flag
2023-05-18 14:17:54 +03:00
Dmitry Stogov
477dbf7d76
Avoid live range constrction for RLOAD with fixed registers
2023-05-18 13:37:12 +03:00
Dmitry Stogov
b6517f2028
Split IR_LIVE_INTERVAL_HAS_HINTS into IR_LIVE_INTERVAL_HAS_HINT_REGS and
...
IR_LIVE_INTERVAL_HAS_HINT_REFS
2023-05-18 10:48:31 +03:00
Dmitry Stogov
c9fa8dfebd
Fixed SSA deconstruction
...
Previously we performed parallel copy for virtual registers, now we do
the same for the target CPU registers.
2023-05-17 22:37:45 +03:00
Dmitry Stogov
af7117a3b7
Use cfg_map if available
2023-05-17 11:14:34 +03:00
Dmitry Stogov
d859591943
Inline fast path
2023-05-05 18:37:14 +03:00
Dmitry Stogov
c3fca224ff
Introduce IR_OP_FLAG_PINNED and IR_BB_HAS_PHI/PI/PARAM/VAR flags
2023-05-05 16:59:22 +03:00
Dmitry Stogov
1150c80ca2
Fixed support for OSR ENTRY
2023-05-05 12:59:33 +03:00
Dmitry Stogov
76f44fa126
Implemented path-exploration based live ranges construction
...
The algorithm is based on "Computing Liveness Sets for SSA-Form Programs",
Florian Brandner, Benoit Boissinot, Alain Darte, Benoit Dupont de Dinechin,
Fabrice Rastello. TR Inria RR-7503, 2011
In comparison to the existing bitset based approach, the new algorithm
is more memory-space efficient and faster on big functions.
2023-05-05 02:01:53 +03:00
Dmitry Stogov
ac3a11e911
Improve ir_add_live_range(). Set ival->type when process definition.
2023-05-04 12:23:40 +03:00
Dmitry Stogov
d30f523c62
Avoid iteration over an empty bitset
2023-05-03 12:30:05 +03:00
Dmitry Stogov
1bbee7b9da
Get rid of ir_live_interval.top
2023-04-28 09:49:12 +03:00
Dmitry Stogov
0de0c1d0fa
Improve parallel copy algorithm to support move of single source into multiple destinations
2023-04-26 10:56:55 +03:00
Dmitry Stogov
1749168078
Add ir_insn_len() and ir_insn_inputs_to_len() private helpers
2023-04-21 13:40:55 +03:00
Dmitry Stogov
e01c43a967
Simplify access to nodes with variable inputs count
2023-04-21 12:40:17 +03:00
Dmitry Stogov
ac7f9a3a02
Improve ir_compute_live_ranges()
2023-04-14 01:47:47 +03:00
Dmitry Stogov
1115e7fb6e
cleanup
2023-04-13 21:45:38 +03:00
Dmitry Stogov
2a17b87219
LSRA optimization
2023-04-13 20:56:49 +03:00
Dmitry Stogov
e5c01495da
Use arena to allocate live_intervals and nested data structures
2023-04-13 13:47:16 +03:00
Dmitry Stogov
0b78a322f8
Cache deleted live ranges in ir_ctx.unused_ranges
2023-04-13 11:42:47 +03:00
Dmitry Stogov
7d395532d9
Simplify ir_assign_virtual_registers()
2023-04-13 03:01:08 +03:00
Dmitry Stogov
f85f5fd2a8
Remove data dependency between TAILCALL and UNREACHABLE
2023-04-13 02:41:28 +03:00
Dmitry Stogov
d71cbd47d5
Disable LICM across an OSR ENTRY if the value can't be restored at OSR ENTRY point
2023-04-07 16:36:27 +03:00
Dmitry Stogov
efa8a83153
Fix spilling code for arguments passed theought stack and change RA to
...
prefer reusing the same register for splitted intervals
i# utils/
2023-04-06 00:16:49 +03:00
Dmitry Stogov
1e5e9e08ce
Re-implement instruction fusion and live-range construction
2023-04-05 19:20:43 +03:00
Dmitry Stogov
ee827ee983
Don't create two DEF UsePos
2023-03-29 17:22:49 +03:00
Dmitry Stogov
2392f546bf
Improve merging of sorted lists
2023-03-24 12:42:41 +03:00
Dmitry Stogov
87dbdcea0d
Add necessary compensation loads for bounded nodes when enter into function through OSR entry-point
2023-03-21 13:45:37 +03:00
Dmitry Stogov
f5b7065b10
Refactor the ENTRY nodes
...
Now all ENTRY nodes have a "fake" input control edge.
Through this edge all of them are dominated by START node.
2023-03-17 09:02:37 +03:00
Dmitry Stogov
300665700f
Adopt IR test engine for Windows (this requires php and diff installed)
2023-03-01 20:31:14 +03:00
Dmitry Stogov
9b34731d16
Fix most MSVC compilation warnings
2023-02-28 02:11:09 +03:00
Anatol Belski
964f5a0191
build: MSVC compatibility
...
Signed-off-by: Anatol Belski <ab@php.net>
2023-02-25 00:04:57 +01:00
Dmitry Stogov
31ea3153f3
Add (commeted) code that could eliminate register move for RSTORE
2023-02-16 17:49:30 +03:00
Dmitry Stogov
c7e2cca534
Add hint to reuse register in ZEXT/SEXT
2023-02-15 18:33:02 +03:00
Dmitry Stogov
0eff9e0516
Registers %r4b - %r7b are not available in 32-bit mode
2023-01-24 15:31:31 +03:00
Dmitry Stogov
32ad3d1052
Use inline functions to avoid false positive address sanitaizer warnings
2023-01-20 15:35:02 +03:00
Dmitry Stogov
3ac58893f2
Fix address sanitizer warnings
2023-01-20 11:30:22 +03:00
Dmitry Stogov
5103c18269
Fix load fusion in combination with depended register spill load
2023-01-19 13:39:29 +03:00
