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852 Commits

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Author SHA1 Message Date
Dmitry Stogov
dd5a3a3b72 Add flexible support for temporary registers. 
Get rid of hardcoded temporary registers (incomplete)
 2022-05-05 22:35:39 +03:00
Dmitry Stogov
7de4566498 Add tests for 64-bit constants 2022-05-04 15:37:07 +03:00
Dmitry Stogov
1130c256ae Find optimal split position 2022-05-04 11:59:35 +03:00
Dmitry Stogov
4f294109e8 Result of PARAM may be stored into a spill slot without register 2022-05-04 09:50:23 +03:00
Dmitry Stogov
a5b676b590 Fix incorrect operands order 2022-05-04 09:11:05 +03:00
Dmitry Stogov
1b156c49e8 Use "hint" regiser only if it's not disabled by "--debug-regset" 2022-05-04 09:08:23 +03:00
Dmitry Stogov
27540fd43a Use optimal split position (incompete) 2022-04-29 19:24:15 +03:00
Dmitry Stogov
b3c61507a4 Fixed possible incorrect splitting 2022-04-29 18:50:57 +03:00
Dmitry Stogov
102b367d64 cleanup 2022-04-29 15:24:41 +03:00
Dmitry Stogov
f5f9614854 cleanup 2022-04-29 14:19:53 +03:00
Dmitry Stogov
23945c4bdc Better debug logging 2022-04-29 12:14:26 +03:00
Dmitry Stogov
2e3ba321f8 Swap UsePos flags and prefer to reload registers that SHOULD be in a CPU register 2022-04-29 03:39:32 +03:00
Dmitry Stogov
3e6f84eef4 Add "must be in reg" constraint 2022-04-28 14:48:43 +03:00
Dmitry Stogov
ea46798aeb Fix live interval splitting and second chance binpacking (it seems to work, but may be icomplete) 2022-04-28 13:09:55 +03:00
Dmitry Stogov
acffada3b1 Fix interval processing order 2022-04-28 10:27:01 +03:00
Dmitry Stogov
fffc0ad2ef Delay spill slot allocation 2022-04-28 10:16:02 +03:00
Dmitry Stogov
240259adf8 add task 2022-04-28 09:23:02 +03:00
Dmitry Stogov
53532fcb39 Select better register 2022-04-28 01:25:10 +03:00
Dmitry Stogov
5b7a7decd0 Fix splitting of use positions 2022-04-28 00:12:01 +03:00
Dmitry Stogov
9287830a77 Process remaining splits after all unhandled intervals 2022-04-27 23:31:20 +03:00
Dmitry Stogov
59b63cbb91 Sort oputput UsePos after inputs 2022-04-27 21:24:51 +03:00
Dmitry Stogov
7f8f186abd Fix the way as linera-scan walks through splitted intervals 2022-04-27 18:18:53 +03:00
Dmitry Stogov
6e77f886cb LSRA tweaks 2022-04-27 15:02:51 +03:00
Dmitry Stogov
2b9e793b4e Add debug options 2022-04-27 14:47:52 +03:00
Dmitry Stogov
c89246f35a Replace asserts with checks 2022-04-27 01:34:29 +03:00
Dmitry Stogov
329e1f5a44 Fix splitting (incomplete) 2022-04-27 01:04:03 +03:00
Dmitry Stogov
310f605d6c Fix register clobbering 2022-04-26 22:49:41 +03:00
Dmitry Stogov
beaa2744e1 Keep fixed live intervals after coalescing 2022-04-26 21:16:22 +03:00
Dmitry Stogov
1370629b47 Fixed interval sorting 2022-04-26 11:51:48 +03:00
Dmitry Stogov
6548818887 Improve interval splitting (incomplete) 2022-04-26 00:54:07 +03:00
Dmitry Stogov
648d7084bc Fix intrval reconstruction after operand swapping 2022-04-25 21:00:01 +03:00
Dmitry Stogov
99e2b4c3fd Remove done and add new tasks 2022-04-22 13:31:28 +03:00
Dmitry Stogov
4a6c8d60a6 Fix ALLOCA to align stack frame 2022-04-22 12:55:38 +03:00
Dmitry Stogov
5cb0af8cd9 Support for compound assignment instructions 2022-04-22 12:11:30 +03:00
Dmitry Stogov
549ac2efd9 Add test 2022-04-22 11:32:59 +03:00
Dmitry Stogov
c47de38bab Merge spill slots for VAR, VLOAD and VSTORE (this may be unsafe) 2022-04-22 11:30:33 +03:00
Dmitry Stogov
034ef95e07 Allow memory update instructions (without loading into register) 2022-04-22 01:40:10 +03:00
Dmitry Stogov
84b2bac02c Add more tests 2022-04-22 00:11:34 +03:00
Dmitry Stogov
ea77ea27cb Improve code for commutative instructions 
(ir_last_use() may be incomplete)
 2022-04-21 21:47:00 +03:00
Dmitry Stogov
c36efda8a5 Improve register allocation for commutative instructions 
- swap operands f this make sense
- fix coalescing bug
 2022-04-21 16:38:18 +03:00
Dmitry Stogov
bb9813975e Add IR_OP_FLAG_COMMUTATIVE 2022-04-21 11:30:05 +03:00
Dmitry Stogov
139b49c6ea Update tasks 2022-04-21 10:20:41 +03:00
Dmitry Stogov
6f3cc3052c Implement ABS for C code generator 
Remove POW
 2022-04-21 01:00:46 +03:00
Dmitry Stogov
506e7b658f Implement ABS and NEG 2022-04-21 00:31:28 +03:00
Dmitry Stogov
20c9f2e92a Add comment 2022-04-20 19:30:28 +03:00
Dmitry Stogov
a5054f4c31 Add hints for passing arguments 2022-04-20 19:15:03 +03:00
Dmitry Stogov
ffdb53821d Refactor constraint model 
Each instruction consist from 4 sub positions LOAD, USE, DEF, SAVE.
Hardware constraints are modeled conectiong live intervals and fixed
intervals to different sub-positions.
 2022-04-20 18:53:15 +03:00
Dmitry Stogov
9d18dd765b Fix stack frame layout 2022-04-20 14:12:52 +03:00
Dmitry Stogov
9796a7d9a4 Fixed stack frame corruption 2022-04-20 12:27:29 +03:00
Dmitry Stogov
705f0f1e1d VADDR instruction 2022-04-20 12:00:36 +03:00