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371 Commits 2 Branches 0 Tags 3.2 MiB
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18 Commits

Author SHA1 Message Date
Dmitry Stogov
5e4503b624 Fix JMP optimization for MERGE/N and last basic block 2022-08-31 00:01:15 +03:00
Dmitry Stogov
32198c00b7 Reimplement JMP optimization 2022-08-30 23:15:20 +03:00
Dmitry Stogov
00e92483bc Fix compilation warnings 2022-06-21 11:41:59 +03:00
Dmitry Stogov
5ef1e97261 Better support for unreachable basic blocks 2022-06-20 16:34:44 +03:00
Dmitry Stogov
5fb115ab11 Remove LOOP_EXIT 2022-06-15 17:27:31 +03:00
Dmitry Stogov
ad052c59ab cleanup 2022-06-06 22:36:11 +03:00
Dmitry Stogov
ead2b69fc6 x86_32 backend (incomplete) 2022-05-25 22:00:18 +03:00
Dmitry Stogov
9215162833 Ger rid of ir_ctx.bb_num and double neaning of ir_ctx.prev_insn_len 2022-05-25 11:58:35 +03:00
Dmitry Stogov
d250f77713 Improve type conversion nodes 2022-05-20 09:00:13 +03:00
Dmitry Stogov
c6b0e95d6b Add type conversion nodes (no code generation yet) 2022-05-20 01:01:48 +03:00
Dmitry Stogov
911219493d Implement IJMP instruction (indirect jump or computed goto) 2022-05-19 18:56:48 +03:00
Dmitry Stogov
69b5a852e5 Make DESSA API use "ir_ref" instead of "virtual register number" 
(0 - is still a temporary register)
 2022-05-06 16:19:57 +03:00
Dmitry Stogov
6f3cc3052c Implement ABS for C code generator 
Remove POW
 2022-04-21 01:00:46 +03:00
Dmitry Stogov
705f0f1e1d VADDR instruction 2022-04-20 12:00:36 +03:00
Dmitry Stogov
51daf5556c Initial support for ALLOCA, LOAD and STORE (incomplete) 2022-04-19 23:42:05 +03:00
Dmitry Stogov
7e9d1d7dba Improve VLOAD/VSTORE support in C code generator 2022-04-19 17:14:44 +03:00
Dmitry Stogov
9ccefcf973 Support for more instruction in C backend and BOOL_NOT in x86_86 2022-04-08 19:02:11 +03:00
Dmitry Stogov
2937993190 Initial import 2022-04-06 00:19:23 +03:00