11 Commits

Author	SHA1	Message	Date
Dmitry Stogov	5d05d78462	Eliminate duplicate spill loads at the same basic block	2023-06-22 01:24:50 +03:00
Dmitry Stogov	c9fa8dfebd	Fixed SSA deconstruction ... Previously we performed parallel copy for virtual registers, now we do the same for the target CPU registers.	2023-05-17 22:37:45 +03:00
Dmitry Stogov	9eb366698d	Avoid reservaton of temporary resiser for argument passing ... We may use any scratch register that is not used for parameters	2023-04-26 12:16:05 +03:00
Dmitry Stogov	1e5e9e08ce	Re-implement instruction fusion and live-range construction	2023-04-05 19:20:43 +03:00
Dmitry Stogov	ee827ee983	Don't create two DEF UsePos	2023-03-29 17:22:49 +03:00
Dmitry Stogov	d79bd88f6f	Improve x86 code generation for passing address of label to stack ... - leal .L1, %eax - movl %eax, (%esp) + movl $.L1, (%esp)	2023-03-29 15:48:41 +03:00
Dmitry Stogov	24e8e216a1	Remove a "reference" edge from LOOP_END to LOOP_BEGIN node.	2023-03-23 00:47:27 +03:00
Dmitry Stogov	2e31446e37	Better 'jp' elimination for IR_CMP_AND_BRANCH_FP	2023-02-07 01:57:07 +03:00
Dmitry Stogov	67da9e93ea	Fix register clobbering during argument passing and spill load	2022-12-26 20:25:11 +03:00
Dmitry Stogov	d26b162ffa	Fix register clobbering during argument passing	2022-12-26 18:27:53 +03:00
Dmitry Stogov	37dececa71	Add more tests (8 tests ara failed on 32-bit x86)	2022-11-08 11:56:22 +03:00