8 Commits

Author	SHA1	Message	Date
Dmitry Stogov	5d05d78462	Eliminate duplicate spill loads at the same basic block	2023-06-22 01:24:50 +03:00
Dmitry Stogov	ebaefd376a	Fix stack frame and assign all spill slots before code genearatin	2023-06-21 19:04:22 +03:00
Dmitry Stogov	b8be0b9dd9	Avoid loading of stack parameter to register if this is not necessary	2023-06-09 00:35:15 +03:00
Dmitry Stogov	c9fa8dfebd	Fixed SSA deconstruction ... Previously we performed parallel copy for virtual registers, now we do the same for the target CPU registers.	2023-05-17 22:37:45 +03:00
Dmitry Stogov	1e5e9e08ce	Re-implement instruction fusion and live-range construction	2023-04-05 19:20:43 +03:00
Dmitry Stogov	ee827ee983	Don't create two DEF UsePos	2023-03-29 17:22:49 +03:00
Dmitry Stogov	24e8e216a1	Remove a "reference" edge from LOOP_END to LOOP_BEGIN node.	2023-03-23 00:47:27 +03:00
Dmitry Stogov	37dececa71	Add more tests (8 tests ara failed on 32-bit x86)	2022-11-08 11:56:22 +03:00