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6a8830c1dc
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126 Commits

Author SHA1 Message Date
Dmitry Stogov
6a8830c1dc Better usage of the register hints 2023-06-09 16:26:15 +03:00
Dmitry Stogov
0d3af66a2b Fix test 2023-06-09 10:58:49 +03:00
Dmitry Stogov
b8be0b9dd9 Avoid loading of stack parameter to register if this is not necessary 2023-06-09 00:35:15 +03:00
Dmitry Stogov
186dc6b0a6 Fixed GH issue #33: IR program failed to compile with "-O0" "-S" options 2023-06-05 18:22:12 +03:00
Dmitry Stogov
b5bb5f869a Fixed GH Issue #34 (Simple if-else IR program compile failure) 2023-06-05 14:21:03 +03:00
Dmitry Stogov
b560ddc8f6 Added test 2023-05-29 17:11:26 +03:00
Dmitry Stogov
c9d3804b6e Fixed mistakes in GCM algorithm 2023-05-29 17:02:50 +03:00
Dmitry Stogov
4d2ef9401f Fixed GH Issue #41 (ir_emit_c() dumping misses BB label) 2023-05-29 13:58:32 +03:00
Dmitry Stogov
75edc8fec5 Added type compatibility assertion and fixed mistakes in tests 2023-05-22 20:48:07 +03:00
Dmitry Stogov
3dcb083eb6 Fix Win64 tests 2023-05-17 22:49:26 +03:00
Dmitry Stogov
c9fa8dfebd Fixed SSA deconstruction 
Previously we performed parallel copy for virtual registers, now we do
the same for the target CPU registers.
 2023-05-17 22:37:45 +03:00
Dmitry Stogov
53f4435f8e Fixed test 2023-04-26 14:24:43 +03:00
Dmitry Stogov
60802d942f Fix previous commit. We still need a temporary register for indirect calls. 2023-04-26 14:10:58 +03:00
Dmitry Stogov
9eb366698d Avoid reservaton of temporary resiser for argument passing 
We may use any scratch register that is not used for parameters
 2023-04-26 12:16:05 +03:00
Dmitry Stogov
0de0c1d0fa Improve parallel copy algorithm to support move of single source into multiple destinations 2023-04-26 10:56:55 +03:00
Dmitry Stogov
1f7a2bd243 Remove useless "AVX" tests for AArch64 2023-04-18 10:14:59 +03:00
Dmitry Stogov
f85f5fd2a8 Remove data dependency between TAILCALL and UNREACHABLE 2023-04-13 02:41:28 +03:00
Dmitry Stogov
efa8a83153 Fix spilling code for arguments passed theought stack and change RA to 
prefer reusing the same register for splitted intervals
i#	utils/
 2023-04-06 00:16:49 +03:00
Dmitry Stogov
1e5e9e08ce Re-implement instruction fusion and live-range construction 2023-04-05 19:20:43 +03:00
Dmitry Stogov
ee827ee983 Don't create two DEF UsePos 2023-03-29 17:22:49 +03:00
Dmitry Stogov
d79bd88f6f Improve x86 code generation for passing address of label to stack 
-       leal .L1, %eax
-       movl %eax, (%esp)
+       movl $.L1, (%esp)
 2023-03-29 15:48:41 +03:00
Dmitry Stogov
5bed3d73a5 Fix test 2023-03-29 15:13:17 +03:00
Dmitry Stogov
26e462fa42 Add more folding rules 2023-03-29 14:07:31 +03:00
Dmitry Stogov
e4b618ad00 Fix fusion of IF(_, CMP(AND(_, _) 0)) 2023-03-28 19:03:06 +03:00
Dmitry Stogov
6d36fb12c3 Fix example code and test 2023-03-23 00:54:47 +03:00
Dmitry Stogov
24e8e216a1 Remove a "reference" edge from LOOP_END to LOOP_BEGIN node. 2023-03-23 00:47:27 +03:00
Dmitry Stogov
ccbf3da286 Add test 2023-03-22 22:09:25 +03:00
Dmitry Stogov
1542048331 Fix TAILCALL on WIN64 2023-03-02 22:08:24 +03:00
Dmitry Stogov
29122c15c3 Add complex WIN64 tests 2023-03-02 17:57:26 +03:00
Dmitry Stogov
c89a038fd3 Fix tests with capstone 5 
Different versions of capstone may disassemble MOVD/MOVQ differentrly
 2023-03-02 17:54:50 +03:00
Dmitry Stogov
5a48805c81 Add support for Windows-64 ABI ("home space") 
Fix parameter passing code to perform sign or zero extension when pass a regiser or a constant

TODO: ARM code maight need similar changes
 2023-03-02 13:27:01 +03:00
Dmitry Stogov
ebdeba9fff Add simple tests for Windows-x86_64 
conv_004.irt and conv_010.irt fail with capstone 5 because of changes in movd/movq
 2023-03-02 00:55:20 +03:00
Dmitry Stogov
00d5e471ad Improve load fusion, register allocateion and code selection for ADD 2023-02-21 22:55:47 +03:00
Dmitry Stogov
2f2fed89bb Uze zero extended "mov" to load 64-bit register ("mov $u32, %r32") 2023-02-17 18:11:13 +03:00
Dmitry Stogov
1d7ab16c2a Allow load fuson for CALL and TAILCALL with arguments 2023-02-14 14:51:12 +03:00
Dmitry Stogov
2e31446e37 Better 'jp' elimination for IR_CMP_AND_BRANCH_FP 2023-02-07 01:57:07 +03:00
Dmitry Stogov
02104b0950 Add XFAIL-ed test for a non-efficient register allocation that should be improved 2023-02-07 00:06:53 +03:00
Dmitry Stogov
54597bc862 Clear destination regeister before INT to FP conversion to avoid partial register stall 2022-12-28 00:05:23 +03:00
Dmitry Stogov
67da9e93ea Fix register clobbering during argument passing and spill load 2022-12-26 20:25:11 +03:00
Dmitry Stogov
d26b162ffa Fix register clobbering during argument passing 2022-12-26 18:27:53 +03:00
Dmitry Stogov
95729f76bf Use IMUL instead of MUL 2022-12-16 12:57:40 +03:00
Dmitry Stogov
efbc51baaa Fixed codegeneration for TRUNC on aarch64 2022-12-07 11:56:53 +03:00
Dmitry Stogov
daf659a457 Fix incorrect conditions 2022-12-01 00:43:42 +03:00
Dmitry Stogov
c6aeb417fa Extend test suite to support XFAIL section 2022-11-22 10:43:29 +03:00
Dmitry Stogov
3e3746d5cb Refactor API that expose target CPU register constraints for register allocator 2022-11-17 23:30:35 +03:00
Dmitry Stogov
05127b1b13 Remove duplicate code and allow load fusion of IR_SHIFT.op2 2022-11-16 13:20:58 +03:00
Dmitry Stogov
673779ba6a Use IR_COPY_INT/FP rule instead of IR_COPY op 2022-11-16 12:55:40 +03:00
Dmitry Stogov
4c536aae20 Extend SCCP to perform Dead Load Elimination 2022-11-08 15:39:00 +03:00
Dmitry Stogov
37dececa71 Add more tests (8 tests ara failed on 32-bit x86) 2022-11-08 11:56:22 +03:00
Dmitry Stogov
2ff0617db6 Perform iterative folding and DCE as a final pass of SCCP 2022-11-08 00:41:08 +03:00